WO1991003078A1 - Insulated gate thyristor with gate turn on and turn off - Google Patents

Insulated gate thyristor with gate turn on and turn off Download PDF

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Publication number
WO1991003078A1
WO1991003078A1 PCT/US1990/004219 US9004219W WO9103078A1 WO 1991003078 A1 WO1991003078 A1 WO 1991003078A1 US 9004219 W US9004219 W US 9004219W WO 9103078 A1 WO9103078 A1 WO 9103078A1
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Prior art keywords
cells
igbt
gate
transistor
turn
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Application number
PCT/US1990/004219
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French (fr)
Inventor
Nathan Zommer
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Ixys Corporation
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Publication of WO1991003078A1 publication Critical patent/WO1991003078A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66363—Thyristors
    • H01L29/66371—Thyristors structurally associated with another device, e.g. built-in diode
    • H01L29/66378—Thyristors structurally associated with another device, e.g. built-in diode the other device being a controlling field-effect device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/744—Gate-turn-off devices
    • H01L29/745—Gate-turn-off devices with turn-off by field effect
    • H01L29/7455—Gate-turn-off devices with turn-off by field effect produced by an insulated gate structure

Definitions

  • the present invention relates generally to semiconductor switching devices and more particularly to such a device based on insulated gate bipolar transistor (IGBT) technology.
  • IGBT insulated gate bipolar transistor
  • the ideal power switching device would be characterized by fast switching speed, low on-resistance, and ease of control.
  • Known power devices include thyristors, which provide very low on-resistance, but reguire special techniques for control; insulated gate bipolar transistors (IGBTs) , which are designed to avoid latch latch-up and are thus easier to turn on and turn off, but have a higher on-resistance than thyristors; and insulated gate field effect transistors (IGFETs) , which are faster than IGBTs but have a higher on- resistance.
  • IGFETs are usually referred to as MOSFETs (metal- oxide-semiconductor field effect transistors) , even though most modern IGFETs have polysilicon rather than metal gates.
  • Thyristors are regenerative devices, which means that they latch on as long as there is a current flowing that is above a certain holding current. A regular thyristor (or SCR) cannot be turned off unless the current that passes is less than the holding current.
  • MOS-controlled thyristor but most reported devices are actually thyristors to which MOSFETs have been added. Such devices typically utilize a MOSFET that is turned on in order to provide an "emitter" short that turns off the thyristor. The idea of using a MOSFET to turn off a thyristor
  • the concept required two gates for the device, one for turn-on (the usual SCR gate) and one for turn-off (the MOSFET gate) .
  • manufacturing the device required the complex task of merging crude thyristor-like semiconductor processing with the high purity, fine geometry requirements of MOSFET processing.
  • the present invention provides a superior insulated gate thyristor (IGTH) that is built on IGBT technology rather than SCR or thyristor technology.
  • the device provides the low on-resistance of a thyristor with the gate turn-on and turn- off capability of an IGBT.
  • the device may be fabricated in a cellular or stripe configuration, using a somewhat modified IGBT process. First, the process is modified (by reduced doping) in order to promote (rather than inhibit) latch-up. Second, certain regions are formed without source diffusions to create a lateral MOSFET that can turn off the latched IGBT.
  • certain of the p/p+ diffusion areas are masked during the n+ source diffusion to create special cells.
  • the gate overlying the region between the special cells and the normal cells provides a lateral p-channel device that provides the turn-off mechanism.
  • the special cells provide an extra vertical PNP bipolar transistor that provides a parallel • conduction path when the thyristor is latched, and aids in the turn-off by diverting current from the thyristor.
  • FIG. 1A is a schematic cross-section of a prior art IGBT structure
  • Fig. IB is a top view showing a possible cell layout of the IGBT of Fig. 1A;
  • Fig. 1C is a top view showing a possible stripe layout of the IGBT of Fig. 1A;
  • Fig. 2 is a schematic of the equivalent circuit of the IGBT of Fig. 1A;
  • Fig. 3A is a schematic cross-section of a cellular embodiment of an insulated gate thyristor (IGTH) according to the present invention
  • Fig. 3B-C are top views showing possible cell layouts for the IGTH of Fig. 3A;
  • Fig. 4 is a schematic of the equivalent circuit of the IGTH of Fig. 3A;
  • Fig. 5A is a schematic cross-section of a stripe embodiment of an IGTH according to the present invention
  • Fig. 5B is a top view showing the stripe layout for the IGTH of Fig. 5A.
  • FIG. 1A is a simplified sectional view of a prior art insulated gate bipolar transistor (IGBT) chip 10.
  • IGBT insulated gate bipolar transistor
  • the active area of a typical chip may consist of hundreds or thousands of microscopically small cells 11, each defining an active device.
  • the chip may be laid out in stripes 11* rather than cells.
  • IGBT 10 is preferably fabricated by a double- diffused MOS (DMOS) process, as is well known in the art.
  • DMOS double- diffused MOS
  • a p+ substrate 12 has its upper surface region doped to define an n-f* layer 15.
  • An n- epitaxial (epi) layer 17 is formed on the surface of the substrate and the active regions are formed therein.
  • a typical cell 11 of the IGBT comprises a p/p+ body 22 formed in epi layer 17 and an n-i- region 25 formed within the perimeter of body 22.
  • Body 22 is p-type over most of its lateral extent with one or more central regions doped p+. The portion of body
  • channel region 27 adjacent the surface and between the source region and the n- epi layer defines a channel region 27.
  • a polysilicon layer 30 overlies the channel region and the regions between cells, and is separated from the epi surface by a thin layer 32 of gate oxide.
  • the polysilicon extends over the surface of the device with an opening at each cell (for source and body metallization) so as to form a common gate electrode for all the cells in the device.
  • Portions 35 of a top metal layer connect n+ region 25 to a common source node S.
  • Other portions 36 of the top metal layer connect the polysilicon layer to a common gate node G».
  • a metal layer 37 is formed on the bottom surface of the substrate to form a bottom electrode E common to all cells of the device.
  • n-channel devices may be briefly outlined as follows:
  • Implant p+ regions within the openings (non-critical alignment) .
  • Fig. IB shows a simplified top view of a typical layout of an embodiment laid out in cells 11.
  • the solid octagon denotes the opening in the gate polysilicon layer while the dashed lines show the channel region under the gate ⁇ (bounded by the p-well boundary and the source region boundary) .
  • This particular type of cell has the n+ source region formed so that the body portion contacts the epi surface in two regions (denoted by solid rectangles) .
  • the contact opening for the source/body contact extends over both these regions and the intermediate n+ region.
  • Fig. 1C shows a simplified top view of an embodiment laid out in stripes ll 1 .
  • the p-well, channel, and source region extend longitudinally.
  • Fig. 2 shows the equivalent circuit of IGBT 10, which consists of an n-channel MOSFET T, a PNP bipolar transistor T 2 , an NPN bipolar transistor T- , and a resistor R.
  • MOSFET T has its drain defined by epi layer 17, its gate by the portions of polysilicon layer 30 that overlie channel region 27, and its source by n+ region 25.
  • PNP transistor T ⁇ has its emitter defined by p+ substrate 12, its base by n+ layer 15 and n- epi layer 17, and a pair of collectors defined by the p+ diffusion in p/p+ body 22 and by the p-portion of the body.
  • NPN transistor T 3 has its emitter defined by n+ region 25, its base by P/P+ body 22, and its collector by n+ layer 15 and n- epi layer 17. Resistor R is defined by p/p+ body 22.
  • Transistors T 2 and T 3 are in a four-layer configuration characteristic of an SCR. In an SCR, resistor R is purposely made high so that current flow through T 2 causes T- to turn on and create a latched condition, characteristic of SCR operation. In an IGBT, however, the latched condition is avoided by making R sufficiently small that the voltage drop across the resistor is never enough to turn transistor T 3 on. Thus transistors T, and T_ are turned on without turning transistor T 3 on, and transistors T ⁇ and T 3 do not latch up.
  • MOSFET T 1 to control the current flow between bottom electrode 37 and source electrode 35.
  • PNP transistor T_ is to reduce the resistivity of the n- epi of MOSFET T., when it is on. This phenomenon is referred to as conductivity modulation, and allows single gate turn-on and turn-off with a lower forward voltage drop than is possible with a comparably rated MOSFET.
  • Fig. 3A is a simplified sectional view of an insulated gate thyristor (IGTH) 40, implemented in a cellular configuration, according to the present invention.
  • IGTH 40 is of similar construction to the cellular version of IGBT 10 except that a number of the cells in the active area are altered to define special cells 50.
  • a special cell 50 differs from a normal IGBT cell 11 in it does not have an n+ region corresponding to n+ region 25.
  • the body of a special cell 50 is denoted as 52. This cell differentiation is readily achieved by masking those cells that are to be special cells during the n+ implant step to prevent the introduction of n- type impurities into the special cell bodies.
  • IGTH 40 also differs from IGBT 10 in that body 22 for the normal cells is less heavily doped so that equivalent resistor R is higher (say by an order of magnitude) .
  • the higher resistance may be achieved by reducing the p+ implant in the body, or by eliminating the p+ implant entirely while increasing the dose for the p implant.
  • the body portions of the special cells may benefit from increased p+ doping.
  • Figs. 3B and 3C show the cell grid with different possible arrangements for the formation of special cells 50.
  • Fig. 3B shows a configuration where 25% of the cells are special cells.
  • Fig. 3C shows a configuration where 50% of the cells are special cells. The significance of this will be described below.
  • Fig. 4 is a schematic of the equivalent circuit of IGTH 40.
  • Cells 11, connected in parallel provide the portions of the structure common with Fig. 2, namely, n-channel MOSFET Tl, PNP and NPN transistors T, and T 3 , and resistor R.
  • Cells 50, connected in parallel define a vertical PNP transistor T 4 and a p-channel MOSFET T 5 .
  • PNP transistor T 4 has its emitter defined by p+ substrate 12, its base by n+ layer 15 and n- epi layer 17, and its collector by p/p-f- body 52.
  • MOSFET T 5 has its source defined by p/p+ body 52, its drain defined by p/p+ body 22, and its channel region defined by those regions 55 of n- epi layer 17 underlying the intercell portions of polysilicon layer 30. Connections are made to bodies 52 of special cells 50, and these are commonly connected to a node designated C, which may or may not be connected to the common source connection S. Fig. 4 shows S and C as separate nodes with an optional connection 55 shown in phantom.
  • the primary design considerations for IGTH relative to standard IGBT processing are as follows. Latch-up (normally avoided in IGBTs) is promoted by decreasing the doping of the IGBT cells 1 bodies. To the extent that departures from the standard IGBT wafer (p+/n+/n- epi) are acceptable, the n+ layer can be less heavily doped or eliminated and the p-t- layer can be more heavily doped, so as to increase the gain of the PNP transistor.
  • the doping in the p/p+ body controls the resistance R and gain of the NPN transistors. Reducing this doping increases R (promoting latch-up) and increases the gain of the NPN transistor. To effect turn-off, p-channel MOSFET T 5 must compete with NPN transistor T 3 .
  • Figs. 3B- C show arrangements with at most 50% special cells, some applications may require more special cells than normal IGBT cells. In fact, if the configuration shown in Fig. 3B were reversed, so that each special cell were a normal cell and each normal cell were a special cell, 75% of the cells would be _ special cells.
  • Fig. 5A is a simplified sectional view of an IGTH 80, implemented in a stripe configuration.
  • Fig. 5B shows a top view.
  • the stripes are fabricated according to generally the same process as described above, with exceptions as noted below.
  • Each stripe comprises a p/p+ body 82, a single n+ source region 85 located near one edge of the body so as to define a single channel 87.
  • Polysilicon 90 overlies the channels and the regions between the bodies, being separated from the silicon surface by gate oxide 92.
  • the overall body doping is reduced to cause latching.
  • the equivalent circuit of IGTH 80 corresponds to that in Fig. 4 except that nodes S and C are shorted together.
  • the present invention provides a new insulated gate thyristor device which is turned on and off by one MOS gate, and acts as a transistor/thyristor combination.
  • the device offers superior functionality over previous MOS-controlled thyristor devices because of its simple gate drive and its simple operation.
  • the device can be used as an IGBT (transistor) or as an IGTH (MOS gated thyristor) , depending on the gate bias current level.
  • IGBT transistor
  • IGTH MOS gated thyristor
  • NMOS process it would be possible to implement the present invention in a PMOS process (where p and n are " interchanged) .
  • the transistor corresponding to T 5 would then be an n-channel device. Since n-channel devices tend to have low resistance, such a variation would probably require a lower fraction of special cells than is needed for the NMOS device.

Abstract

An insulated gate thyristor (IGTH) (40, 80) that is built on IGBT technology rather than SCR or thyristor technology. The device provides the low on-resistance of a thyristor with the gate turn-on and turn-off capability of an IGBT. The device may be fabricated in a somewhat modified IGBT process, in a cellular (40) or stripe (80) configuration. First the process is modified (by reduced doping) in order to promote (rather than inhibit) latch-up. Second, certain regions (52) are formed without source diffusions to create a lateral MOSFET (T5) that can turn off the latched IGBT.

Description

INSULATED GATE THYRISTOR WITH GATE TURN ON AND TURN OFF
BACKGROUND OF THE INVENTION The present invention relates generally to semiconductor switching devices and more particularly to such a device based on insulated gate bipolar transistor (IGBT) technology.
The ideal power switching device would be characterized by fast switching speed, low on-resistance, and ease of control. Known power devices include thyristors, which provide very low on-resistance, but reguire special techniques for control; insulated gate bipolar transistors (IGBTs) , which are designed to avoid latch latch-up and are thus easier to turn on and turn off, but have a higher on-resistance than thyristors; and insulated gate field effect transistors (IGFETs) , which are faster than IGBTs but have a higher on- resistance. IGFETs are usually referred to as MOSFETs (metal- oxide-semiconductor field effect transistors) , even though most modern IGFETs have polysilicon rather than metal gates.
Thyristors are regenerative devices, which means that they latch on as long as there is a current flowing that is above a certain holding current. A regular thyristor (or SCR) cannot be turned off unless the current that passes is less than the holding current. There have been efforts to create a MOS-controlled thyristor, but most reported devices are actually thyristors to which MOSFETs have been added. Such devices typically utilize a MOSFET that is turned on in order to provide an "emitter" short that turns off the thyristor. The idea of using a MOSFET to turn off a thyristor
(or SCR) was introduced by V.A.K. Temple of General Electric.
The concept required two gates for the device, one for turn-on (the usual SCR gate) and one for turn-off (the MOSFET gate) .
However, manufacturing the device required the complex task of merging crude thyristor-like semiconductor processing with the high purity, fine geometry requirements of MOSFET processing.
Merging these two processes resulted in a MOS-controlled thyristor process that was complex, low yielding, and with more masking and diffusion steps than are required for a thyristor or MOSFET separately.
SUMMARY OF THE INVENTION The present invention provides a superior insulated gate thyristor (IGTH) that is built on IGBT technology rather than SCR or thyristor technology. The device provides the low on-resistance of a thyristor with the gate turn-on and turn- off capability of an IGBT. In brief, the device may be fabricated in a cellular or stripe configuration, using a somewhat modified IGBT process. First, the process is modified (by reduced doping) in order to promote (rather than inhibit) latch-up. Second, certain regions are formed without source diffusions to create a lateral MOSFET that can turn off the latched IGBT.
In the context of an n-channel process and a cellular configuration, certain of the p/p+ diffusion areas are masked during the n+ source diffusion to create special cells. The gate overlying the region between the special cells and the normal cells provides a lateral p-channel device that provides the turn-off mechanism. The special cells provide an extra vertical PNP bipolar transistor that provides a parallel • conduction path when the thyristor is latched, and aids in the turn-off by diverting current from the thyristor. The benefits of the present invention are achieved in the context of a known technology, with modifications as outlined above. No extra masking steps are required.
A further understanding of the nature and advantages of the present invention may be realized by reference to the remaining portions of the specification and the attached drawings.
BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a schematic cross-section of a prior art IGBT structure;
Fig. IB is a top view showing a possible cell layout of the IGBT of Fig. 1A;
Fig. 1C is a top view showing a possible stripe layout of the IGBT of Fig. 1A;
Fig. 2 is a schematic of the equivalent circuit of the IGBT of Fig. 1A;
Fig. 3A is a schematic cross-section of a cellular embodiment of an insulated gate thyristor (IGTH) according to the present invention;
Fig. 3B-C are top views showing possible cell layouts for the IGTH of Fig. 3A;
Fig. 4 is a schematic of the equivalent circuit of the IGTH of Fig. 3A;
Fig. 5A is a schematic cross-section of a stripe embodiment of an IGTH according to the present invention; and Fig. 5B is a top view showing the stripe layout for the IGTH of Fig. 5A.
DESCRIPTION OF SPECIFIC EMBODIMENTS Fig. 1A is a simplified sectional view of a prior art insulated gate bipolar transistor (IGBT) chip 10. As shown in*. Fig. IB and as will be discussed below, the active area of a typical chip may consist of hundreds or thousands of microscopically small cells 11, each defining an active device. For the IGBT shown, all the cells are the same and are connected in parallel. As shown in Fig. 1C, the chip may be laid out in stripes 11* rather than cells. IGBT 10 is preferably fabricated by a double- diffused MOS (DMOS) process, as is well known in the art. (As alluded to above, the use of the term "MOS" or "MOSFET" is not intended to imply a metal gate) . A p+ substrate 12 has its upper surface region doped to define an n-f* layer 15. An n- epitaxial (epi) layer 17 is formed on the surface of the substrate and the active regions are formed therein. A typical cell 11 of the IGBT comprises a p/p+ body 22 formed in epi layer 17 and an n-i- region 25 formed within the perimeter of body 22. Body 22 is p-type over most of its lateral extent with one or more central regions doped p+. The portion of body
22 adjacent the surface and between the source region and the n- epi layer defines a channel region 27.
A polysilicon layer 30 overlies the channel region and the regions between cells, and is separated from the epi surface by a thin layer 32 of gate oxide. The polysilicon extends over the surface of the device with an opening at each cell (for source and body metallization) so as to form a common gate electrode for all the cells in the device. Portions 35 of a top metal layer connect n+ region 25 to a common source node S. Other portions 36 of the top metal layer connect the polysilicon layer to a common gate node G». A metal layer 37 is formed on the bottom surface of the substrate to form a bottom electrode E common to all cells of the device.
The fabrication process for n-channel devices may be briefly outlined as follows:
(1) Dope upper portion of p+ substrate n+.
(2) Grow n- epitaxial layer. (3) Grow localized field oxide to define peripheral non-active areas of the chip.
(4) Deposit gate oxide.
(5) Deposit polysilicon over gate oxide.
(6) Create openings in the polysilicon and gate oxide to define the cells.
(7) Implant p-type dopants aligned to polysilicon openings.
(8) Implant p+ regions within the openings (non-critical alignment) . (9) Diffuse to form p-well (body) .
(10) Mask at least portions of p+ diffusion and implant n+.
(11) Diffuse to form source regions and channel regions. (12) Deposit CVD oxide over wafer.
(13) Etch poly contacts and source/body contacts.
(14) Deposit metal layer.
(15) Etch metal layer to define gate electrode and source/body electrode. (16) Passivate.
Fig. IB shows a simplified top view of a typical layout of an embodiment laid out in cells 11. The solid octagon denotes the opening in the gate polysilicon layer while the dashed lines show the channel region under the gate ■ (bounded by the p-well boundary and the source region boundary) . This particular type of cell has the n+ source region formed so that the body portion contacts the epi surface in two regions (denoted by solid rectangles) . The contact opening for the source/body contact extends over both these regions and the intermediate n+ region. This type of cell is described in Application Serial No. 166,809, filed March 10, 1988, now U.S. Patent 4,860,072. Fig. 1C shows a simplified top view of an embodiment laid out in stripes ll1. In this embodiment, the p-well, channel, and source region extend longitudinally.
Fig. 2 shows the equivalent circuit of IGBT 10, which consists of an n-channel MOSFET T,, a PNP bipolar transistor T2, an NPN bipolar transistor T- , and a resistor R. MOSFET T, has its drain defined by epi layer 17, its gate by the portions of polysilicon layer 30 that overlie channel region 27, and its source by n+ region 25. PNP transistor T~ has its emitter defined by p+ substrate 12, its base by n+ layer 15 and n- epi layer 17, and a pair of collectors defined by the p+ diffusion in p/p+ body 22 and by the p-portion of the body. NPN transistor T3 has its emitter defined by n+ region 25, its base by P/P+ body 22, and its collector by n+ layer 15 and n- epi layer 17. Resistor R is defined by p/p+ body 22. Transistors T2 and T3 are in a four-layer configuration characteristic of an SCR. In an SCR, resistor R is purposely made high so that current flow through T2 causes T- to turn on and create a latched condition, characteristic of SCR operation. In an IGBT, however, the latched condition is avoided by making R sufficiently small that the voltage drop across the resistor is never enough to turn transistor T3 on. Thus transistors T, and T_ are turned on without turning transistor T3 on, and transistors T~ and T3 do not latch up. This allows MOSFET T1 to control the current flow between bottom electrode 37 and source electrode 35. The effect of PNP transistor T_ is to reduce the resistivity of the n- epi of MOSFET T., when it is on. This phenomenon is referred to as conductivity modulation, and allows single gate turn-on and turn-off with a lower forward voltage drop than is possible with a comparably rated MOSFET.
Fig. 3A is a simplified sectional view of an insulated gate thyristor (IGTH) 40, implemented in a cellular configuration, according to the present invention. IGTH 40 is of similar construction to the cellular version of IGBT 10 except that a number of the cells in the active area are altered to define special cells 50. A special cell 50 differs from a normal IGBT cell 11 in it does not have an n+ region corresponding to n+ region 25. The body of a special cell 50 is denoted as 52. This cell differentiation is readily achieved by masking those cells that are to be special cells during the n+ implant step to prevent the introduction of n- type impurities into the special cell bodies. IGTH 40 also differs from IGBT 10 in that body 22 for the normal cells is less heavily doped so that equivalent resistor R is higher (say by an order of magnitude) . The higher resistance may be achieved by reducing the p+ implant in the body, or by eliminating the p+ implant entirely while increasing the dose for the p implant. The body portions of the special cells may benefit from increased p+ doping.
Figs. 3B and 3C show the cell grid with different possible arrangements for the formation of special cells 50. Fig. 3B shows a configuration where 25% of the cells are special cells. Fig. 3C shows a configuration where 50% of the cells are special cells. The significance of this will be described below.
Fig. 4 is a schematic of the equivalent circuit of IGTH 40. Cells 11, connected in parallel, provide the portions of the structure common with Fig. 2, namely, n-channel MOSFET Tl, PNP and NPN transistors T, and T3, and resistor R. Cells 50, connected in parallel define a vertical PNP transistor T4 and a p-channel MOSFET T5. PNP transistor T4 has its emitter defined by p+ substrate 12, its base by n+ layer 15 and n- epi layer 17, and its collector by p/p-f- body 52. MOSFET T5 has its source defined by p/p+ body 52, its drain defined by p/p+ body 22, and its channel region defined by those regions 55 of n- epi layer 17 underlying the intercell portions of polysilicon layer 30. Connections are made to bodies 52 of special cells 50, and these are commonly connected to a node designated C, which may or may not be connected to the common source connection S. Fig. 4 shows S and C as separate nodes with an optional connection 55 shown in phantom. Consider first the operation of IGTH 40 when a positive voltage (say +15 volts) is applied to gate node G». This causes MOSFET Tχ to turn on, and due to the modified IGBT cell doping, causes bipolar transistors , and T3 (the inherent SCR) to latch. (As noted above, the emphasis in normal IGBT design is to avoid a latched condition) .
Consider next the operation of IGTH 40 when a negative voltage relative to S, (say -15 volts) is applied to the gate electrode. This causes the surface of the n- epi layer under the polysilicon (region 55) to invert and thereby define a p-channel, which turns MOSFET T5 on. Turning MOSFET 5 on acts to divert base current from the base of transistor T3 by shorting the resistor, which tends to turn transistor T3 off, thus reversing the latched condition. If nodes C and S are connected, the result is a 3- pin device. On the other hand, if node C is brought out as a separate pin, the turn-off operation can be enhanced since node C can be biased more negatively than node S during turn-off. The primary design considerations for IGTH relative to standard IGBT processing are as follows. Latch-up (normally avoided in IGBTs) is promoted by decreasing the doping of the IGBT cells1 bodies. To the extent that departures from the standard IGBT wafer (p+/n+/n- epi) are acceptable, the n+ layer can be less heavily doped or eliminated and the p-t- layer can be more heavily doped, so as to increase the gain of the PNP transistor. The doping in the p/p+ body controls the resistance R and gain of the NPN transistors. Reducing this doping increases R (promoting latch-up) and increases the gain of the NPN transistor. To effect turn-off, p-channel MOSFET T5 must compete with NPN transistor T3. Since the on-resistance of one cell of p-channel MOSFET T5 is greater than that of one cell of n- channel MOSFET T« and much greater than that of one cell of the bipolar devices, a significant number of the special cells may be needed. The relative occurrence of special cells determines forward voltage drop, switching time, and maximum latched current that can be switched off by the gate. While Figs. 3B- C show arrangements with at most 50% special cells, some applications may require more special cells than normal IGBT cells. In fact, if the configuration shown in Fig. 3B were reversed, so that each special cell were a normal cell and each normal cell were a special cell, 75% of the cells would be _ special cells.
Fig. 5A is a simplified sectional view of an IGTH 80, implemented in a stripe configuration. Fig. 5B shows a top view. The stripes are fabricated according to generally the same process as described above, with exceptions as noted below. Each stripe comprises a p/p+ body 82, a single n+ source region 85 located near one edge of the body so as to define a single channel 87. Polysilicon 90 overlies the channels and the regions between the bodies, being separated from the silicon surface by gate oxide 92. As in the case of the cellular implementation, the overall body doping is reduced to cause latching. The equivalent circuit of IGTH 80 corresponds to that in Fig. 4 except that nodes S and C are shorted together.
In conclusion, it can be seen that the present invention provides a new insulated gate thyristor device which is turned on and off by one MOS gate, and acts as a transistor/thyristor combination. The device offers superior functionality over previous MOS-controlled thyristor devices because of its simple gate drive and its simple operation. Still, the device can be used as an IGBT (transistor) or as an IGTH (MOS gated thyristor) , depending on the gate bias current level. Moreover, this ability to create different degrees of transistor versus thyristor action is achieved without increasing the number of processing steps in the fabrication of the device. While the above is a full description of the preferred embodiments, various modifications, alternative constructions, and equivalents may be used. For example, while the description above is in terms of an NMOS process, it would be possible to implement the present invention in a PMOS process (where p and n are" interchanged) . The transistor corresponding to T5 would then be an n-channel device. Since n-channel devices tend to have low resistance, such a variation would probably require a lower fraction of special cells than is needed for the NMOS device.
Therefore, the above description and illustrations should not be taken as limiting the scope of the present invention which is defined by the appended claims.

Claims

WHAT IS CLAIMED IS:
1. An insulated gate thyristor semiconductor device comprising: a semiconductor chip having an n-type top portion bounded by a top surface and a p-type substrate; a first set of IGBT cells formed in said top portion, each of said IGBT cells having a p-type body and an n-type source region formed within the periphery of the said body to define a channel between the source region and the body periphery; a plurality of special cells formed in said top portion and interspersed with said IGBT cells, each special cell having a p-type body portion, but no n-type source region; a conductive gate layer insulated from said top surface, said gate layer overlying said channels in said IGBT cells, portions of said bodies in said special cells, and regions between the bodies of said IGBT cells and the bodies of said special cells; said IGBT cells defining an n-channel MOSFET, a PNP bipolar transistor and an NPN bipolar transistor; the combination of said special cells and at least some of said IGBT cells defining a p-channel MOSFET operable to divert base current from said NPN bipolar transistor.
2. An integrated circuit structure having an equivalent circuit comprising: an n-channel MOSFET T1 having a drain, a gate, and a source; first and second PNP bipolar transistors T, and T * t each having an emitter, a base, and a collector. an NPN bipolar transistor 3 having an emitter, a base, and a collector; a p-channel MOSFET T*- having drain, gate, and source, electrodes and a resistor; and a resistor R having first and second ends; the emitters of PNP transistors T~ and T. being commonly connected to a node E; the drain of MOSFET T, , the bases of PNP transistors T- and T., and the collector of NPN transistor T3 being commonly connected; the collector of PNP transistor T2, the base of NPN transistor T3, the source of p-channel MOSFET T*5, and the first end of resistor R being commonly connected; the source of n-channel MOSFET T, , the emitter of NPN transistor T3, and the second end of resistor R being commonly connected; resistor R being connected between the collector of PNP transistor T2 and the emitter of NPN transistor T3; the drain of p-channel MOSFET T5 and the collector of PNP transistor T. being connected in common.
3. The device of claim 2 wherein the source of MOSFET T-^ and the drain of p-channel MOSFET T5 are commonly connected.
PCT/US1990/004219 1989-08-17 1990-07-27 Insulated gate thyristor with gate turn on and turn off WO1991003078A1 (en)

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US39539889A 1989-08-17 1989-08-17
US395,398 1989-08-17
US54227390A 1990-06-22 1990-06-22
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EP0476815A2 (en) * 1990-08-18 1992-03-25 Mitsubishi Denki Kabushiki Kaisha Thyristor and method of manufacturing the same
DE4207569A1 (en) * 1991-03-14 1992-09-17 Fuji Electric Co Ltd CONTROLLABLE THYRISTOR WITH INSULATED GATE AND METHOD FOR THE PRODUCTION THEREOF
EP0529322A1 (en) * 1991-08-16 1993-03-03 Asea Brown Boveri Ag MOS-controlled thyristor (MCT)
US5194927A (en) * 1990-08-16 1993-03-16 Fuji Electric Co., Ltd. Semiconductor device
EP0538282A1 (en) * 1990-06-14 1993-04-28 North Carolina State University Gated base controlled thyristor
DE4135411A1 (en) * 1991-10-26 1993-04-29 Asea Brown Boveri DISABLED PERFORMANCE SEMICONDUCTOR COMPONENT
US5296725A (en) * 1992-06-10 1994-03-22 North Carolina State University At Raleigh Integrated multicelled semiconductor switching device for high current applications
EP0645053A1 (en) * 1991-12-23 1995-03-29 Harris Corporation Field effect transistor controlled thyristor having improved turn-on characteristics
US5489789A (en) * 1993-03-01 1996-02-06 Kabushiki Kaisha Toshiba Semiconductor device
US5644150A (en) * 1994-03-28 1997-07-01 Fuji Electric Co., Ltd. Insulated gate thyristor
EP0889531A1 (en) * 1997-06-30 1999-01-07 Asea Brown Boveri AG MOS-controlled semiconductor device

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EP0538282A4 (en) * 1990-06-14 1993-10-06 North Carolina State University Gated base controlled thyristor
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EP0889531A1 (en) * 1997-06-30 1999-01-07 Asea Brown Boveri AG MOS-controlled semiconductor device

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