WO1991012497A1

WO1991012497A1 - Crystal-oriented motion sensor and process for manufacturing it

Info

Publication number: WO1991012497A1
Application number: PCT/DE1991/000058
Authority: WO
Inventors: Jiri Marek; Martin Warth; Guenther Findler; Hans-Peter Trah
Original assignee: Robert Bosch Gmbh
Priority date: 1990-02-06
Filing date: 1991-01-22
Publication date: 1991-08-22
Also published as: DE4003473C2; JPH05503994A; EP0514395A1; DE4003473A1

Abstract

A motion sensor, in particular for measuring oscillating, tilting or accelerated motion, is manufactured from a monocrystalline silicon wafer. At least one vertical paddle perpendicular to the wafer surface, which is capable of oscillating in the plane of the wafer, is etched out of the silicon wafer. Means for evaluating the deflection of the at least one paddle are also provided. The front face and rear face of the silicon wafer are (110) surfaces and the delimiting side walls of the etched depression are (111) surfaces. The at least one paddle is arranged in function of the crystallographic angles which form the (111) planes with and in the (110) plane.

Description

Crystal-oriented motion sensor and method for its production

State of the art

The invention relates to a sensor for measuring motion according to the preamble of the main claim.

Acceleration sensors based on silicon micromechanics are already known from patent application P 38 14 952, in which a paddle which is suspended from one or more webs is deflected perpendicularly to the wafer surface. The deflection is evaluated piezoresistively. Due to the required seismic mass and the direction of movement of the paddle, such sensors occupy a relatively large part of the wafer surface.

From the unpublished patent application P 39 27 163 it is known that structures can be etched out in semiconductor wafers with the aid of photomasking technology. In particular, tongues or paddles can be exposed by isotropic wet chemical undercutting of webs. Advantages of the invention

The fiction, contemporary sensor with the characterizing features of the main claim has the advantage that it is very easy to implement sensors with a small chip surface by taking advantage of the natural crystallographic surfaces of the monocrystalline silicon wafer in the arrangement and dimensioning of the sensor paddles vertically to the wafer surface. In this context, it has proven to be advantageous that the sensor paddles vibrate in the chip plane and are thus protected by the chip even in the event of an overload. A further advantage is that the capacitive evaluation of the sensor signals requires small trench widths, which are particularly easy to manufacture when using the (111) crystal planes as vertical etch stop boundaries for the lateral undercut.

Advantageous further developments of the sensor specified in the main claim are possible through the measures listed in the subclaims. In silicon wafers with (100) surfaces, sensors can advantageously be etched out, the evaluation of which is carried out capacitively, as well as those whose evaluation is piezoresistive. A particular advantage of the capacitive sensors is that ^* the working capacity can be increased as required by connecting several capacitors in parallel. If the (111) crystal planes perpendicular to the wafer surface are used as the etch stop limit for the lateral undercut, etch trenches with an aspect ratio of up to 100: 1 can be produced, which is particularly advantageous since it can be used to produce paddles which have a very low rigidity exhibit. Another advantage is that, due to the high aspect ratio, the entire thickness of the wafer can be etched through. Paddles and electrodes with a particularly large working capacity can be manufactured with a small footprint. Sensor structures in wafers that consist of a silicon substrate and one applied to it can also be advantageously implemented There are epitaxial layers, a pn junction occurring between the substrate and the epitaxial layer due to their different doping. Alternatively, a p / n junction can also advantageously be introduced into a p- or n-doped wafer by means of a corresponding diffusion. If this pn junction is polarized in the reverse direction, it serves on the one hand as an etching stop and on the other hand it has an insulating effect on the substrate. Within the epitaxial layer, the sensor structure can be isolated particularly advantageously either by means of a pn junction, which is polarized in the reverse direction, as well as by means of an isolation trench which completely penetrates the epitaxial layer and extends into the silicon substrate. The paddles can advantageously be exposed either by isotropic wet-chemical undercutting of webs from the front of the wafer or by means of a backside etching. A particular advantage of taking advantage of the crystallographic conditions is to select a simple parallelogram as the etching window for the rear side etching, the angles of which have the same dimensions as the angles which form the (111) planes in the (110) wafer surface. In the case of capacitively operating sensors, it is advantageous if the fixed electrodes are not completely exposed by a rear side etching, but are connected to the silicon substrate at their two ends.

A particular advantage in the production of sensors according to the invention proves that when using KOH or other alkalis, dielectrics known as etches can be used as the masking layer. Another advantage of producing sensor structures in (IΙO) wafers using the crystallographic conditions by anisotropic wet chemical etching is that a combined etching attack from the front and back is possible. drawing

Embodiments of the invention are shown in the drawing and explained in more detail in the following description.

FIG. 1 shows the top view of a sensor, FIG. 2 shows the top view of a further sensor and FIG.

Description of the invention

1 shows a silicon wafer 10 with the crystallographic orientation of the surface of (110). The silicon wafer 10 in this exemplary embodiment can have a uniform doping or else consist of a silicon substrate and an epitaxial layer applied thereon, at whose interface there is a pn junction due to the different doping of the substrate and the epitaxial layer. In this context, the p / n transition is essential. B. can also be generated by diffusion of foreign atoms in the silicon wafer. In an etched trench 20, which has the shape of a parallelogram according to the invention with the corner angles 70.53 ° and 109.47 °, paddles 151, 152, 153 and rigid electrodes 161, 162, 163, which can vibrate, protrude in the wafer plane.

When anisotropically etching silicon in K0H, (111) planes are etched particularly slowly. On (110) wafers, the (111) planes are perpendicular to the wafer surface and therefore allow deep trenches with a high aspect ratio to be etched. Deep etching can be achieved a hundred times faster than lateral etching.

However, the implementation of deep trench structures on silicon wafers with (110) orientation requires compliance with certain ones Design rules based on crystallography. The vertical (111) planes, which are used as etching-limiting walls, form angles of 70.53 ° and 109.47 ° with one another in the (110) plane. Undercutting of the mask can largely be avoided only if these angles are exactly observed in the design of the etching mask. In this context, the exact adherence to the mask alignment on the wafer surface with regard to the crystallographic orientation is of crucial importance. Only through this adjustment accuracy can it be ensured that the vibratable paddles are not completely etched away during the etching by under-etching the etching mask.

Compliance with the required accuracy of adjustment requires an accuracy of the Fiat misorientation of <= + 0.1 °. If this is not guaranteed, the use of an adjustment mask becomes necessary, or the flat misorientation must be compensated for by misorientation of the etching mask with respect to the Fiat.

In addition to the perpendicular (III) planes, oblique silicon areas 141 are also formed in the acute angles of the parallelogram with an angle of inclination to the wafer surface of 35.26 °. At the obtuse angles, oblique silicon areas are also formed on the bottom of the etching pit (FIG. 2). The inclined silicon surfaces 141 make design reservations necessary because they can restrict the movement of the paddles 151, 152, 153.

The aspect ratio in the anisotropic wet chemical etching of (IΙO) wafers is so high that it is possible to etch through the entire wafer. For example, a combined etching attack from the front and back can be implemented. In this case, the height of the paddles or the depth of the etched trenches corresponds to the entire thickness of the wafer. The paddles and electrodes are isolated by The structures are separated from the silicon wafer, for example by sawing. For this purpose, the sensor should be applied beforehand, for example by anodic bonding, to a carrier made of a suitable material such as silicon or glass, it being important to note that the paddles remain capable of vibrating. This can be achieved, for example, by means of a cavern in the carrier or Si wafer or else by means of selective epitaxy.

FIG. 2 shows a sensor structure in which vibratable paddles 161, 162 are formed within the epitaxial layer. A fixed electrode 151, 152 is assigned to each of the paddles 161, 162, so that each pair of electrode paddles forms a capacitance. The two capacitances shown are connected in parallel with a conductive connection 256 for the movable electrodes and a further conductive connection 255 for the fixed electrodes. This has the advantage that the working capacity can be increased as desired. An isolation trench 21 provides electrical isolation of the sensor structure within the expitaxial layer. The isolation trench 21, which is also etched from the front during the structuring of the paddles, penetrates completely through the epitaxial layer and extends into the silicon substrate. Just like the isolation of the sensor structure from the silicon substrate, the isolation of the sensor structure can also take place within the epitaxial layer by means of a reverse pn junction.

The parallelogram denoted by 22 represents the starting surface for the rear side etching, which takes place starting from the rear side of the silicon wafer 10 up to the pn junction, which serves as the etching stop limit in the reverse direction. At the base of the etching pit, directly below the epitaxial layer, This results in obliquely lying silicon surfaces 141 in the acute angles of the parallelogram and 142 in the obtuse angles of the parallelogram. The location of the sloping Silicon surfaces 141 lying in the acute angles of the parallelogram are characterized by the size x in FIG. It depends on the etching depth t of the backside etching and results from crystallographic considerations of x = 1, 633t. For the size y, which characterizes the position of the sloping silicon surfaces 142 in the obtuse angles of the parallelogram, one finds empirically the etching in 30% KOH at 80 ° C y = 0.544 t. In contrast to the large x, which is solely due to crystallography, y depends on the etching conditions. When arranging and dimensioning the paddles 161, 162, the inclined silicon surfaces 141, 142 must be taken into account, since their position at the base of the rear-side etching pit can hinder the swinging of the paddles 161, 162. The fixed electrodes 151, 152 are only exposed by the rear side etching 22 in a central region. At their end, they are at least at a length d that corresponds to the thickness of the epitaxial layer, but are usually connected to the substrate in a length of 2d. This measure is intended to ensure the immobility of the electrodes 151, 152.

FIG. 3 shows a silicon wafer with a (110) crystal orientation, from which a sensor structure according to the invention is etched out, at various stages of the method.

FIG. 3a shows the silicon wafer 10, which consists of a silicon substrate 12 and an epitaxial layer 13 applied thereon. At the interface between the epitaxial layer 13 and the silicon substrate 12 there is a pn junction due to their different doping, which can be polarized in the reverse direction by means of a pn etching connection 27. To passivate the surface, there is a silicon oxide layer 311 on the epitaxial layer, which contains only recesses for the pn-etching connection 27 and a contact 26. The contact 26 serves for the electrical connection of the sensor. Both contact 26 and pn-etch connection 27 are in a plasma nitride layer 321 is embedded so that only a small recess remains. The recess in the plasma nitride layer 321 above the contact 26 is covered by a low-temperature oxide layer 331. The pn-etching connection 27 is exposed through a recess 23. A plasma nitride layer 322 is applied to mask the back of the silicon wafer 10, since a simple thermal oxide has an etching rate that is too high and would therefore not withstand etching with KOH. A silicon oxide layer 312 is located between the plasma nitride layer 322 and the silicon substrate 12 in order to avoid stresses between the silicon substrate 12 and the plasma nitride layer 322.

The front and rear sides of the silicon wafer 10 are structured using means of photo masking technology. The resulting recesses 23 in the silicon oxide layer 311 on the front side of the silicon wafer 10 and the recess 22 for the etching of the rear side in the plasma nitride layer 322 and the silicon oxide layer 312 are shown in FIG. 3b.

When the back of the silicon wafer 10 is etched with KOH, etching-limiting walls which are perpendicular to the (110) surface of the silicon wafer 10 and are (111) planes are formed. The pn junction between the silicon substrate 12 and the epitaxial layer 13, which is polarized in the reverse direction via the pn-etching connection 27, serves as the etching stop for the etching of the rear side. In FIG .

The front is etched in a further process step. The etching stop results from the duration of the etching treatment, which is chosen such that the isolation trench 21, which is not opposite the backside etching 22, completely penetrates the epitaxial layer 13 and extends into the silicon substrate 12. The etched trenches 20, which lie opposite the rear side etching 22, form until they encounter the low-temperature oxide layer 332, which serves to passivate the rear side of the silicon wafer 10. The silicon wafer 10 at this stage is shown in Figure 3d.

To expose a paddle 15, the low-temperature oxide layer 332 and 331 on the back and the front of the silicon wafer 10 are removed. In addition, the silicon oxide layer 311 on the front side of the silicon wafer 10 is removed in the sensor region. In addition to the vibratable paddle 15, two fixed electrodes 161, 162 have been created. To connect the sensor structure to an evaluation circuit, the contact 26 was exposed by removing the plasma nitride layer 321, so that the desired sensor structure of FIG. 3e is produced.

For the implementation of capacitive acceleration sensors, the etching of the rear and the front are carried out in an aligned manner.

Claims

Expectations

1. Sensor for motion measurement, in particular for vibration, inclination or acceleration measurement, the sensor being produced from a monocrystalline silicon wafer (10), from which at least one paddle (15) which is oscillatable in the wafer plane and is arranged vertically to the wafer surface is etched out, and with means for evaluating the deflection of the at least one paddle (15), characterized in that the front and the back of the silicon wafer (10) are (110) surfaces, that the lateral boundary walls of the etching trenches (111) are ^" surfaces, and that When arranging the at least one paddle (15), the crystallographic angles that form the (111) planes with and in the (110) plane are taken into account.

2. Sensor according to claim 1, characterized in that the evaluation of the deflection takes place capacitively or piezoresistively.

3. Sensor according to claim 1 or 2, characterized in that a fixed electrode (16) is arranged opposite the at least one paddle (15) and that the paddle (15) and electrode (16) are electrically insulated from one another.

4. Sensor according to any one of the preceding claims, characterized gekenn¬ characterized in that a plurality of paddles (151, 152, 153) each face a fixed electrode (161, 162, 163) and that both the paddles (151, 152) and the electrodes (161, 162) are contacted via a conductive connection (255, 256), so that the capacitances formed by the paddles (151, 152) and the associated electrodes (161, 162) are connected in parallel.

5. Sensor according to one of the preceding claims, characterized gekenn¬ characterized in that the sensor structure is applied to a carrier, preferably by anodic bonding, that there is a distance between the carrier and the at least one paddle (15), and that the distance between the carrier and the at least one paddle (15) is produced by etching the underside of the paddle or the carrier or by selective epitaxy.

6. Sensor according to one of the preceding claims, characterized gekenn¬ characterized in that the at least one paddle (15) has a wafer thickness and that the isolation of the sensor structure by separating the sensor structure from the silicon wafer (10), preferably by sawing.

7. Sensor according to one of claims 1 to 4, characterized in that the Si wafer (10) has a lower layer and an upper layer, between which a p / n transition occurs, that the lower layer by a p or n-doped Si substrate (12) is formed and that the upper layer with a doping opposite to the Si substrate (12) is either produced by diffusion or is an epitaxial layer applied to the Si substrate (12).

8. Sensor according to claim 7, characterized in that the at least one paddle (15) is formed within a layer, preferably the upper layer.

9. Sensor according to one of claims 7 or 8, characterized in that the isolation of the sensor structure from the silicon substrate (12) by a reverse polarized pn junction and that the isolation within the upper layer by a reverse polarity pn junction or by means of an insulation trench which completely penetrates the upper layer and extends into the silicon substrate (12).

10. Sensor according to one of claims 7 to 9, characterized in that the at least one paddle (15) is exposed starting from an undercut from the front of the silicon wafer (10).

11. Sensor according to one of claims 7 to 9, characterized in that the at least one paddle (15) is exposed by a rear side etching (22) and that the starting surface of the rear rare etching (22) has the shape of a simple parallelogram, the angle of which die have the same dimensions as the angles that the (111) planes form in the (110) plane.

12. Sensor according to claim 11, characterized in that the at least one paddle (15) is arranged such that the oblique silicon surfaces (depending on the etching depth) forming in the corners of the parallelogra-shaped starting surface when etching the back of the silicon wafer (10) 141, 142) do not hinder the movement of the paddle.

13. Sensor according to one of claims 11 or 12, characterized gekenn¬ characterized in that the electrode (16) is exposed only in a central region of the rear side etching (22), so that the electrode (16) at its two ends with the silicon substrate (12) is connected.

14. A method for producing a sensor for motion measurement according to one of claims 11 to 13, characterized in that the rear side etching (22) using the photo masking technique by anisotropic wet chemical etching in the silicon wafer (10) It is introduced that a pn junction between the silicon substrate (12) and the upper layer, which is polarized in the reverse direction, serves as the etching stop during the etching of the rear side, and that the etching of the front side takes place anisotropically, wet-chemically with the aid of the photomasking technique.

15. The method according to claim 14, characterized in that KOH or other anisotropically corrosive hydroxides, preferably NaOH or NH.OH, are used as etches, that a plasma nitride layer (322) in conjunction with a silicon oxide layer as a masking of the rear side of the silicon wafer (10) (312) is used and that the finished etched back of the silicon wafer (10) is passivated with a low-temperature oxide layer (332).

16. The method according to claim 14 or 15, characterized in that the front of the silicon wafer (10) with a silicon oxide layer (311) is passivated and that the depth of the etching trenches (20) and the isolation trench (21) by the duration of the etching treatment is determined.

17. The method according to claim 14 to 16, characterized in that the etching of the front and the back of the silicon wafer (10) takes place simultaneously.