WO1991016726A1 - Multilayer circuit board for mounting ic and manufacture thereof - Google Patents

Multilayer circuit board for mounting ic and manufacture thereof Download PDF

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Publication number
WO1991016726A1
WO1991016726A1 PCT/JP1991/000523 JP9100523W WO9116726A1 WO 1991016726 A1 WO1991016726 A1 WO 1991016726A1 JP 9100523 W JP9100523 W JP 9100523W WO 9116726 A1 WO9116726 A1 WO 9116726A1
Authority
WO
WIPO (PCT)
Prior art keywords
conductive
circuit board
mounting
bump
multilayer circuit
Prior art date
Application number
PCT/JP1991/000523
Other languages
English (en)
French (fr)
Inventor
Yasuyuki Tanaka
Chikafumi Oomachi
Original Assignee
Nippon Mektron, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Mektron, Ltd. filed Critical Nippon Mektron, Ltd.
Publication of WO1991016726A1 publication Critical patent/WO1991016726A1/ja
Priority to US08/011,004 priority Critical patent/US5317801A/en

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    • H—ELECTRICITY
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/043—Reflowing of solder coated conductors, not during connection of components, e.g. reflowing solder paste
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Definitions

  • the present invention relates to a multi-layer circuit board for mounting an IC, which is configured such that an IC bare chip can be directly mounted on a multi-layer circuit board formed using a flexible circuit board and the like, and a manufacturing method therefor. More specifically, is the present invention a required part of a multilayer circuit board? An L portion is formed, and a conductive bump member protruding outside the circuit board is formed in cooperation with a plating means or a filling means of a conductive member applied to the perforated portion, and the circuit board is formed by the conductive bump member.
  • the present invention relates to a multilayer circuit board for mounting Ic, which is configured to ensure reliable electrical connection between a desired conductive layer and a pad of an IC bare chip, and a suitable manufacturing method therefor.
  • a tab method using a protruding lead finger is well known, but this method is mainly used for a single-layer circuit board.
  • inner and outer conductive layers 2 to 7 each having a required circuit wiring pattern are laminated via an appropriate insulating base material.
  • the flexible multi-layer circuit board 1 by the flip-chip method is manufactured, and the IC bare chip 9 is connected to the connection end portions 2A and 3A of the outer conductive layers 2 and 3 via bumps 9A and 9B, respectively. Connected.
  • the outer conductive layer 2 is connected to the other outer conductive layer 6 at the through-hole conductive portion 8 without conducting with the inner conductive layer 4, and the other outer conductive layer 3 is The other inner conductive layer 5 and the outer conductive layer 7 are electrically connected to each other at a through-hole conductive portion 8A.
  • These through-hole conducting portions 8 and 8 A are connection bars for the IC bare chip 9.
  • the lamps 9A and 9B and the connection ends 2A and 3A are formed at positions appropriately separated from the connection ends 2A and 3A. Since the connection ends 2 A and 3 A of the circuit board 1 and the connection bumps 9 A and 9 B of the IC bare chip 9 are generally connected to each other by soldering, the flexibility of the flip-chip structure is used. Even in the case of the flexible multi-layer circuit board 1, a solder flow prevention dam 10.0.10A is arranged around the connection ends 2A and 3A.
  • the through-hole conducting portions 8 and 8 A for interconnecting the inner and outer conductive layers are mounted with the IC bare chip 9. It is difficult to dispose the IC bare chip 9 at a high density because it is difficult to dispose the IC bare chip 9 at this location because of the difficulty of the through hole conduction structure and the necessity of providing the solder flow prevention dams 10 and 10A. Since the configuration on the circuit board 1 is accompanied by great restrictions, the circuit board 1 of this type generally has a large size in addition to the mounting density of the IC bare chip 9, and the bumps 9A and 9B for interconnection also have an IC base. It is necessary to arrange on the side of the chip 9, and together with the many steps for that and the necessity of the solder flow prevention dam as described above, the cost associated with the Ic mounting method by this method can be avoided. Absent.
  • a hole for making electrical connection with a desired conductive layer of a multilayer circuit board is formed in a required portion of the circuit board.
  • the conductor projecting out of the circuit board in cooperation with the plating means applied to the L part or the filling means of the conductive member A multi-layer circuit board for mounting Ic is formed in which an electrically conductive bump member is formed, and the electrically conductive bump member is used to ensure reliable electrical connection between a desired conductive layer of the circuit board and a pad of the IC bare chip. It was fabricated and configured so that the Ic bare chip could be easily and quickly mounted on the bump member formed on this multi-layer circuit board by means such as heat fusion, ultrasonic bonding or laser light or infrared light. It is intended to provide a multilayer circuit board for mounting Ic and a method for manufacturing the same.
  • a multilayer circuit board configured to laminate a plurality of circuit conductive layers on which a required circuit wiring pattern is formed via an insulating base material, Steps to expose the ends of the conductive layers stepwise to the required locations where mutual conduction should be provided between the above circuit conductive layers?
  • An L portion is formed, and an interlayer conductive member is provided in the stepped hole to electrically connect the conductive layers.
  • the interlayer conductive member is disposed on the interlayer conductive member, and is electrically connected to the outside of the circuit board from the interlayer conductive member. It is configured to include a conductive bump member for Ic pad bonding protruding from the surface.
  • the interlayer conductive member is constituted by a plating member electrically connected to the conductive bump member or a bump pedestal made of a filled conductive member, or an interlayer conductive member.
  • the conductive bump member and the conductive bump member can be made of the same conductive member by means of soldering or the like, and when these conductive bump members are formed of a solder member, they are projected by reflow processing.
  • the site can be formed in a hemispherical shape.
  • the bump structure as described above for connecting to an IC bare chip also forms a conduction hole reaching a specific circuit conductive layer in the circuit conductive layer, and is provided in the conduction hole.
  • a conductive member electrically connected to the specific circuit conductive layer is provided.
  • the conductive member is disposed on the conductive member and protrudes from the conductive member to the outside of the circuit board to be electrically connected to the Ic pad. It is also preferable to configure the conductive bump member as a compatible conductive bump member. And the method of forming the same member as the conductive bump member can be appropriately adopted.
  • a necessary circuit wiring pattern is formed in advance on the inner circuit conductive layer except for the outer circuit conductive layer, and the inner and outer circuit circuits are formed.
  • the inner and outer layers of each circuit conductive layer are formed. Step-shaped holes that are laminated and joined to each other with an insulating base material interposed, and the corresponding insulating base materials at corresponding locations where the conductive layers should be connected to each other are removed to expose each conductive layer portion in a stepped manner.
  • a required circuit wiring patterning process is performed on the outer conductive layer for a circuit, and then the conductive layer is projected outside the circuit board.
  • Conductivity for IC pad bonding on the above interlayer conductive member Adoption of the basic steps of forming a lamp member is preferred.
  • a solder plating process is performed on the stepped hole to electrically connect the conductive layers and a part of the solder plating member.
  • the conductive layer for the outer circuit is subjected to a required circuit wiring patterning process.
  • the interlayer conductive member and the conductive bump member can be formed of the same conductive member.
  • the conductive layers for inner and outer layers are laminated and bonded to each other with an insulating substrate interposed, and then the above-mentioned insulating base materials at corresponding locations where conduction is to be formed are removed to expose the specific conductive layer portion.
  • a hole is formed, a conductive member is formed in the hole, a required circuit wiring patterning process is performed on the circuit conductive layer of the outer layer, and then the interlayer is protruded outside the circuit board.
  • IC package on conductive member By adopting a method including each step of forming a conductive bump member for bonding a pad, it is possible to form a conductive bump member for bonding an IC pad to a specific conductive layer for a circuit. Even in the case of such a bump structure, similarly to the above, the steps subsequent to the step of forming the conductive hole are performed by performing solder plating on the hole and electrically connecting the hole to the specific conductive layer portion. After forming a conductive bump member for IC pad bonding in which a part of the solder plating member projects outside the circuit board, a necessary circuit wiring patterning process is performed on the outer conductive layer for the circuit.
  • the interlayer conductive member and the conductive bump member can be formed of the same conductive member.
  • the same multilayer circuit board can be provided with the above-described conductive bump member for IC pad bonding having a different structure.
  • FIGS. 1 (1) to 1 (3) show the concept of an IC mounting multilayer circuit board provided with a conductive bump member for IC pad bonding having a structure in which a plurality of conductive layers are electrically connected according to one method of the present invention.
  • FIG. 2 (1) to (3) show the conductive bump for IC pad bonding, which connects multiple conductive layers to the same multi-layer circuit board, and other structures that connect conductively to specific conductive layers.
  • FIGS. 3 (1) to (7) are main manufacturing process diagrams of an IC mounting multilayer circuit board having a conductive bump member for IC pad bonding having the structure shown in FIG. 1 (1).
  • FIGS. 4 (1) and (2) show the multi-layer circuit board for mounting ICs with the conductive bump members for IC pad bonding shown in FIG. 1 (2) in connection with the manufacturing process diagram of FIG. Main part manufacturing process diagram,
  • FIGS. 5 (1) and (2) show the relevant parts of the IC mounting multilayer circuit board with the IC pad bonding conductive bump members shown in FIG. 1 (3) in connection with the manufacturing process diagram of FIG. Manufacturing process diagram,
  • FIGS. 6 (1) to (7) show a multi-layer circuit board for mounting an IC having an IC pad bonding conductive bump member having a structure electrically connected to a specific conductive layer according to another method of the present invention.
  • FIG. 7 is a conceptual view of a multi-layer circuit board for mounting an IC having a conductive bump member for bonding an IC pad with a conductive bump pedestal formed by a filled conductive member by modifying the manufacturing process of FIG. Part enlarged cross-sectional configuration diagram,
  • Fig. 8 shows a modification of the manufacturing process shown in Fig. 6, and the solder bumps without the conductive bump pedestal are used to directly form the conductive bumps for IC pad bonding.
  • FIG. 9 is a conceptual enlarged cross-sectional configuration diagram of a principal part for explaining a conventional multilayer circuit board for mounting ICs.
  • FIGS. 1 (1) to 1 (3) are conceptual cross-sectional views of a principal part of a multilayer circuit board for mounting ICs according to an embodiment of the present invention.
  • an inner conductive layer 11 and an outer conductive layer 12 for forming a two-layer circuit board are each patterned in a conventional manner with respect to a foil-like conductive material such as a copper foil. It is formed so as to have a required circuit wiring pattern by processing, and these inner and outer conductive layers 11 and 12 are connected via a suitable flexible insulating base material 13 and 14 such as polyimide film. Laminated with each other.
  • a stepped hole for exposing the periphery of the inner conductive layer 11 with the outer conductive layer 12 as the bottom is shown in the figure.
  • a hole 17 is formed in the hole 17 so that the inner and outer conductive layers 11 and 12 are electrically connected to each other.
  • a conductive bump pedestal 15 is provided by a sticking means, and a mechanically protruding hemispherical shape is formed on the bump pedestal 15 from the circuit board to the outside as shown in the figure by solder plating and reflow processing.
  • a conductive bump member 16 for IC pad bonding having extremely good strength and electrical characteristics can be formed.
  • the stepped hole portion 17 for the stepped conductive bump pedestal 15 forming the interlayer conductive structure has the respective conductive layers in a structure having an upper conductive layer in addition to the inner conductive layer 11.
  • the hole diameter gradually increases as the layer shifts from the lower layer to the upper layer, and the upper hole diameter is formed such that the maximum displacement of the lower circuit board can be appropriately absorbed.
  • the formation mode of the part 17 significantly reduces the process of laminating and joining the circuit boards of the inner and outer layers.
  • silver paste, solder or a solder paste can be freely filled in the step hole 17 instead of the step conductive bump pedestal 15 by the above-mentioned plating means.
  • a similar hemispherical conductive bump member 16A can be formed on the filled conductive bump pedestal 15A formed as shown in FIG.
  • a solder hole for the step-like hole 17 is formed.
  • Another conductive bump member 16B for IC pad bonding that can form the interlayer conductive member and the conductive bump member with the same conductive member can be formed by the sticking means and the reflow process.
  • FIGS. 2 (1) to 2 (3) show the conductive bumps 16 and 16A or 16B of the conductive structure between the eyebrows and the specific conductive layers in the inner and outer conductive layers shown in FIG.
  • This shows a multilayer circuit board for mounting ICs in which conductive bump members of other structures are formed on the same multilayer circuit board.
  • the conductive bump members 16 of Fig. 1 (1) are used.
  • hemispherical conductive bump members 16 which are not connected to other outer conductive layers 12 A but are made conductive only to inner conductive layers 11 through conductive bump pedestals 15 B 16 I have C In the case of FIG.
  • a conductive bump pedestal 15C for connecting only to the other outer conductive layer 12B without being connected to the inner conductive layer 11 is provided.
  • An example in which a similar hemispherical conductive bump member 16D is formed on the pedestal 15C and the above-described conductive bump member 16 is formed on the same multilayer circuit board will be described.
  • the conductive layer connected only to the outer conductive layer 12 B is provided. those that are configured with a direct-formed conductive bump members 1 6 E in sex bump pedestal of Shino solder main luck member.
  • FIGS. 3 (1) to 7 (7) are manufacturing process diagrams of the multilayer circuit board for mounting IC shown in FIG. 1 (1).
  • a material such as a flexible double-sided copper-clad laminate having conductive layers 11 and 18 on both surfaces of a flexible insulating substrate 13 and a conductive layer 2 2 on one surface of the flexible insulating substrate 14
  • Prepare a material such as a flexible single-sided copper-clad laminate provided with a conductive layer, etch the required circuit wiring pattern for the conductive layer 11 and, at the Etching and removal of the portions 11 and 18 are performed at the same time to form large and small holes 19 and 20 for appropriately exposing the insulating base material 13.
  • the conductive layer 22 of the single-sided copper-clad laminate is left unpatterned without any patterning treatment.
  • the conductive layer 18 is not for forming a circuit wiring pattern, but functions as a mask for forming a stepped hole as described later. A thinner material than the layer can be used.
  • the copper-clad laminate ⁇ is used not only for a general material in which an insulating base material and a conductive layer are bonded with an adhesive, but also for a conductive layer such as a copper foil having a required thickness.
  • a conductive layer such as a copper foil having a required thickness.
  • the diameter of the hole 20 as described above is changed according to the transition from the lower layer to the upper conductive layer. Is formed so as to gradually increase, and the lower hole is formed in a mode included in the upper hole, whereby the positional displacement of the substrate during the lamination processing of each of the following layers is determined. Problems can be significantly reduced.
  • stepped holes 17 As shown in FIG.
  • a chemical resin etching method using an appropriate mask means in combination can be adopted, but it is preferable to perform the removal treatment on the insulating material using an excimer laser means, and in this case, a complicated mask is used. Step-shaped holes with the above-mentioned relationship of each hole diameter with high efficiency and high efficiency while making the conductive layers 11 and 18 at the ends of each hole function as a member equivalent to a mask without the necessity of hole formation processing etc. 17 can be formed.
  • this laminate was subjected to electroless copper plating, and if necessary, electrolytic copper plating was further performed thereon to form a step formed in the previous step.
  • a stepped interlayer conductive member 23 is formed on the inner peripheral surface of the hole 17 as shown in FIG.
  • the outer conductive layer 11 and the inner conductive layer 11 are electrically connected to each other by the stepped interlayer conductive member 23.
  • the outer conductive layer 22 is subjected to a required circuit wiring patterning process using a known method such as photolithography or the like, and an unnecessary portion of the upper conductive layer 18 is removed by etching.
  • a step-shaped conductive bump pedestal 15 having a structure in which the outer conductive layer 12 and the inner conductive layer 11 which are patterned are electrically connected can be formed.
  • the solder plating process 24 on the bump pedestal 15 and the reflow process thereof result in a stepped conductive bump pedestal 15 as a stepped interlayer conductive member as shown in FIG.
  • a multilayer circuit board for mounting ICs having a hemispherical conductive pad member 16 for IC pad bonding protruding outside the circuit board can be manufactured.
  • a conductive bump pedestal 15A composed of another structure constituting an interlayer conductive member can be formed by filling an appropriate conductive member such as a solder paste, and then FIG. 3 (5)
  • a solder plating 25 is formed on the surface of the bump pedestal 15A by applying a reflow process as shown in FIG. 4 (2).
  • a hemispherical conductive bump member 16A shown in FIG. 1 (2) having a structure projecting outside from 15A can be formed.
  • the outer layer patterning process can be performed before the filling process of the conductive bump pedestal 15A.
  • the step of filling the stepped hole 17 with the solder hole 26 is performed as shown in FIG. 5 (1).
  • a reflow process is performed on the solder plating 26 as shown in FIG. 5 (2).
  • a hemispherical conductive bump member 16B corresponding to FIG. 1 (3) in which the interlayer conductive member and the bump member are formed of the same solder member can be formed.
  • FIGS. 6 to 8 show a method for projecting a hemispherical conductive bump member as described above on a specific conductive layer of a multilayer circuit board.
  • Components similar to those in the process and having the same reference numerals as those shown in FIG. 3 indicate the same components. That is, In order to manufacture a conductive bump member 16D that is electrically connected to the outer conductive layer 12B without being connected to the conductive layer 11 as shown in FIG. 2 (2), first, as shown in FIG. As shown in (1), the inner conductive layer 11 is formed such that the diameter of the hole 2 OA provided in the inner conductive layer 11 is appropriately larger than the diameter of the hole 19 A formed in the conductive layer 18 for the mask.
  • the holes 19A and 2OA are formed, and then, as shown in FIG. 6 (2), a lamination process of both circuit boards is performed in the same manner as described above.
  • a conductive hole for removing only the outer conductive layer 22 by removing the insulating bases 13 and 14 located in the hole 19A by means of an excimer laser or the like. Form part 27.
  • the inner circuit wiring pattern conductive layer 11 is not exposed to the conductive hole 27 for forming a bump member by forming the hole 20 A, and it is exposed through the insulating layer. Since it is disposed at a position receded from 27, it is not placed in a conductive relationship with the conductive bump member.
  • the electroless plating for the conduction hole 27 and the electrolytic plating plating thickening process performed as necessary.
  • the circuit wiring pattern for the outer conductive layer 22 and the conductive layer 18 for the mask are formed.
  • a conductive layer 12B and a conductive bump pedestal 15C having a concave cross section are formed as shown in FIG. The same as the process of attaching the solder bump 29 of FIG.
  • the conductive bump pedestal 15 C which can be performed before or after the formation process of the bump pedestal 15 C and the conductive layer 12 B.
  • the conductive material that is firmly joined to the bump pedestal 15C and protrudes outside from this circuit board The bumps member 1 6 D can and fabrication child is.
  • FIG. 2 (1) in order to form a conductive bump member 16C which does not conduct to the outer circuit wiring pattern 12A but is connected only to the inner conductive layer 11 to conduct. Make changes before the above steps. That is, the opening of Fig.
  • a required circuit wiring patterning treatment is performed on the inner conductive layer 11 without forming the hole 2 OA in the inner conductive layer 11 and a hole 19 A having a required size is formed on the conductive layer 18 for the mask.
  • a step of laminating both substrates only the portion of the insulating substrate 13 that appeared in the hole 19A was appropriately removed by excimer laser means or the like to partially expose the inner conductive layer 11 and
  • the conductive member described above is filled in the conductive hole 27 shown in FIG. 3 (3).
  • a conductive bump pedestal 15D is formed as shown in Fig. 7, and this bump pedestal 15D is conductively connected to only the outer conductive layer 12B as shown in Fig. 7 by solder plating and reflow processing. It is possible to manufacture the hemispherical conductive bump member 16F.
  • the outer conductive layer 1 is formed as shown in FIG.
  • the structure of the conductive bump member that is conductively connected only to the inner conductive layer 11 has a filled conductive structure that is constructed in the same manner as in Figs. 7 and 8. It is also possible to configure a conductive bump member via a bump pedestal or a conductive bump member formed only by soldering means. Then, a method of manufacturing a conductive bump member having a structure for electrically connecting a plurality of conductive layers described with reference to FIGS. 3 to 5 and a specific conductive layer described with reference to FIGS. 6 to 8 are used.
  • a conductive bump member By applying the method of manufacturing a conductive bump member with a structure that is conductively connected to In a multi-layer circuit board structure having more than one conductive layer, it is not conductively connected to one or more conductive layers, but is conductively connected between other conductive layers between eyebrows.
  • the structure of the conductive bump member can be arbitrarily implemented in practical use.
  • the conductive bump member that can be configured in various structures according to the above embodiment is an optimum conductive bump member corresponding to the structure of an Ic bare chip or the structure of a multilayer circuit board on which it is mounted in relation to its function.
  • the above-described multilayer circuit board structure can be applied to not only a flexible multilayer circuit board but also a hybrid structure including both flexible and hard circuit boards. It can be applied arbitrarily.
  • the conductive bump member for IC pad bonding which functions as a bump on which the IC bare chip is mounted, is embedded in an insulating base material and has a structure in which its tip protrudes outward in a hemispherical shape and is supported by the insulating base material. Therefore, a conductive bump member for Ic pad bonding having high mechanical strength and electrical characteristics and high positional accuracy can be manufactured.
  • the conductive holes that need to be formed in the insulating base material in order to provide such conductive bump members for IC pad bonding can be manufactured quickly and efficiently using excimer lasers while greatly reducing the number of processes. It is possible to form fine holes without being affected by the problem of smearing in the conventional drilling method.
  • the conductive bump member for Ic pad bonding manufactured by the method of the present invention is formed in a hemispherical shape at low cost by using a solder plating member, so that the connection mounting process with the IC bay chip can be easily performed. .
  • the structure of a conductive bump member for conductively connecting a plurality of conductive layers in a multilayer circuit board and the structure of another conductive bump member capable of conductive connection to a specific conductive layer can be manufactured alone or in combination. Therefore, in connection with the structure of the Ic bare chip or its function, The most suitable conductive bump material can be configured with a high degree of design freedom according to the structure of the board.
  • the conductive bump members having various structures can be arranged on the portion of the multilayer circuit board corresponding to the pad of the IC bear chip, so that the wiring density of the multilayer circuit board can be improved. Therefore, this type of multilayer circuit board can be further compacted.

Description

明 細 書 I c搭載用多層回路基板及びその製造法
「技術分野」
本発明は可撓性回路基板等を用いて構成される多層回路基板に対 して I Cベアチップを直接的に実装可能に構成した I C搭載用多層 回路基板及びその為の製造法に関する。 更に具体的に云えば、 本発 明は多層回路基板の所要部位に？ L部を形成し、 この穿孔部に施すメ ツキ手段又は導電部材の充填手段と協働してこの回路基板外部に突 出する導電性バンプ部材を形成し、 該導電性バンプ部材により この 回路基板の所望の導電層と I Cベアチップのパッ ドとの間の確実な 電気的接続を図れるように構成した I c搭載用多層回路基板及びそ の為の好適な製造法に関する。
「背景技術」
可撓性回路基板等に I Cベアチップを実装するための手法と して 突出形成したリ ー ドフィ ンガーを用いるタブ方式は周知であるが、 この方式は主に単層の回路基板に採用されるものであって、 多層の 可撓性回路基板の場合には、 第 9図に示す如く各々所要の回路配線 パター ンを形成した内外層の導電層 2〜7を適宜な絶縁基材を介し て積層したフ リ ップチップ方式による可撓性多層回路基板 1 を製作 し、 I Cベアチップ 9 は外層導電層 2、 3 に於ける接続端部 2 A、 3 Aの部分で夫々バンプ 9 A、 9 Bを介して接続実装される。 図示 の場合、 外層の導電層 2は内層の導電層 4 と導通化することな く他 の外層導電層 6 にスルーホール導通部 8の部分で接続されており、 また他の外層導電層 3はその他の内層導電層 5及び外層導電層 7 と スルーホール導通部 8 Aで相互に導通接続されている。 そして、 こ れらのスルーホール導通部 8、 8 Aは I Cベアチップ 9の接続用バ ンプ 9 A、 9 B乃至は接続端部 2 A、 3 Aから適宜離れた部位に形 成されている。 回路基板 1 の接続端部 2 A、 3 Aと I Cベアチップ 9の接続用バンプ 9 A、 9 Bとは半田で相互に接続するのが一般的 である為、 斯かるフ リ ップチップ構造の可撓性多層回路基板 1 の場 合でもそれらの接続端部 2 A、 3 Aの周辺には、 半田流れ防止ダム 1 0. 1 0 Aが配設される。
上記の如きフ リ ップチップ方式に従った可撓性多層回路基板 1 の 構造では、 内外層の各導電層を相互接続する為のスル-ホ -ル導通 部 8、 8 Aを I Cベアチップ 9の実装部位に配設することは斯かる スルーホール導通構造から困難であること、 また半田流れ防止ダム 1 0 , 1 0 Aを設ける必要があること等から I Cベアチップ 9の実 装部を高密度にこの回路基板 1 に構成することは大きな制約を伴う ので、 I Cベアチップ 9の実装密度の割合には一般にこの種形態の 回路基板 1 は大型となる他、 相互接続用バンプ 9 A、 9 Bも I Cベ ァチップ 9の側に配設する必要があり、 その為の多数の工程と上記 の如き半田流れ防止ダムの必要性と相俟ってこの方式による I c搭 載方式に伴う コス ト高は避けられない。
—方、 従来手法でスル-ホ -ル導通部 8、 8 Aを形成する為には 所要導通個所に ドリルで透孔を穿設する必要があるが、 その際の高 回転の ドリル穿孔時の摩擦熱による好ましくないス ミァ発生とその 除去処理の問題が付随するこ と、 またこの種形態の可撓性回路基板 等の柔軟質材料の場合に於ける ドリル穿孔径には一定の限度がある こと、 更に、 多層化処理工程に際しても所要層に於けるラ ン ド位置 合わせ処理と穿孔位置合わせ処理に関連して少なからざる困難を生 ずる。
「発明の開示」
本発明は多層回路基板の所望の導電層と電気的接続を図る為の孔 部をこの回路基板の所要部位に形成し、 該穿？ L部に施すメ ツキ手段 又は導電部材の充填手段と協働してこの回路基板外部に突出する導 電性バンプ部材を形成し、 この導電性バンプ部材により回路基板の 所望の導電層と I Cベアチップのパッ ドとの間の確実な電気的接続 を図れるように構成した I c搭載用多層回路基板を製作し、 この多 層回路基板に形成したバンプ部材に対して I cベアチップを熱融着 法、 超音波ボンディ ング或いはレーザ—光や赤外光等の手段で容易 迅速に実装できるように構成した I c搭載用多層回路基板及びその 製造法を提供するものである。
その為に本発明の I C搭載用多層回路基板では、 絶縁基材を介し て所要の回路配線パターンを形成した複数の回路用導電層を積層す るように構成された多層回路基板に於いて、 上記回路用導電層間に 相互の導通を与えるべき所要部位にそれら導電層の端部を段状に露 出させる為の段状？ L部を形成し、 上記各導電層の間を電気的に接続 する為に上記段状孔部に層間導通部材を設け、 該層間導通部材上に 配設され且つこの層間導通部材から回路基板外部に突出する I cパ ッ ド接合用導電性バンプ部材を備えるように構成したものである。 上記の如き I C搭載用多層回路基板に於いて、 層間導通部材は導電 性バンプ部材と電気的に接合したメ ツキ部材若しく は充填導電性部 材からなるバンプ台座で構成するか又は層間導通部材と導電性バン プ部材とを半田メ ツキ等の手段による同一の導電性部材で構成する ことも自在であり、 これらの導電性バンプ部材を半田部材で構成す る場合にはリフロー処理によってその突出部位を半球状に形成する ことができる。
I Cベアチップと接続するための上記のようなバンプ構造は、 ま た、 回路用導電層に於ける特定の回路用導電層に達する導通用孔部 を形成し、 該導通用孔部に設けられて上記特定の回路用導電層と電 気的に接合した導通部材を設け、 該導通部材上に配設され且つ該導 通部材からこの回路基板の外部に突出して I cパッ ドと電気的に接 合可能な導電性バンプ部材と して構成することも好適であって、 斯 かる導電性バンプ構造に関しても上記の如きバンプ台座や導通部材 と導電性バンプ部材との同一部材形成等による手法を適宜採用でき る
このような I C搭載用多層回路基板を製作する手法としては、 外 層の回路用導電層を除き内層の回路用導電層には予め所要の回路配 線パターンを形成し、 該内外層各回路用導電層に対して相互の導通 を形成すべき所要部位に於いて上記各導電層にその孔径が漸次増大 する導通用孔をエキシマレーザー手段等で形成した後、 この内外層 各回路用導電層を絶縁基材の介在下に相互に積層接合し、 上記各導 電層に相互導通を形成すべき対応個所の上記各絶縁基材を除去して 各導電層部分が段状に露出する段状孔部を形成し、 この段状孔部に 層間導通部材を形成した後、 上記外層の回路用導電層に対して所要 の回路配線パターンニング処理を施し、 次いでこの回路基板の外部 に突出するように上記層間導通部材上に I Cパッ ド接合用導電性バ ンプ部材を形成するという基本的な各工程の採用が好適である。 こ こで、 上記段状孔部の形成工程以降の工程は、 該段状孔部に半 田メ ツキ処理を施して上記各導電層間を電気的に導通させると共に その半田メ ツキ部材の一部がこの回路基板の外部に突出して I cパ ッ ドと接合する為の導電性バンプ部材を形成した後、 上記外層回路 用導電層に対して所要の回路配線パターンニング処理を施すように 変更することにより、 上記層間導通部材と導電性バンプ部材とを同 —の導電性部材で形成することもできる。
更には、 上記内外層回路用導電層の特定の回路用導電層に対して 導通を形成する対応部位に於ける他の回路用導電層部分をその導通 に関与しない大きさに除去した後、 上記内外層各回路用導電層を絶 縁基材の介在下に相互に積層接合し、 次に導通形成する対応個所の 上記各絶縁基材を除去して上記特定の導電層部分を露出させる導通 用孔部を形成し、 該孔部に導通部材を形成した後、 上記外層の回路 用導電層に対して所要の回路配線パターンニング処理を施した後、 この回路基板外部に突出するように上記層間導通部材上に I Cパッ ド接合用導電性バンプ部材を形成する各工程からなる手法の採用に より、 特定の回路用導電層に対して I Cパッ ド接合用導電性バンプ 部材を形成するこ とが可能となる。 斯かるバンプ構造の場合でも上 記と同様に導通用孔部の形成工程以降の工程を、 該孔部に半田メ ッ キ処理を施して該特定の導電層部分と電気的に接合されたその半田 メ ツキ部材の一部がこの回路基板の外部に突出する I Cパッ ド接合 用導電性バンプ部材を形成した後、 上記外層の回路用導電層に対し て所要の回路配線パターンニング処理を施すように変更するこ とに よって、 上記層間導通部材と導電性バンプ部材とを同一の導電性部 材で形成することが可能となる。 そして、 上記の如き手法の組合せ により、 同一の多層回路基板に対して構造の異なる既述の I Cパッ ド接合用導電性バンプ部材を具備させるこ とも出来る。
上記種々の手法に於ける各工程の具体的な処理方法は以下の実施 例中で詳述される。
「図面の簡単な説明」
第 1図（1) 〜（3) は本発明の一方の手法に従って複数の導電層相互 間を導通接続する構造の I Cパッ ド接合用導電性バンプ部材を備え た I C搭載用多層回路基板の概念的な要部拡大断面構成図、
第 2図（1) 〜（3) は同一の多層回路基板に対して複数の導電層相互 間を導通接続する I Cパッ ド接合用導電性バンプ部材と特定の導電 層に関して導通接続する他の構造の I Cパッ ド接合用導電性バンプ 部材とを具備させるように構成した本発明の他の手法による同様な I C搭載用多層回路基板の概念的な要部拡大断面構成図、
第 3図（1) 〜（7) は第 1図（1) に示した構造の I Cパッ ド接合用導 電性バンプ部材を有する I C搭載用多層回路基板の主要な製造工程 図、
第 4図（1) 、 (2) は第 3図の製造工程図と関連して第 1図（2) の I C パッ ド接合用導電性バンプ部材を備えた I C搭載用多層回路基板の 要部製造工程図、
第 5図（1) 、 (2) は第 3図の製造工程図と関連して第 1図（3) の I C パッ ド接合用導電性バンプ部材を備えた I C搭載用多層回路基板の 要部製造工程図、
第 6図（1) 〜（7) は本発明の他の手法に従って特定の導電層に対し て導通接続された構造の I Cパッ ド接合用導電性バンプ部材を備え た I C搭載用多層回路基板の主要な製造工程図、
第 7図は第 6図の製造工程を変更して充填導電部材によつて形成 した導電性バンプ台座付き I Cパッ ド接合用導電性バンプ部材を有 する I C搭載用多層回路基板の概念的な要部拡大断面構成図、
第 8図は同じく第 6図の製造工程に変更を加えて導電性バンプ台 座無しの半田メ ツキ部材で I Cパッ ド接合用導電性バンプ部材を直 接的に構成するようにした I C搭載用多層回路基板の概念的な要部 拡大断面構成図、 そして、
第 9図は従来構造の I C搭載用多層回路基板を説明する為の概念 的な要部拡大断面構成図である。
「発明を実施する為の最良の形態」 第 1図（1) 〜（3) は本発明の一実施例によって構成された I C搭載 用多層回路基板の概念的要部断面構成図を示し、 同図（1) に於いて、 二層構造の回路基板を構成する為の内層の導電層 1 1及び外層の導 電層 1 2は各々銅箔等の箔状導電材に対する常法のバタ— ンニング 処理により所要の回路配線パター ンを備えるように形成され、 これ らの内外両導電層 1 1、 1 2はポリイ ミ ドフ ィルム等の適当な可撓 性絶縁基材 1 3、 1 4を介して相互に積層される。 そして、 I Cベ ァチップを実装すべき該当個所に、 図では説明の便宜上一個のみを 示すが、 外層導電層 1 2を底部として内層導電層 1 1 の周縁部を露 出させる為の段状の孔部 1 7を形成し、 この孔部 1 7に内外両導電 層 1 1、 1 2を導通させる層間導通部材と しての段状に形成したメ — — ツキ手段による導電性バンプ台座 1 5を具備させ、 このバンプ台座 1 5上に半田メ ツキ処理とそのリ フロー処理によって図の如く この 回路基板から外部に半球状に突出形成された機械的強度並びに電気 的特性の極めて良好な I Cパッ ド接合用導電性バンプ部材 1 6を構 成することができる。
上記に於いて、 層間導通構造を形成する段状の導電性バンプ台座 1 5の為の段状孔部 1 7は内層導電層 1 1 の他に上層の導電層を有 する構造ではその各導電層が下層から上層に移行するに応じてその 孔径が漸次増大し上部の孔径が下部回路基板の位置合わせ最大ずれ 量を好適に吸収できる程度に形成されるものであって、 斯かる段状 孔部 1 7の形成態様によって内外層各回路基板の相互積層接合処理 を格段に軽減化させるものでる。
上記の如きメ ツキ手段による段状導電性バンプ台座 1 5 に代えて 段状孔部 1 7内に第 1図（2) の如く銀ペース ト、 半田若しくは半田べ ース ト等の充填自在な適宜な導電部材を設けることによって同図の 如く形成した充填導電性バンプ台座 1 5 A上に同様な半球状導電性 バンプ部材 1 6 Aを構成することも可能である。 更に、 上記構造の 導電性バンプ台座 1 5或いは 1 5 Aを介在させる導電性バンプ部材 の形成態様に代えて、 第 1図（3) に示すとおり、 段状孔部 1 7に対す る半田メ ツキ手段とそのリフロー処理により層間導通部材と導電性 バンプ部材とを同一の導電性部材で形成することの可能な他の I C パッ ド接合用導電性バンプ部材 1 6 Bを構成できる。
第 2図（1) 〜（3) は第 1図に示す眉間導通構造の導電性バンプ部材 1 6、 1 6 A或いは 1 6 Bと内外導電層に於ける特定の導電層と導 通化された他の構造の導電性バンプ部材とを同一の多層回路基板に 形成した I C搭載用多層回路基板を示し、 第 2図（1) の構造では第 1 図（1) の導電性バンプ部材 1 6に加えて、 他の外層の導電層 1 2 Aに は接続されず内層の導電層 1 1 に対してのみ導電性バンプ台座 1 5 B を介して導通化された半球状の導電性バンプ部材 1 6 Cを備えるよ うに構成されており、 また、 第 2図（2) の場合では内層導電層 1 1 に は接続されず他の外層導電層 1 2 Bにのみ接続する為の導電性バン プ台座 1 5 Cを形成してこの台座 1 5 C上に同様な半球状の導電性 バンプ部材 1 6 Dを構成したものと上記の導電性バンプ部材 1 6 と を同一の多層回路基板に形成した例を示す。 同様に、 第 2図（3) の I C 搭載用多層回路基板では、 第 1図（3) の導電性バンプ部材 1 6 Bの他 に、 外層導電層 1 2 Bに対してのみ接続された導電性バンプ台座な しの半田メ ツキ部材で直接的に形成した導電性バンプ部材 1 6 Eを 備えるように構成されたものである。 そして、 図示しないが第 1図 (2) に示す如き導電性バンプ部材 1 6 Aと上記導電性バンプ部材 1 6 C、 1 6 D若しく は 1 6 Eの構造とを上記同様に同一の多層回路基板に 構成することも勿論可能であって、 実装すべき I Cベアチップとこ の多層回路基板との関連に於いて上記の如き種々の構造による I C パッ ド接合用導電性バンプ部材を組合せ可能に構成できる。
第 3図（1) 〜（7) は第 1図（1) に示す I C搭載用多層回路基板の製 造工程図であって、 同図（1) の如く先ずポリイ ミ ドフィルム等の適当 な可撓性絶縁基材 1 3の両面に導電層 1 1 、 1 8を有する可撓性両 面銅張積層扳等の材料と、 同じく可撓性絶縁基材 1 4の片面に導電 層 2 2を設けた可撓性片面銅張積層板等の材料とを用意し、 導電層 1 1 に対しては所要の回路配線パターンをエッチング形成すると共 に以下の如く層間導通を要する対応個所の導電層 1 1 、 1 8部分を 同時にエツチング除去して絶縁基材 1 3を適宜露出させる各々大小 の孔部 1 9、 2 0を形成する。 この段階では片面銅張積層板の導電 層 2 2にはパターンニング処理を加えずそのままとする。 導電層 1 8 は回路配線パター ンを形成する為のものではなく、 後述の如く段状 孔部を穿設する際のマスクとして機能するものであるから、 この導 電層 1 8は他の導電層に比して薄いものを使用することが出来る。
こ こで、 上記両銅張積層扳は絶縁基材と導電層とを接着剤で貼着 した一般的な材料の他、 例えば所要の厚さの銅箔等の導電層に対す る絶縁基材の為のフ ィ ルム部材のキャスティ ング手段若しく は上記 の如き可撓性の絶縁基材に対する導電部材のスパッタ リ ング又はィ オン蒸着等の手法によって導電層を形成した後、 この導電層上にメ ツキ手段で他の導電層を厚付して構成できる無接着剤型の積層扳材 料を使用することも出来る。
また、 内層となる導電層 1 1 の他に更に内層の導電層を有する多 層回路基板を構成する場合には、 下層から上層の導電層に移行する に応じ上記の如き孔部 2 0の径が漸次的に増大するように形成し、 下層の孔部はその上層の孔部に含まれる態様に形成することによつ て、 以下の各層の積層処理時に於ける基板の相互の位置ずれの問題 を格段に軽減できる。
そこで、 適当なプリプレダ又は接着剤 2 1 を介して同図（2) の如く 上記両回路基板を積層接合した後、 上記孔部によ り露出する絶縁基 材部位を除去して同図（3) に示す如き段状孔部 1 7を形成するもので ある。 その際、 適当なマスク手段の併用による化学的樹脂エツチン グ手法も採用可能であるが、 エキシマレーザ-手段を用いて絶縁材 に対する除去処理を行うのが好適あって、 この場合には煩雑なマス ク形成処理等の必要性なく、 各々の孔部端の導電層 1 1、 1 8部位 をマスク相当部材と して機能させながら高能率迅速に上記各孔径の 関係で構成される段状孔部 1 7を形成可能である。
斯かる段状孔部 1 7を形成した段階に於いてこの積層体を無電解 銅メ ツキ処理に付し、 更に必要ならばその上に電解銅メ ツキ処理を 施して前工程で形成した段状孔部 1 7の内周面に同図（4) に示す如く 段状層間導通部材 2 3を形成する。 斯かる段状層間導通部材 2 3 に より外層と内層の各導電層 1 1、 2 2は電気的に接続された状態と なる。
次いで、 外層の導電層 2 2に対するフ ォ ト リ ソグラフ等の公知手 法の採用による所要の回路配線パター ンニング処理と上層の導電層 1 8に於ける不要部分のエッチング除去処理とを施すことによ り、 同図（5) のようにパターンニングされた外層の導電層 1 2 と内層の導 電層 1 1 を電気的に接続した構造の段状導電性バンプ台座 1 5を構 成できるので、 以下、 同図（6) 、 (7) の如くバンプ台座 1 5に対する 半田メ ツキ処理 2 4 とそのリ フロー処理により第 1図に示す如き段 状の層間導通部材としての段状導電性バンプ台座 1 5上に回路基板 外部に突出する半球状の I Cパッ ド接合用導電性バンプ部材 1 6を 備えた I C搭載用多層回路基板を製作できる。
上記工程に於いて、 第 3図（3) の如き段状孔部 1 7の穿設工程終了 後、 第 4図（1) に示す如く該段状孔部 1 7内に銀ペース ト、 半田又は 半田ペース ト等の適宜な導電性部材を充填処理することにより層間 導通部材を構成する他の構造からなる導電性バンプ台座 1 5 Aを形 成することができ、 次いで第 3図（5) のパターンニング処理工程を施 した後、 上記バンプ台座 1 5 Aの面上に半田メ ツキ 2 5を被着形成 し、 これに第 4図（2) に示す如く リフロー処理を加えることによって バンプ台座 1 5 Aから外部に突出する構造の第 1図（2) に示す半球状 の導電性バンプ部材 1 6 Aを構成できる。 なお、 外層パターンニン グ処理工程は導電性バンプ台座 1 5 Aの充填処理形成前に行う こと も出来る。
また同様に、 第 3図（3) の段状孔部 1 7の穿設工程終了後、 第 5図 (1) の如くその段状孔部 1 7に対する半田メ ツキ 2 6の充填処理工程 でバンプ台座なしの層間導通部材を構成し、 斯かる工程の前後に於 いて上記同様な外層パターンニング処理工程を行った後、 第 5図（2) の如く該半田メ ツキ 2 6にリフロー処理を加えることによって層間 導通部材とバンプ部材とを同一な半田部材で構成した第 1図（3) に対 応する半球状の導電性バンプ部材 1 6 Bを構成することが出来る。
第 6図〜第 8図は多層回路基板の特定の導電層に対して上記の如 き半球状の導電性バンプ部材を突出形成する為の手法を示し、 それ らの製造法は既述の各工程と類似のものであって、 第 3図に示す符 号と同一の部材はそれらと同一の構成要素を示している。 即ち、 内 層の導電層 1 1 には接続することなく、 第 2図（2) のとおり、 外層の 導電層 1 2 Bと導通接続する導電性バンプ部材 1 6 Dを製作するに は、 先ず第 6図（1) に示す如くマスク用導電層 1 8に形成する孔部 1 9 A の径より内層の導電層 1 1 に設ける孔部 2 O Aの径を適宜大き く な るように内層導電層 1 1 の回路配線パター ンニング処理時に上記両 孔部 1 9 A、 2 O Aを形成し、 以下、 既述の工程と同様に第 6図（2) の如く両回路基板の積層処理を行い、 そこで同図（3) のようにェキ シマレ—ザ—手段等で上記孔部 1 9 Aに位置する絶縁基材 1 3、 1 4 の部分を除去して外層導電層 2 2のみを露出させる導通用孔部 2 7 を形成する。 内層の回路配線パター ン導電層 1 1 は上記孔部 2 0 A の形成によってバンプ部材形成の為の上記導通用孔部 2 7には露出 せず、 それは絶縁層を介してこの導通用孔部 2 7から後退した部位 に配設されるので、 導電性バンプ部材と導通関係に置かれることは ない。
そこで、 第 3図（4) 〜（7) と同様に第 6図（4) のとおり導通用孔部 2 7に対する無電解メ ツキと必要に応じて行う電解メ ツキの厚付け 処理とにより該孔部 2 7に露出する外層導電層 2 2 の部分と電気的 に接合された導通部材 2 8を形成した後、 外層導電層 2 2に対する 回路配線パター ンニングとマスク用導電層 1 8に於ける不要部分除 去の為のエツチング処理によつて同図（5) のような回路配線パタ一ン 化した導電層 1 2 Bと断面凹型状の導電性バンプ台座 1 5 Cを形成 し、 次いで斯かるバンプ台座 1 5 Cと導電層 1 2 Bの形成処理工程 の前又は後に行う ことの可能な導電性バンプ台座 1 5 Cに対する同 図（6) の半田メ ツキ 2 9の被着処理と同図（7) のリフロー処理により 該バンプ台座 1 5 Cに強固に接合され且つこの回路基板から外部に 突出する導電性バンプ部材 1 6 Dを製作するこ とができる。 こ こ で、 第 2図（1) の如く外層の回路配線バター ン 1 2 Aとは導通せず、 内層導電層 1 1 にのみ導通接続した導電性バンプ部材 1 6 Cを構成 する為には、 上記工程の前段に変更を加える。 即ち、 第 6図（1 ) の開 始工程に於いて、 内層導電層 1 1 には孔部 2 O Aを設けることなく 所要の回路配線パターンニング処理を施し、 且つマスク用導電層 1 8 には所要の大きさの孔部 1 9 Aを形成し、 両基板の積層工程後にそ の孔部 1 9 Aに現れた絶縁基材 1 3の部分のみをエキシマレーザー 手段等で適宜除去して内層導電層 1 1 を部分的に露出させ、 以下、 前記工程と同様にその導通用孔部に対する導通部材の被着処理工程、 外層導電層 2 2に対する回路配線バターン 1 2 A及び導電性バンプ 台座 1 5 Bの形成工程、 該バンプ台座 1 5 Bへの半田メ ツキ被着処 理とそのリフロー処理工程により、 内層導電層 1 1 にのみ導通化し た第 2図（1) に示す導電性バンプ部材 1 6 Cを得ることが出来る。 更に、 第 6図（4) の無電解メ ツキ処理等による導通部材 2 8の形成 手段に代えて、 同図（3) に示す導通用孔部 2 7に既述の導電性部材を 充填して第 7図の如く導電性バンプ台座 1 5 Dを形成し、 このバン プ台座 1 5 Dに対する半田メ ツキ処理とリ フロー処理により、 同図 のとおり、 外層導電層 1 2 Bにのみ導通接続した半球状の導電性バ ンプ部材 1 6 Fを製作することが可能となる。 同様に、 第 6図（3) の導通用孔部 2 7への半田メ ツキ処理を施す変更工程と上記と同様 なその後段の工程の採用によって、 第 8図に示すとおり外層の導電 層 1 2 Bにのみ導通接続された他の半球状の導電性バンプ部材 1 6 E をも構成することができ、 これは第 2図（3) に既述した I Cパッ ド接 合用導電性バンプ部材 1 6 Eに応用される。
なお、 第 2図（1) に示すとおり、 内層の導電層 1 1 とのみ導通接続 した導電性バンプ部材の構造に第 7図及び第 8図と同様な手法に従 つて構成される充填導電性バンプ台座を介した導電性バンプ部材或 いは半田メ ッキ手段のみで形成した導電性バンプ部材を構成するこ とも可能である。 そして、 第 3図〜第 5図に関連して説明した複数 の導電層間を導通接続する構造の導電性バンプ部材の製作手法と第 6図〜第 8図に関連して説明した特定の導電層に対して導通接続す る構造の導電性バンプ部材の製作手法とを応用することにより、 三 層以上の導電層を備える多層回路基板構造に於いて、 或る一又はそ れ以上の導電層とは導通接続せず、 他の複数の導電層相互間を眉間 導通接続する I cパッ ド接合用導電性バンプ部材の構造も実用に際 して任意に実施できる。
上記態様によ り種々の構造に構成可能な導電性バンプ部材は I c ベアチップの構造又はその機能と関連してそれを搭載させる多層回 路基板の構造等に対応させて最適な導電性バンプ部材の選択又はそ れらの組合せが可能であり、 また、 上記の如き多層回路基板構造は 可撓性多層回路基板の他、 可撓性と硬質の両回路基板からなるハイ プリ ッ ド構造にも任意に応用可能である。
「産業上の利用可能性」
I Cベアチップを搭載させるバンプと して機能する I Cパッ ド接 合用導電性バンプ部材は、 絶縁基材に埋設されその先端部が外部に 半球状に突出した状態で絶縁基材に支持された構造である為、 機械 的強度と電気的特性の傻れたものであって且つ位置精度の高い I c パッ ド接合用導電性バンプ部材を製作できる。
このような I Cパッ ド接合用導電性バンプ部材を設ける為に絶縁 基材に形成する必要のある導通用孔部はエキシマレ—ザ一手段等の 採用によって工程を大幅に削減しながら高能率迅速に形成すること が可能であり、 また、 従来の ドリル穿孔法に於けるスミ ア発生の問 題に影響されることなく、 微小孔の形成も好適に処理できる。
本発明の手法により製作される I cパッ ド接合用導電性バンプ部 材は半田メ ツキ部材を使用して半球状に安価に突出形成して I Cベ ァチップとの接続実装処理を簡便に実施できる。
多層回路基板に於ける複数の導電層の相互間を導通接続する導電 性バンプ部材の構造及び特定の導電層に導通接続可能な他の導電性 バンプ部材の構造を単独又は組合せて製作可能である為、 I cベア チップの構造又はその機能と関連してそれを搭載させる多層回路基 板の構造などに対応させて仕様に最適な導電性バンプ部材を高い設 計自由度で構成できる。
上記のように種々の構造からなる導電性バンプ部材は I Cベアチ ップのパッ ドに対応した位置の多層回路基板部位に配設できる為、 多層回路基板の配線密度の向上化を図れることとなり、 従ってこの 種の多層回路基板サイズのコ ンパク ト化も更に促進できる。
現今の I Cベアチップの実装処理に有利なエリアボンディ ング、 即ち面実装を可能にする最適な I C搭載用多層回路基板を提供でき る o

Claims
請 求 の 範 囲 . 絶縁基材の介在下に所要の回路配線パターンを形成した複数の回 路用導電層を積層するように構成された多層回路基板に於いて、 上記回路用導電層間に相互の導通を与えるべき所要部位にそれら 導電層の端部を段状に露出させる為の段状孔部を備え、 上記各導 電層の間を電気的に接続する為に上記段状孔部に層間導通部材を 設け、 この層間導通部材上に配設され且つ該層間導通部材からこ の回路基板外部に突出する I cパッ ド接合用導電性バンプ部材を 備えるように構成したことを特徴とする I C搭載用多層回路基板。 . 前記層間導通部材を上記導電性バンプ部材と電気的に接合された 導電性部材からなるバンプ台座で構成したことを特徴とする請求 項 1 の I c搭載用多層回路基板。
. 前記バンプ台座が上記段状孔部内に露出した上記各導電層を電気 的に接続する段状のメ ツキ部材で構成された請求項 2の I C搭載 用多層回路基板。
. 前記メ ツキ部材が無電解メ ツキ層を具備する請求項 3の I C搭載 用多層回路基板。
. 前記バンプ台座が上記段状孔部に充填されて上記各導電層を電気 的に接続する導電性部材である請求項 2の I C搭載用多層回路基 板。
. 前記導電性バンプ部材をリフロ -自在な半田部材で構成した請求 項 1〜 5のいずれかに記載の I C搭載用多層回路基板。
. 前記層間導通部材と上記導電性バンプ部材とが同一の導電性部材 で構成された請求項 1 の I C搭載用多層回路基板。
. 前記導電性部材をリフロ -自在な半田部材で構成した請求項 7の I C搭載用多層回路基板。
. 前記導電性バンプ部材に於ける回路基板からの突出部位を半球状 に構成した前記請求項のいずれかの I C搭載用多層回路基板。
10. 絶縁基材の介在下に所要の回路配線パターンを形成した複数の回 路用導電層を積層するように構成された多層回路基板に於いて、 上記回路用導電層に於ける特定の回路用導電層に達する導通用孔 部を備え、 この導通用孔部に設けられて上記特定の回路用導電層 と電気的に接合した導通部材を有し、 この導通部材上に配設され 且つ該導通部材からこの回路基板外部に突出する I Cパッ ド接合 用導電性バンプ部材を備えるように構成したことを特徴とする I C 搭載用多層回路基板。
11. 前記導通部材を上記導電性バンプ部材と電気的に接合した導電性 バンプ台座で構成したことを特徴とする請求項 1 0の I C搭載用 多層回路基板。
12. 前記バンプ台座 ϋ上記孔部底に露出する上記特定の回路用導電層 と接合したメ ツキ部材である請求項 1 1 の I C搭載用多層回路基 板。
13. 前記メ ッキ部材が無電解メ ッキ層を具備する請求項 1 2の I C搭 載用多層回路基板。
14. 前記バンプ台座 ϋ上記孔部に充填されて上記特定の回路用導電層 に接合した導電性部材である請求項 1 1 の 1 じ搭載用多層回路基 板。
15. 前記導電性バンプ部材をリフロー自在な半田部材で構成した請求 項 1 0〜 1 4のいずれかに記載の I C搭載用多層回路基板。
16. 前記導通部材と上記導電性バンプ部材を同一の導電性部材で構成 した請求項 1 0 の I C搭載用多層回路基板。
17. 前記導電性部材をリフロ -自在な半田部材で構成した請求項 1 6 の I C搭載用多層回路基板。
18. 前記導電性バンプ部材に於ける回路基板からの突出部位を半球状 に構成したことを特徵とする請求項 1 0〜 1 7のいずれかに記載 した I C搭載用多層回路基板。
19. 前記多層回路基板に於いて、 前記請求項 1 〜 9のいずれかに記載 の導電性バンプ部材と前記請求項 1 0〜 1 8のいずれかに記載さ れた導電性バンプ部材とを共に具備する I C搭載用多層回路基板。
20. 外層の回路用導電層を除き内層の回路用導電層には予め所要の回 路配線パター ンを形成し、 該内外層各回路用導電層に対して相互 の導通を形成すべき所要部位に於いて上記各導電層にその孔径が 漸次増大する導通用孔を形成した後、 この内外層各回路用導電層 を絶縁基材の介在下に相互に積層接合し、 上記各導電層に相互導 通を形成すべき対応個所の上記各絶縁基材を除去して各導電層部 分が段状に露出する段状孔部を形成し、 該段状孔部に層間導通部 材を形成した後、 上記外層の回路用導電層に対して所要の回路配 線パター ンニング処理を施し、 次いでこの回路基板外部に突出す るように上記層間導通部材上に I cパッ ド接合用導電性バンプ部 材を形成する各工程を含む I c搭載用多層回路基板の製造法。
21.前記各絶縁基材の除去処理工程が化学的樹脂ェッチング手段若し く はエキシマレーザー手段を用いて行われる請求項 2 0の I C搭 載用多層回路基板の製造法。
22. 前記層間導通部材を形成する為の工程は上記導電性バンプ部材と 電気的に接合された導電性バンプ台座を形成する工程からなる請 求項 2 0又は 2 1の I C搭載用多層回路基板の製造法。
23. 前記導電性バンプ台座が上記段状孔部に対するメ ツキ手段で段状 に形成された請求項 2 2の I C搭載用多層回路基板の製造法。
24.前記メ ッキ手段が少なく とも無電解メ ッキ法を含む請求項 2 3の I C搭載用多層回路基板の製造法。
25. 前記導電性バンプ台座を上記段状孔部に対する導電性部材の充填 処理で形成した請求項 2 2の I C搭載用多層回路基板の製造法。
26. 前記導電性バンプ部材が半田メ ツキ処理によって形成された請求 項 2 0〜 2 5のいずれかの I C搭載用多層回路基板の製造法。
27. 半田メ ッキ処理によって形成した前記導電性バンプ部材にリ フロ 一処理を施して回路基板から突出する部位を半球状に形成する請 求項 2 6の I C搭載用多層回路基板の製造法。
28. 外層の回路用導電層を除き内層の回路用導電層には予め所要の回 路配線パター ンを形成し、 該内外層各回路用導電層に対して相互 の導通を形成すべき所要部位に於いて上記各導電層にその孔径が 漸次増大する導通用孔を形成した後、 この内外層各回路用導電層 を絶縁基材の介在下に相互に積層接合し、 上記各導電層に相互導 通を形成すべき対応個所の上記各絶縁基材を除去して各導電層部 分が段状に露出する段状孔部を形成し、 該段状孔部に半田メ ツキ 処理を施して上記各導電層間を電気的に導通させると共にその半 田メ ツキ部材の一部がこの回路基板外部に突出する I Cパッ ド接 合用導電性バンプ部材を形成した後、 上記外層の回路用導電層に 対して所要の回路配線パター ンニング処理を施す各工程からなる I C搭載用多層回路基板の製造法。
29. 前記各絶縁基材の除去処理工程が化学的樹脂ェツチング手段若し く はエキシマレーザー手段によつて行われる請求項 2 8の I C搭 載用多層回路基板の製造法。
30. 半田メ ツキ処理によって形成した前記導電性アンプ部材にリフロ —処理を施して回路基板から突出する部位を半球状に形成する請 求項 2 8〜 2 9の I C搭載用多層回路基板の製造法。
31. 外層の回路用導電層を除き内層の回路用導電層には予め所要の回 路配線パター ンを形成し、 上記内外層回路用導電層の特定の回路 用導電層に対して導通を形成する対応部位に於ける他の回路用導 電層部分をその導通に関与しない大きさに除去した後、 上記内外 層各回路用導電層を絶縁基材の介在下に相互に積層接合し、 次い で導通形成する対応個所の上記各絶縁基材を除去して上記特定の 導電層部分を露出させる導通用孔部を形成し、 この孔部に導通部 材を形成した後、 上記外層の回路用導電層に対して所要の回路配 線パター ンニング処理を施した後、 この回路基板外部に突出する ように上記層間導通部材上に I cパッ ド接合用導電性バンプ部材 を形成する各工程からなる I c搭載用多層回路基板の製造法。
32. 外層の回路用導電層を除き内層の回路用導電層には予め所要の回 路配線パター ンを形成し、 上記内外層回路用導電層の特定の回路 用導電層に対して導通を形成する対応部位に於ける他の回路用導 電層部分をその導通に関与しない大きさに除去した後、 上記内外 層各回路用導電層を絶縁基材の介在下に相互に積層接合し、 次い で導通形成する対応個所の上記各絶縁基材を除去して上記特定の 導電層部分を露出させる導通用孔部を形成し、 該孔部に半田メ ッ キ処理を施して該特定の導電層部分と電気的に接合されたその半 田メ ツキ部材の一部がこの回路基板の外部に突出する I Cパッ ド 接合用導電性バンプ部材を形成した後、 上記外層の回路用導電層 に対して所要の回路配線パターンニング処理を施す各工程を含む I C搭載用多層回路基板の製造法。
33. 前記各絶縁基材の除去処理工程が化学的樹脂ェッチング手段或い はエキシマレ—ザ—手段を用いて行われる請求項 3 1又は 3 2の I C搭載用多層回路基板の製造法。
34. 前記導通部材を形成する為の工程は上記導電性バンプ部材と電気 的に接合した導電性バンプ台座を形成する工程からなる請求項 3 1 の I C搭載用多層回路基板の製造法。
35. 前記導電性バンプ台座が上記導通用孔部に対するメ ツキ手段で段 状に形成された請求項 3 4の I C搭載用多層回路基板の製造法。
36. 前記メ ッキ手段が少なく とも無電解メ ッキ法を含む請求項 3 5の I C搭載用多層回路基板の製造法。
37. 前記導電性バンプ台座を上記導通用孔部に対する導電性部材の充 填処理で形成された請求項 3 4の I C搭載用多層回路基板の製造
38. 前記導電性バンプ部材が半田メ ツキ処理によって形成された請求 項 3 1 又は 3 3〜 3 7のいずれかの I C搭載用多層回路基板の製
IE.法
39. 半田メ ッキ処理によって形成した前記導電性バンプ部材にリフロ 一処理を施して回路基板から突出する部位を半球状に形成する請 求項 3 2又は 3 8の I C搭載用多層回路基板の製造法。
PCT/JP1991/000523 1990-04-23 1991-04-19 Multilayer circuit board for mounting ic and manufacture thereof WO1991016726A1 (en)

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US5317801A (en) 1994-06-07
US5260518A (en) 1993-11-09

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