WO1991018459A2 - Vorrichtung für das umwandeln eines digitalblockes und verwendung derselben - Google Patents
Vorrichtung für das umwandeln eines digitalblockes und verwendung derselben Download PDFInfo
- Publication number
- WO1991018459A2 WO1991018459A2 PCT/CH1991/000117 CH9100117W WO9118459A2 WO 1991018459 A2 WO1991018459 A2 WO 1991018459A2 CH 9100117 W CH9100117 W CH 9100117W WO 9118459 A2 WO9118459 A2 WO 9118459A2
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- WO
- WIPO (PCT)
- Prior art keywords
- block
- blocks
- sub
- encryption
- output
- Prior art date
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
- H04L9/0625—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation with splitting of the data block into left and right halves, e.g. Feistel based algorithms, DES, FEAL, IDEA or KASUMI
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
- H04L2209/125—Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/24—Key scheduling, i.e. generating round keys or sub-keys for block encryption
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
- Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
- Y04S40/00—Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them
- Y04S40/20—Information technology specific aspects, e.g. CAD, simulation, modelling, system security
Definitions
- the invention relates to a device for the block-wise conversion of a first digital block into a second digital block according to the preamble of claim 1.
- the invention further relates to the use of this device according to the preamble of the other independent claim.
- the Data Encryption Standard DES is generally considered a very good encryption tool. However, it is an open, debated question whether the DES standard has become uncertain or not. The short length of the secret key plays an important role here.
- Fig. 1 basic block diagram of a device for transmitting messages in encrypted form
- FIG. 2 block diagram of an encryption unit
- FIG. 3 block diagram of a primary
- FIG. 8 block diagram of a supplementary item
- FIG. 9 block diagram of an encryption level
- FIG. 11 block diagram of a second supplementary item
- FIG. 12 block diagram of a second
- FIG. 13 block diagram of a second
- the messages to be transmitted originate in a message source (message source) 11, for example a computer. These messages are encrypted in an encryption unit (encrypter) 12 and sent as cipher text to a generally accessible transmission line 13.
- the cipher text X reaches a decrypter 14 on the receiver side, which decrypted supplies it to a message sink (destination) 15, for example a second computer.
- Decryption unit 14 use a secret key block Z for the encryption or decryption of the messages, which is provided by a key source 16 and is supplied to both units 12, 14 on a secure channel 17.
- This channel 17 is, for example, a courier with a sealed envelope.
- the cipher text on the transmission line 13 is always subject to the risk that an enemy cryptanalysisr 19 reads this text and tries to obtain the assigned plain text X or the key block Z. (The result of these attempts
- the encryption method should be resistant to this in principle or at least for a sufficiently long time.
- Fig. 2 shows a block diagram of the
- Encryption unit 12 in the case of gradual block encryption.
- the plaintext X. to be encrypted comes continuously from the message source 11 and reaches an input unit 21, for example a series / parallel converter in the case of a serial bit stream.
- These plain text subblocks of the respective plain text block X reach first through inputs 25 to 28, respectively consisting of sixteen parallel lines, a first encryption level 61.1.
- the sub-blocks X ⁇ to X 4 are mixed together with six different control blocks by means of suitable logic functions.
- the (general) control blocks are at
- Decryption sub-blocks U x to U 6 which are each derived from the key block Z. This will be discussed in more detail later. The encryption process is mainly described below, which is why the term key sub-block is preferred.
- the key partial blocks Z x to Z 6 are present at second inputs 29, 30, 32, 33, 49, 52 of the first encryption level 61.1.
- You and other key sub-blocks Z 7 to Z S2 are delivered by a key sub-block generation unit 63.
- the method for obtaining the key partial blocks Z x to Z 8 from the key block Z is that it is divided into eight equal parts, each 16 bits long.
- the 128 bits of the key block Z are then cyclically shifted by 25 bits in a uniform direction, for example to the left (cyclically interchanged), and the resulting new sequence of 128 bits is again divided into eight equal parts to form the key sub-blocks Z 9 to Z 16 , and so on until the formation of Z S2 .
- Each key sub-block Z x to Z 52 thus has a (second) length m of 16 bits, is uniquely derived from the key block Z and generally differs from every other key sub-block.
- the key sub-blocks Z-, Z 6 are located at the six second inputs 29, 30, 32, 33, 49, 52 of the first encryption stage 61.1.
- the first intermediate sub-blocks W n to W 14 are for the second encryption step at the connections or inputs 35 to 38 (identical to the outputs of the previous stage 61.1) of a second one
- Encryption level 61.2 This encryption level 61.2 is constructed identically to the first encryption level 61.1.
- the described key sub-blocks Z 7 to Z 12 are present at their six second key inputs and the second intermediate sub-blocks W 21 , W 22 , W 23 , W 24 or overall the second intermediate block W 2 appear at their outputs.
- the second intermediate sub-blocks W 21 to W 24 are present for the third encryption step at a third encryption level, not shown, the third intermediate sub- blocks W 31 to W 34 at a fourth encryption level, etc. up to a ninth encryption level 69 with four, different from the previous levels second inputs 129, 130, 132, 133.
- ciphertext block Y which corresponds to the respective plaintext block X in a complicated but unambiguous manner assigned.
- This ciphertext block Y is converted in an output unit 79, for example a parallel / series converter, in such a way that it can be transmitted on the transmission line 13.
- the encryption process thus takes place in nine successive successive encryption levels 61.1, 61.2, 69, of which the first eight are identical to one another.
- the different key sub-blocks Z x to Z 52 mentioned in total serve as keys.
- the encryption unit 60 required for the encryption process X ⁇ Y is shown in dashed lines in FIG. 2.
- the encryption levels 61.1, 61.2, 69 can be implemented in different ways.
- a so-called software solution can be provided, in which one or more processors work according to a predetermined program.
- each input e.g. the first inputs 25 to 28
- the m 16 parallel lines of each input in series.
- a hardware solution can also be provided in which the logical function elements are present as independent circuit units. These are then either constructed from discrete chip elements or preferably from a few large integration modules (very large scale integration VLSI).
- VLSI very large scale integration
- all lines of all inputs are preferably treated in parallel.
- a partial series procedure is also possible here, e.g. the various inputs (e.g. 25 to 28) are connected in series to part-central circuit units via ultiplexer.
- the hardware solution has the advantage over the software solution that it can work much faster, up to clock frequencies of around 100 Mbit / s and more.
- the hardware solution for the encryption levels 61.1, 61.2, 69 is therefore put in the foreground and for reasons of illustration.
- 3 shows the block diagram of a primary encryption logic 40.
- This logic comprises four operational units 41 to 44 of two different types JJ, j, which are interconnected by three connections 45 to 47, the last (47) of which is an output of the logic 40 forms.
- Each operation unit 41 to 44 has two inputs and one output. Each input and output is designed as a 16-bit parallel input or output, to which a 16-bit block is present in parallel.
- the operational units 41 to 44 are designed to logically combine two input blocks E 1 E 2 and to form an associated output block A of 16 bits. In terms of the method, the operation units are connected in four stages, the two types of units 41 to 44 alternating.
- the operational units of the first type [__, ie units 42 and 44 have the following properties: These units consider each input block E lf E 2 as an integer in binary representation, this number being the set of numbers or the quantity ⁇ 0, 1, 2 , ..., (2 m -l) ⁇ (the number m (second length) is preferably the number 16, but can also be 4 or 8).
- the units 42, 44 then form the sum modulo 2 m from the input blocks E lr E 2 and emit a corresponding output block A.
- the operation units 42, 44 of the first type are thus modulo 2 m adders.
- the two input blocks E x , E 2 and the output block A are each a number in binary and decimal form specified.
- the respective output block A is then the product modulo (2 m + l) of the input blocks E lr E 2 .
- the units 41, 43 are thus multipliers modulo (2 m + 1).
- the primary encryption logic 40 brings about very good mixing (diffusion), since each of its two output blocks a lf a 2 depends on both input blocks e x , e 2 and on the two key sub-blocks Z 5 / Z 6 , that is to say on the values at all inputs. It can be demonstrated that the number of four operations constitutes a minimum for fulfilling this mixing task. The above-mentioned use of operating units of different types is used to generate the necessary confusion.
- This encryption logic has four first inputs 125 to 128 for four input blocks e 5 to e 8 to be encrypted in parallel, four outputs 35 to 38 for the delivery of four output blocks a 5 to a 8 and two second inputs 49, 52 already mentioned for the input of two key sub-blocks Z 5 , Z 6 .
- the heart of the extended encryption logic 140 is the described primary logic 40. This is supplemented by six operation units 115 to 120 of a third type ⁇ -, in such a way that the input 125 to the units
- the extended encryption logic 140 is functionally constructed in such a way that each output 35 to 38 depends on all inputs 125 to 128 and 49, 52, that operational units of different types [ ⁇ J, CJ, follow one another and that the property of involution is given. This last property means that the expanded encryption logic 140 is a self-inverse function for the blocks e 5 to e 8 present at its first inputs 125 to 128, specifically for any pair of key partial blocks Z 5 , Z 6 .
- FIG. 8 shows the block diagram of a supplementary encryption logic 240.
- This has two operation units 111, 112 of the second type __ and two operation units 113, 114 of the first type ___].
- the outputs of logic 240 are the same as outputs 135 to 138 of operation units 111 to 114.
- FIG. 9 shows the block diagram of one of the first eight, identical encryption stages in FIG. 2, for example the first stage 61.1. Then this encryption level is removed from the Combination of an additional encryption logic 240 and an expanded encryption logic 140 is formed, the outputs 135 to 138 of the logic 240 being directly (galvanically) connected to the inputs 125 to 128 of the subsequent logic 140.
- the inputs 25 to 28 of the respective encryption level (61.1) are identical to the inputs 225 to 228 of the additional encryption logic 240.
- the outputs of the extended logic 140 cross the outputs 35 to 38 of the encryption level 61.1.
- Six key sub-blocks are present at the second inputs 29, 30, 32, 33, 49, 52, for example, blocks Z x to Z 6 , at the first inputs 25 to 28 either four plain text sub-blocks X x to X 4 or four intermediate sub- blocks W nl to W n4 .
- the ninth encryption level 69 corresponds exclusively to the supplementary encryption logic 240, the four outputs 135 to 138 of this logic 240 being identical to the four outputs 75 to 78 of the encryption level 69.
- the encryption unit 60 (FIG. 2) as overall logic for encrypting plain text blocks X, each of which corresponds to a sequence of 64 bits, has the following overall properties:
- Each block at outputs 75 to 78 is dependent on all blocks on the first inputs 25 to 28 and on almost all blocks on the second inputs 29, 30, 32, 33, 49, 52, in total of fifty-three blocks. (The output blocks are not dependent on three blocks each, which are present at the second inputs 129, 130, 132, 133 of the ninth encryption stage 69.)
- each bit of each block W (n + 1) 1 to W (n + 1 at the outputs 35 to 38 is dependent on all bits of all blocks W nl to W n4 and Z. n at the first
- an encryption unit 60 can either be used to encrypt a plain text block X or to decrypt a ciphertext block Y.
- the unit 60 can thus be used both for the encryption process X -> Y and for the decryption process Y -> X.
- FIG. 10 now shows fifty-two decryption sub-blocks u x to U 52 which are to be used for the decryption process Y -> X, in comparison to the key sub-blocks Z x to Z 52 and in their relationship to these key sub-blocks and to the nine encryption levels 61.1 , 61.2, 69 (Fig. 2).
- Y -> X are the negative values of the modulo-2 16 addition of the third and fourth key sub-blocks in the (10-i) th stage of the encryption process X -> Y.
- the invention allows a large number of variants. Some of these are listed below.
- Encryption logic 40 interchanged. However, it is also possible to construct the primary encryption logic 40 in a more complex manner and / or to omit the second inputs 49, 52 in such a variant.
- the principle can be broken that the types J j, j, f of the immediately successive operating units are always different. However, it is advantageous if at least the vast majority of all pairs of directly successive operations consist of two operations of different types [+ J,, +). •
- the key sub- blocks Z ⁇ to Z 52 are derived from the key block Z by a method other than the one described.
- the encryption unit 60 is primarily constructed using discrete operational units 41 to 44, 111 to 114, 115 to 120 as special logic units (hardware solution), primarily using commercially available processors and memories that work according to an assigned program ( Software solution) or in mixed construction.
- Each of the described logics 40, 140, 240, 60, 61.1, 61.2, 69 can be understood as a "black box" with first and second inputs and outputs.
- Each of these logics converts the two or four first sub-blocks adjacent to the first inputs into assigned second sub-blocks of the same length, which can be tapped at the outputs.
- the conversion process is influenced by the key sub-blocks applied to the second inputs, or more generally by suitable control blocks. Parallel inputs and outputs are advantageous if higher working speeds are required.
- the (second) length m is either 4, 8 or preferably 16 bits.
- the invention has the advantageous further property that it is relatively uncomplicated to set up and works quickly and easily both in the hardware and in the software version.
- the Encryption logics 40, 140, 240 can be built up from VLSI semiconductor components (VLSI very large scale integration) and can therefore be manufactured inexpensively.
- FIGS. 11 to 14 are modifications of FIGS. 8, 9, 2 and 10.
- FIG. 11 shows the block diagram of a second supplementary encryption logic 240v.
- This has two operation units 111v, 114v of the second type f and two operation units 112v, 113v of the first type [+].
- the outputs of the logic 240 are the same as the outputs 135 to 138 of the operational units IIIV to 114V.
- Fig. 12 shows the block diagram of a second encryption level 61.lv. This is formed from the combination of the supplementary encryption logic 24Ov and an expanded encryption logic 140, the outputs 135 to 138 of the logic 240v being directly (galvanically) connected to the inputs 125 to 128 of the subsequent logic 140.
- the inputs 25 to 28 of the respective encryption level (61.lv) are identical to the inputs 225 to 228 of the second, additional encryption logic 24Ov.
- the outputs of the extended logic 140 form the outputs 35 and 38 directly and cross-over the outputs 36 and 37 of the
- Encryption level 61.lv. The further structure corresponds completely to that of FIG. 9.
- FIG. 13 shows the block diagram of a second encryption unit 60v, which largely corresponds to FIG. 2.
- the inputs W 82 and W 83 are connected crosswise to ... W 22 and ... W 23 , respectively.
- FIG. 14 finally shows a second table of key sub-blocks Z n and decryption sub-blocks U n , corresponding to FIG. 10.
- Y -> X are equal to the modulo (2 16 +1) multiplication inverse of the first and fourth key sub-blocks in the (l ⁇ -i) th stage of the encryption process X -> Y.
- Y -> X are the negative values of the modulo-2 16 addition of the third and second key sub-blocks in the (10-i) th stage of the encryption process X -> Y.
- Z is 1. Furthermore, -Z j modulo-2 16 - added with Z is 0,
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE59100171T DE59100171C5 (de) | 1990-05-18 | 1991-05-16 | Vorrichtung für das umwandeln eines digitalblockes und verwendung derselben. |
AT91908542T ATE91208T1 (de) | 1990-05-18 | 1991-05-16 | Vorrichtung fuer das umwandeln eines digitalblockes und verwendung derselben. |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CH1690/90-8 | 1990-05-18 | ||
CH169090 | 1990-05-18 |
Publications (2)
Publication Number | Publication Date |
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WO1991018459A2 true WO1991018459A2 (de) | 1991-11-28 |
WO1991018459A3 WO1991018459A3 (de) | 1992-03-05 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/CH1991/000117 WO1991018459A2 (de) | 1990-05-18 | 1991-05-16 | Vorrichtung für das umwandeln eines digitalblockes und verwendung derselben |
Country Status (6)
Country | Link |
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US (1) | US5214703A (de) |
EP (1) | EP0482154B1 (de) |
JP (1) | JP3225440B2 (de) |
ES (1) | ES2042346T3 (de) |
HK (1) | HK1003338A1 (de) |
WO (1) | WO1991018459A2 (de) |
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CN103427987B (zh) * | 2012-05-25 | 2016-05-18 | 纬创资通股份有限公司 | 数据加密的方法、数据验证方法及电子装置 |
US10764282B2 (en) | 2017-06-12 | 2020-09-01 | Daniel Maurice Lerner | Protected and secured user-wearable devices for assured authentication and validation of data storage and transmission that utilize securitized containers |
US10154021B1 (en) | 2017-06-12 | 2018-12-11 | Ironclad Encryption Corporation | Securitization of temporal digital communications with authentication and validation of user and access devices |
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US10536445B1 (en) | 2017-06-12 | 2020-01-14 | Daniel Maurice Lerner | Discrete blockchain and blockchain communications |
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EP0382680B1 (de) * | 1989-02-08 | 1994-10-12 | Gretag Data Systems AG | Verfahren zum kryptographischen Behandeln von Daten und kryptographisches System |
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- 1991-05-16 US US07/781,235 patent/US5214703A/en not_active Expired - Lifetime
- 1991-05-16 ES ES199191908542T patent/ES2042346T3/es not_active Expired - Lifetime
- 1991-05-16 EP EP91908542A patent/EP0482154B1/de not_active Expired - Lifetime
- 1991-05-16 JP JP50811991A patent/JP3225440B2/ja not_active Expired - Lifetime
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US4255811A (en) * | 1975-03-25 | 1981-03-10 | International Business Machines Corporation | Key controlled block cipher cryptographic system |
EP0221538A2 (de) * | 1985-11-08 | 1987-05-13 | Nippon Telegraph And Telephone Corporation | Einrichtung und Verfahren zur Datenverschleierung |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6226382B1 (en) | 1994-02-28 | 2001-05-01 | Gemplus | Method for implementing a private-key communication protocol between two processing devices |
EP0800691B1 (de) * | 1994-12-28 | 1999-04-14 | Gemplus | Verfahren zum durchführen eines kommunikationsprotokolles mit geheimschlüssel zwischen zwei verarbeitungsvorrichtungen |
WO1997022192A1 (en) * | 1995-12-08 | 1997-06-19 | Northern Telecom Limited | Constructing symmetric ciphers using the cast design procedure |
US5825886A (en) * | 1995-12-08 | 1998-10-20 | Entrust Technologies Ltd. | Construction symmetric ciphers using the cast design procedure |
WO1999066669A2 (en) * | 1998-06-15 | 1999-12-23 | Rsa Security, Inc. | Block ciphers with integer multiplication, data-dependent and fixed number of rotations in each round |
WO1999066669A3 (en) * | 1998-06-15 | 2000-03-09 | Rsa Security Inc | Block ciphers with integer multiplication, data-dependent and fixed number of rotations in each round |
US6269163B1 (en) | 1998-06-15 | 2001-07-31 | Rsa Security Inc. | Enhanced block ciphers with data-dependent rotations |
AU761436B2 (en) * | 1998-06-15 | 2003-06-05 | Rsa Security Inc. | Enhanced block ciphers with data-dependent rotations |
US8117219B2 (en) | 2004-09-15 | 2012-02-14 | Ubs Ag | Generation of updatable anonymized data records for testing and developing purposes |
Also Published As
Publication number | Publication date |
---|---|
US5214703A (en) | 1993-05-25 |
EP0482154A1 (de) | 1992-04-29 |
WO1991018459A3 (de) | 1992-03-05 |
ES2042346T3 (es) | 1993-12-01 |
JPH05500121A (ja) | 1993-01-14 |
HK1003338A1 (en) | 1998-10-23 |
JP3225440B2 (ja) | 2001-11-05 |
EP0482154B1 (de) | 1993-06-30 |
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