WO1992001089A1 - Crystallisation process - Google Patents

Crystallisation process Download PDF

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Publication number
WO1992001089A1
WO1992001089A1 PCT/GB1991/001086 GB9101086W WO9201089A1 WO 1992001089 A1 WO1992001089 A1 WO 1992001089A1 GB 9101086 W GB9101086 W GB 9101086W WO 9201089 A1 WO9201089 A1 WO 9201089A1
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WO
WIPO (PCT)
Prior art keywords
gold
silicon
crystallisation
amorphous silicon
film
Prior art date
Application number
PCT/GB1991/001086
Other languages
French (fr)
Inventor
John Stoemenos
Original Assignee
Gec-Marconi Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gec-Marconi Limited filed Critical Gec-Marconi Limited
Publication of WO1992001089A1 publication Critical patent/WO1992001089A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B1/00—Single-crystal growth directly from the solid state
    • C30B1/02—Single-crystal growth directly from the solid state by thermal treatment, e.g. strain annealing
    • C30B1/023—Single-crystal growth directly from the solid state by thermal treatment, e.g. strain annealing from solids with amorphous structure
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02672—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using crystallisation enhancing elements

Definitions

  • This invention relates to the crystallisation of amorphous silicon.
  • Figure 1 shows a plan view taken after fifteen minutes anneal, with a diffraction inset showing amorphous material. One minute later, rapid crystallisation occurred resulting in micron size crystal formation, see Figure 2. Area A, as seen in Figure 3, is a large single crystal as can be seen from the diffraction pattern.
  • a number of black contamination spots are visible on all of the plan view figures relating to in situ-heating, and serve as position markers. Their presence is normal.
  • TEM, XTEM and SEM were used to characterise the crystallisation resulting from annealing amorphous silicon (a-Si ) films prepared using Plasma Enhanced Chemical Vapour Deposition (PECVD) overlying a thin gold film on a thermally-oxidised silicon base.
  • a-Si amorphous silicon
  • PECVD Plasma Enhanced Chemical Vapour Deposition
  • the a-Si thickness was estimated as l ⁇ m and the gold thickness as O.l ⁇ m.
  • the a-Si was hydrogenated during deposition.
  • Sample A is as described above.
  • Sample B the gold was distributed in an array of 50 ⁇ diameter dots in a lattice of several millimetres spacing.
  • Sample C was the control sample in which no gold was present.
  • Samples A, B and C were annealed at 600°C for 24hrs in a furnace after being sealed in an evacuated ampoule.
  • the film was completely amorphous.
  • a gold layer was present.
  • the film was amorphous.
  • the a-Si thickness was 0.9 m and the gold layer was about 40 to 50nm thick, see Figure 6.
  • Bad adhesion was observed both macro and microscopically. Immersion into acetone was sufficient to peel away large sections of the film due to the surface tension of the acetone. XTEM confirms this, as poor adhesion is seen in both the a-Si/gold layer and the gold/Si 0 2 layer. This bad adhesion was also seen macroscopically in sample B in the region of the gold dots. Note that there was no adhesion problem in sample C which had no gold content.
  • Gold dots Annealed at 600°C for 24 hrs.
  • the microstructure was mostly a-Si with areas of defective mosaic polysilicon. SEM impression (secondary image, no tilt, cleaning or coating).
  • Films of amorphous silicon of thickness 300nm were deposited onto silicon wafers by LPCVD, rather than PECVD as used before, in order to reduce the hydrogen content and thereby reduce the damage to the film from hydrogen evolution during the anneal/crystallisation. These films were cleaned by plasma etching and then coated with 60nm of gold. Samples were taken from these wafers and were placed in quartz ampoules which were evacuated and then annealed for 24 hours, some at 500°C and some at 600°C.
  • FIGS 11,12 are cross sectional TEMs from the hazy areas of the sample which show that a film of pure silicon has been formed over the surface of the sample and a gold/silicon alloy nearest the substrate. Between pure silicon film and the gold/silicon alloy is a thin interlayer about 1.5nm thick. In addition, a number of small gold particles remain on the surface of the sample.
  • FIG. 13 A plan view micrograph (Figure 13) from the same area shows a mixture of silicon and gold crystallites, but diffraction patterns from the film reveal the presence of substantial single crystalline areas (see insets to Figures 11 and 13). This is attributed to the "single" crystalline silicon overlayer, which is clearly revealed by the cross sectional mi rographs.
  • the gold in order for this process to occur, the gold must be in intimate contact with the amorphous silicon, i.e. intermediate contamination layers of, for example, native oxide must not be present or must be very thin. Except in so far as it may affect the nature of any intermediate layers, it does not matter whether the gold is on top of the silicon or vice versa. Both positions have been shown to be effective.

Abstract

In a process for the crystallisation of amorphous silicon, gold is disposed in intimate contact with the amorphous silicon, and the silicon and the gold are annealed at a temperature of at least 400 °C. The amorphous silicon is preferably deposited on a substrate, with the gold disposed over the silicon or between the silicon and the substrate. The gold may be deposited as a matrix of dots.

Description

Crystanisation Process
This invention relates to the crystallisation of amorphous silicon.
It is an object of the invention to provide a process for crystallisation of amorphous silicon in which the speed of crystallisation is increased relative to that obtainable using conventional processes- According to the invention there is provided a process for the crystallisation of amorphous silicon, wherein gold is disposed in intimate contact with the amorphous silicon, and the silicon and the gold are annealed at a temperature of at least 400°C.
Embodiments of the invention will now be described, by way of example, with reference to the accompanying figures, which show, greatly magnified, the structures of various samples.
During in-situ heating TE experiments on amorphous silicon (GEC RB285 grown at 540°C, 2500A thick), rapid crystallisation was observed in plan view after 15 minutes at 650°C. The effect was observed only in association with a gold specimen grid in intimate contact with the amorphous silicon. When a molybdenum grid was substituted for the gold, a much slower, normal, crystallisation occurred at 650°C. The assumption is made that the gold acted to inititate a rapid reaction.
Figure 1 shows a plan view taken after fifteen minutes anneal, with a diffraction inset showing amorphous material. One minute later, rapid crystallisation occurred resulting in micron size crystal formation, see Figure 2. Area A, as seen in Figure 3, is a large single crystal as can be seen from the diffraction pattern.
A number of black contamination spots are visible on all of the plan view figures relating to in situ-heating, and serve as position markers. Their presence is normal.
In an attempt to clarify the role of gold in initiating this rapid reaction an experiment was performed. The same amorphous material was cleaned and etched in HF to remove oxide, and then a o layer of gold of nominal thickness 200A was sputtered on to the surface. The sample was then annealed in air at 630°C for two hours. XTEM revealed that no reaction had taken place between the gold and the the silicon. A thin contamination layer was observed separating the gold from the silicon. The contamination on the control sample which was not sputtered with gold is not visible due to the low contrast with an epoxy resin used to support the film, but it is assumed to exist.
It is hypothesised that a diffusion of silicon into the gold forms a liquid phase which initiates silicon crystal precipitation, subsequent nucleation and rapid reorganisation of grain boundaries enriched in gold.
The following experiments were carried out to confirm this hypothesis.
TEM, XTEM and SEM were used to characterise the crystallisation resulting from annealing amorphous silicon (a-Si ) films prepared using Plasma Enhanced Chemical Vapour Deposition (PECVD) overlying a thin gold film on a thermally-oxidised silicon base. The a-Si thickness was estimated as lμm and the gold thickness as O.lμm. The a-Si was hydrogenated during deposition.
Sample A is as described above.
In Sample B the gold was distributed in an array of 50 ι diameter dots in a lattice of several millimetres spacing.
Sample C was the control sample in which no gold was present.
Samples A, B and C were annealed at 600°C for 24hrs in a furnace after being sealed in an evacuated ampoule.
The following observations were made:- Control sample C
No gold, No Anneal.
As expected, the film was completely amorphous.
No gold. Anneal at 600°C for 24 hrs.
As expected, no crystallisation occurred. The approximately 5% hydrogenation introduced by the PECVD process is known to inhibit crystallisation at this temperature. A temperature of 720°C would be required to crystallise the silicon. This is a well-documented observation in the literature and we have also observed this effect in annealed specimens, see cross-section (XTEM) micrograph Figure 5.
Sample A
A gold layer was present.
No anneal .
The film was amorphous. The a-Si thickness was 0.9 m and the gold layer was about 40 to 50nm thick, see Figure 6. Bad adhesion was observed both macro and microscopically. Immersion into acetone was sufficient to peel away large sections of the film due to the surface tension of the acetone. XTEM confirms this, as poor adhesion is seen in both the a-Si/gold layer and the gold/Si 02 layer. This bad adhesion was also seen macroscopically in sample B in the region of the gold dots. Note that there was no adhesion problem in sample C which had no gold content.
Gold,600°C anneal for 24 hrs.
About 80% of the film was observed macroscopically to have peeled off. The plan view of these peels shows them to be largely amorphous with a small percentage crystallised with the defective mosaic microstructure observed in previous work on thermal crystallisation of a-Si. From these peels, as well as those portions adhering to the substrate, three different morphologies are distinguished and verified by XTEM:
1) Crystallised polysilicon of the defective mosaic structure type typical of thermal crystallisation with bands of defect in the grains. These areas had a bad adherence to the substrate, see Figure 7 which is a XTEM micrograph.
2) Areas of polysilicon with sharp grain boundaries and grain size of 0.2-0.3pm. Traces of gold are found at boundaries, but clearly separated from the crystal. These areas were found not well adhered to the substrate but were in good contact with the gold.
3) Areas of very large Si crystals with a grain diameter of about 6um and a thickness of 0.5pm. These crystals are located at the gold/silicon interface. Gold particles were found concentrated at the Si/Au/Si02 interface as well as at the polysilicon/large silicon crystal interfaces, but mostly at the former, see Figure 8 which is an XTEM micrograph and Figure 9 which is a plan view micrograph. The high quality of the silicon crystals may be seen from the diffraction pattern in Figure 10.
Sample B
Gold dots. Annealed at 600°C for 24 hrs.
The microstructure was mostly a-Si with areas of defective mosaic polysilicon. SEM impression (secondary image, no tilt, cleaning or coating).
To summarise, crystallisation was found to occur in annealed samples only when gold was present.
Samples without gold did not crystallise during the 600°C 24 hr anneal. Large βμm diameter crystals of 0.5 μm thickness were formed when there was good adhesion between a-Si and the gold. A large fraction of the film area showed poor adhesion of the gold to the amorphous silicon, and poor adhesion of the gold to thermal Si02. These large crystals developed at the gold/a-Si interface anu were approximately 50% of the crystallised film volume. Polysilicon formed in the remaining top half of the film with a grain size of about 0.25 urn. This polysilicon had sharp grain boundaries as opposed to the defective mosaic structure common in thermally crystallised amorphous silicon.
Large crystals grew only when there was good adhesion of the a-Si with the Au/Si02. The large crystals grew until about halfway through the film thickness and then polysilicon growth began abruptly with small traces of gold.
When adhesion was bad, the a-Si always crystallised into polysilicon with gold traces or with the defective mosaic structure. In the latter case, no traces of gold were observed. In regions where the film had good contact but became detached and was held off the substrate in a cantilevered way, there was an abrupt transition of the two types of polysilicon growth mode a short distance from the bonded site.
After crystallisation, most of the gold formed as droplets on the Siθ2/large crystal interface, with a small amount on the polysilicon/large crystal interface. Very few defects were observed inside the large crystal, mainly stacking faults.
The purpose of the above-described experiments was to determine conclusively the effect of gold on the crystallisation of amorphous silicon. The gold was put at the Si02 interface to ensure contact and minimise contamination. Gold clearly has a strong effect. For practical reasons the gold should be on the top surface of the a-Si.
In order to investigate this, further samples were prepared as follows:
Films of amorphous silicon of thickness 300nm were deposited onto silicon wafers by LPCVD, rather than PECVD as used before, in order to reduce the hydrogen content and thereby reduce the damage to the film from hydrogen evolution during the anneal/crystallisation. These films were cleaned by plasma etching and then coated with 60nm of gold. Samples were taken from these wafers and were placed in quartz ampoules which were evacuated and then annealed for 24 hours, some at 500°C and some at 600°C.
The same behaviour was observed in the samples regardless of the annealing temperature employed. The appearance of the surface altered, so that some areas were shiny and others were hazy. Electron microscopy revealed that the hazy areas were those in which the crystallisation process had occurred and large grains had been formed. Figures 11,12 are cross sectional TEMs from the hazy areas of the sample which show that a film of pure silicon has been formed over the surface of the sample and a gold/silicon alloy nearest the substrate. Between pure silicon film and the gold/silicon alloy is a thin interlayer about 1.5nm thick. In addition, a number of small gold particles remain on the surface of the sample. A plan view micrograph (Figure 13) from the same area shows a mixture of silicon and gold crystallites, but diffraction patterns from the film reveal the presence of substantial single crystalline areas (see insets to Figures 11 and 13). This is attributed to the "single" crystalline silicon overlayer, which is clearly revealed by the cross sectional mi rographs.
To summarise the present invention, it is confirmed that the presence of gold results in crystallisation of amorphous silicon films to form very large (^ 6pm) grains on annealing at temperatures of at least 400°C and preferably in the range 500°C - 600°C which would normally result only in the formation of small crystallites (O.lμ ) with a defective mosaic structure.
It has been shown that, in order for this process to occur, the gold must be in intimate contact with the amorphous silicon, i.e. intermediate contamination layers of, for example, native oxide must not be present or must be very thin. Except in so far as it may affect the nature of any intermediate layers, it does not matter whether the gold is on top of the silicon or vice versa. Both positions have been shown to be effective.
The temperatures used here are considerably higher than those used in earlier work by Hultman et al. [Journal of Applied Physics, Vol.62, page 3647, (1987), L. Hultman, A. Robertsson, H.J.G. Hentzell , I. Engstrom and P.A. Psaras, "Crystallisation of Amorphous Silicon during Thin Film Gold Reaction." ] and this has made it possible to produce much larger grains which are advantageous for the fabrication of active devices, e.g. thin film transistors. The higher temperatures used also produce a further increase in the crystallisation rate. The Hultman publication was concerned with the nature of the gold/silicon alloys and compounds formed during the process rather than with crystallisation of polysilicon. Therefore, no grain size is quoted for the polysilicon films disclosed in the article, but it is clear from the photographs therein that the grains are much smaller than those obtained by use of the present invention.

Claims

Claims
1. A process for the crystallisation of amorphous silicon, wherein gold is disposed in intimate contact with the amorphous silicon, and the silicon and the gold are annealed at a temperature of at least 400°C.
2. A process as claimed in Claim 1, wherein the amorphous silicon is deposited on a silicon substrate.
3. A process as claimed in Claim 2, wherein the substrate is formed of thermally-oxidised silicon.
4. A process as claimed in any preceding claim, wherein the • amorphous silicon is formed as a layer, and the gold is deposited thereon or thereunder as a matrix of dots.
5. A process for the crystallisation of amorphous silicon substantially as hereinbefore described with reference to the accompanying drawings.
PCT/GB1991/001086 1990-07-03 1991-07-03 Crystallisation process WO1992001089A1 (en)

Applications Claiming Priority (2)

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GB9014723.2 1990-07-03
GB909014723A GB9014723D0 (en) 1990-07-03 1990-07-03 Crystallisation process

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Cited By (5)

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Publication number Priority date Publication date Assignee Title
EP0609867A2 (en) * 1993-02-03 1994-08-10 Semiconductor Energy Laboratory Co., Ltd. Process for fabricating a semiconductor crystallized layer and process for fabricating a semiconductor device using the same
EP0612102A2 (en) * 1993-02-15 1994-08-24 Semiconductor Energy Laboratory Co., Ltd. Crystallized semiconductor layer, semiconductor device using the same and process for their fabrication
EP0656644A1 (en) * 1993-12-02 1995-06-07 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a crystallized semiconductor layer and semiconductor devices using it
KR100273827B1 (en) * 1993-10-29 2001-01-15 야마자끼 순페이 Semiconductor devices
US6730549B1 (en) 1993-06-25 2004-05-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for its preparation

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US6997985B1 (en) 1993-02-15 2006-02-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor, semiconductor device, and method for fabricating the same

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EP0334110A2 (en) * 1988-03-24 1989-09-27 Siemens Aktiengesellschaft Process for producing polycristalline layers with large crystals for thin film semiconductor devices, like solar cells

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Title
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Applied Surface Science, vol. 36, nos. 1-4, North-Holland Physics Publ. Division, Amsterdam, NL; S. Caune et al.: "Combined CW laser and furnace annealing of amorphous silicon and germanium in contact with some metals", pages 597-604, see page 602, paragraphs 3 and 4, table 2 *
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Journal Of Non-Crystalline Solids, vol. 7, 1972, S.R. Herd et al.: "Metal contact induced crystallization in films of amorphous silicon and germanium", pages 309-327, see page 311, paragraphs 3-5 *

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EP0609867A3 (en) * 1993-02-03 1995-01-11 Semiconductor Energy Lab Process for fabricating a semiconductor crystallized layer and process for fabricating a semiconductor device using the same.
EP1207549A3 (en) * 1993-02-03 2010-07-07 Semiconductor Energy Laboratory Co., Ltd. Method for fabricating a semiconductor device
EP0997950A2 (en) * 1993-02-03 2000-05-03 Semiconductor Energy Laboratory Co., Ltd. Method of improving the crystallization of semiconductor films particularly for thin film transistors
KR100267145B1 (en) * 1993-02-03 2000-10-16 야마자끼 순페이 A method of manufacturing a thin film transistor
EP0997950A3 (en) * 1993-02-03 2009-01-28 Semiconductor Energy Laboratory Co., Ltd. Method of improving the crystallization of semiconductor films particularly for thin film transistors
CN100416750C (en) * 1993-02-03 2008-09-03 株式会社半导体能源研究所 Semiconductor manufacturing technology and semiconductor device manufacturing technology
EP0609867A2 (en) * 1993-02-03 1994-08-10 Semiconductor Energy Laboratory Co., Ltd. Process for fabricating a semiconductor crystallized layer and process for fabricating a semiconductor device using the same
US6610142B1 (en) 1993-02-03 2003-08-26 Semiconductor Energy Laboratory Co., Ltd. Process for fabricating semiconductor and process for fabricating semiconductor device
EP0612102A2 (en) * 1993-02-15 1994-08-24 Semiconductor Energy Laboratory Co., Ltd. Crystallized semiconductor layer, semiconductor device using the same and process for their fabrication
EP0612102A3 (en) * 1993-02-15 1994-10-19 Semiconductor Energy Lab Crystallized semiconductor layer, semiconductor device using the same and process for their fabrication.
US6084247A (en) * 1993-02-15 2000-07-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a catalyst enhanced crystallized layer
US6756657B1 (en) 1993-06-25 2004-06-29 Semiconductor Energy Laboratory Co., Ltd. Method of preparing a semiconductor having controlled crystal orientation
US6730549B1 (en) 1993-06-25 2004-05-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for its preparation
US7148094B2 (en) 1993-06-25 2006-12-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for its preparation
US6335541B1 (en) 1993-10-29 2002-01-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor thin film transistor with crystal orientation
US6285042B1 (en) 1993-10-29 2001-09-04 Semiconductor Energy Laboratory Co., Ltd. Active Matry Display
US6998639B2 (en) 1993-10-29 2006-02-14 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device
KR100273831B1 (en) * 1993-10-29 2001-01-15 야마자끼 순페이 Method for manufacturing semiconductor device
KR100273827B1 (en) * 1993-10-29 2001-01-15 야마자끼 순페이 Semiconductor devices
US7998844B2 (en) 1993-10-29 2011-08-16 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device
EP0656644A1 (en) * 1993-12-02 1995-06-07 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a crystallized semiconductor layer and semiconductor devices using it

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EP0489900A1 (en) 1992-06-17
GB2245552A (en) 1992-01-08
GB9114398D0 (en) 1991-08-21
JPH05501701A (en) 1993-04-02
GB9014723D0 (en) 1990-08-22

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