WO1992020068A1

WO1992020068A1 - Fast memory system employing mostly good memories

Info

Publication number: WO1992020068A1
Application number: PCT/US1991/003184
Authority: WO
Inventors: Ilya Kahn
Original assignee: Sophos Technologic
Priority date: 1991-05-07
Filing date: 1991-05-07
Publication date: 1992-11-12

Abstract

A memory system (10) for use with a processor (12) which provides a memory bus (14) and an address bus (38). The inventive system includes a plurality of mostly good memory blocks (21-36) connected to the address bus (38), each block having a defect at a defect address. A programmable memory (PROMs A and B) is connected to the processor memory bus (14) for storing the addresses of the defects in the mostly good memories (21-36). A redundant memory (42 and 44) provides rows and columns of good memory at addresses corresponding to the addresses of the defects in the mostly good memories (21-36). A selector controller (40) selectively activates the redundant memory when an address is placed on the memory bus (14) which corresponds to an address of a defect in one of the mostly good memories (21-36).

Description

FAST MEMORY SYSTEM EMPLOYING MOSTLY GOOD MEMORIES

BACKGROUND OF THE INVENTION

Field of the Invention:

The present invention relates to memory systems . More specifically , the present invention relates to memory systems using mostly good memories.

While the present invention is described herein with reference to illustrative embodiments for particular applications, it should be understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional modifications , applications , and embodiments within the scope thereof and additional f ields in which the present invention would be of significant utility.

Description of the Related Art:

In some countries , computer memory chips with zero defects are expensive and/or in limited supply. Memory chips with defects are typically considerably less expensive and more available. Mostly good memory chips have a large number of good memory cells and very few defects . In view of the lower cost and greater supply of mostly good memories , there has been a need for technique for util iz ing defective or mostly good memories . This need is addressed somewhat by the invention of U. S. Patent 4,376,300, issued March 8, 1983 to S. K. Tsang entitled Memory System Employing Mostly Good Memories. As disclosed in the reference, a redundant memory chip is used to store data designated to the defective locations in the mostly good memories. In one embodiment, a PROM is programmed to recognize the addresses of the defective elements and to cause the redundant memory to be selected. This embodiment is generally limited to use with a small number of defective chips having either defective rows only or defective columns only. In another embodiment, a content- addressable memory is employed to provide a new address in response to the addresses of defective elements in the mostly good memories.

Unfortunately, the referenced system is slow in that the access time of the memory system is generally longer than that of a conventional memory system. Obviously, this presents significant limitations on the system with respect to timing considerations vis-a-vis the host system.

Accordingly, a need remains in the art for a system for employing mostly good memories which offers an access time comparable with conventional memories employing good memory chips.

SUMMARY OF THE INVENTION

The need in the art is addressed by the present invention which provides a memory system for use with a processor which provides a memory bus and an address bus. The inventive system includes a plurality of mostly good memory blocks connected to the address bus, each block having a defect at a defect address. A programmable memory is connected to the processor memory bus for storing the addresses of the defects in the mostly good memories. A redundant memory provides rows and columns of good memory at addresses corresponding to the addresses of the defects in the mostly good memories. A selector controller selectively activates the redundant memory when an address is placed on the memory bus which corresponds to an address of a defect in one of the mostly good memories.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. la is a block diagram of a first embodiment of the memory system utilizing the teachings of the present invention.

Fig. lb is a block diagram of the CAS selector of the present invention. Fig. lc shows the timing diagram for the memory system of the present invention which is the same as a standard timing diagram for a dynamic memory.

Fig 2a shows a first alternative embodiment of the memory system of the present invention. Fig. 2b is a block diagram of the CAS selector of Fig. 2a.

Fig. 3a shows a second alternative embodiment of the inventive memory system in which the principles of the present invention are extended to the selection of redundant segments or fields of memory within a redundant memory.

Fig. 3b shows more detail of a block of redundant memory of Fig. 3a.

Fig. 3c shows the design of the CAS selector which generates the CAS signals for the redundant memories of Fig. 3a.

Fig. 4a shows a third alternative embodiment of the memory system of the present invention.

Fig. 4b shows an illustrative implementation of the selector controller of Fig. 4a.

Fig. 5a shows a fourth alternative embodiment of a memory system of the present invention constructed in accordance with the present teachings.

Fig. 5b shows an illustrative implementation of the controller of Fig. 5a.

DESCRIPTION OF THE INVENTION

Illustrative embodiments and exemplary applications will now be described with reference to the accompanying drawings to disclose the advantageous teachings of the present invention. Fig. la is a block diagram of a first embodiment of the memory system 10 utilizing the teachings of the present invention . The system 10 is adapted for connection to a microprocessor 12 having a memory bus 14. In a typical implementation, using 64k memory chips , the memory bus 14 has 20 lines making it possible to address a 1 Meg address space . Sixteen lines are used for address selection and four l ines are used for chip selection . Of the sixteen address lines , the first eight are for the row address of memory selected by the microprocessor 12 and are input to a first programmable read-only memory "PROM A" 16. The second eight are for the column addres s o f memory sel ected by the microprocessor 12 and are input to a second programmable read-only memory "PROM B" 18 . Address signals on the memory bus 14 are provided to a plurality of one bit most ly good memor i es 2 1 - 3 6 v i a a 2 : 1 addre s s multiplexer 20 and an address bus 38 .

In the embodiment of Fig . la , each of the mostly good memories 21 - 36 has a defect at a unique address relative to the other memories . The address of each defect is stored in the PROMs A and B. For example, PROM A stores defective row addresses and PROM B stores defective column addresses .

First and second redundant memories "Memory A" and "Memory B" , 42 and 44 respectively, are connected to the address bus 38 and have good memory cells at row and column addresses , respectively , corresponding to the defect addresses of the mostly good memories 21 - 36 . Thus , the mostly good memories 21 - 36 and the redundant memories 42 and 44 all have different location addresses of defective rows and columns . In the illustrative implementation , memory A stores data intended for defective row addresses in the mostly good memories and memory B stores data intended for defective column addresses in the mostly good memories .

When the microprocessor 12 selects an address corresponding to a defective cell in one of the mostly good memories , the corresponding PROM A or B provides a signal to a CAS selector 40. Fig. lb is a block diagram of the CAS selector 40 of the present invention . As shown in Fig . lb , the CAS selector 4 0 includes a demultiplexer 41 , a timing control circuit 43 and a logic circuit 45. The logic circuit 45 includes an AND gate 47 connected to the outputs of the PROMs A and B , an inverter 49 connected to the output of PROM B , a NAND gate 51 connected to the output of PROM A and the inverter 49 , and first and second OR gates 53 and 55. In the alternative , the CAS selector 40 may be implemented with a programmable logic device. The timing control circuit 43 receives read and write control lines from the microprocessor 12. The demultiplexer 41 receives the four address lines from the memory bus 14 and provides CAS 1 - CAS 16. The logic circuit 45 provides control signals CAS RMA and CAS RMB for the redundant memories 42 and 44 respectively. Thus, the CAS selector 40 outputs chip select signals to the mostly good memories 21 - 36 in accordance with a normal mode of operation and selects redundant memory A or B when a defect address is detected on the memory bus 14 by the PROMS 16 and 18. That is, when the microprocessor 12 selects an address corresponding to a defective cell in one of the mostly good memories, the corresponding PROM, A or B or both, provides a signal to a CAS selector 40, the CAS selector selects the appropriate redundant memory. Data I/O is then provided in a conventional manner via an I/O bus 46.

A significant feature of the invention is that the PROMS 16 and 18 are connected directly to the microprocessor 12 via the memory bus 14 instead of the address bus as per prior teachings. As discussed below, this allows the system 10 to be initiated on receipt of a RAS (row address select) signal from the CAS selector 40 at the very moment when the microprocessor 12 starts the read or write operation. Thus, speed of operation is enhanced and access time is minimized. Further, the system 10 is not limited to use with either defective rows or defective columns of memory as per the above- noted U. S. patent at column 4, lines 37 - 43. Both defective row and defective column memories may be utilized simultaneously in the present system.

Fig. lc shows a timing diagram for the present invention which is the same as a standard timing diagram for a dynamic memory. Fig. lc(l) shows the complement of the RAS (row address select) signal from the standard memory bus. Fig. lc(2) shows the complement of the CAS (column address select) signal from the microprocessor 12, Fig. lc(3) shows the address signals from the microprocessor 12, Fig. lc(4) shows the complement of the write enable (WE) signal, and Fig. lc(5) shows the output of memory signal (Q) . At time t₀, the signals states are as shown. At time t^ the CAS' signal goes high and an address transition takes place and the row address is placed on the memory bus 14. At time t₂ the RAS • signal goes low initiating the operation of the memory system 10 of the present invention. The system 10 reads the row address. At time t₃, the row address is removed from the bus and at time t₄, the column address is applied to the bus and the WE' signal goes high. At time t₅, the CAS' signal goes low, the system 10 reads the column address and the Q signal goes to 0 or 1 indicating active output from memory. Then at time t₆ data becomes valid. The time period between t₄ and t₆ is t^ and represents the time between column address and valid data. At time t₇ the RAS' and CAS' signals go high and the memory signal Q goes to the third state, completing the cycle. Redundant memory is selected, if at all, during t_{R D}, between application of the RAS' and CAS' signals. During time period t_j^_jj, column address and column address select signals are not provided to dynamic memory, CAS selector uses this time and information about CAS address to which memory (main or redundant will be chosen at time 't₅. This allows use of defective memory systems at the same speed as good memory systems. (Note that in the illustrative embodiment, t_AA = 40 ns.) That is, in accordance with the present teachings, the connection of the PROMS 16 and 18 to the memory bus 14 allows for the memory system 10 to have an access time comparable to conventional systems because of the possibility of using PROMs with access time on the order of 20 to 25 ns, using current technology, and, as a CAS selector, a programmable logic device with a delay time of 7 to 10 ns.

The embodiment of Fig. la, has the constraint that each address of each defect has to be unique and the redundant memory 42 can have only defective columns while redundant memory 44 can have only defective rows. Fig 2a shows a first alternative embodiment of the memory system 100 of the present invention. The system 100 is essentially identical to that of Fig. la with the exception that the first redundant memory 142 consists of three redundant memories 143, 145 (not shown) and 147 and the second redundant memory 144 consists of three redundant memories 149, 151, 153. The PROMS 116 and 118 are modified to provide two bit outputs instead of one bit outputs. Fig. 2b is a block diagram of the CAS selector 140 of Fig. 2a. As shown in Fig. 2b, the CAS selector 140 of Fig. 2a is modified to control the 6 redundant memories RMA 1 - 3 and RMB 1 - 3. The additional controls are provided by a logic circuit 145 and additional demultiplexers 147 and 149.

The memory system 100 of Fig 2a is more flexible than the memory system 10 of Fig. la in that a set of 38 chips (including redundant memories) may be used with no more than three defective rows at any given address in all the chips. For example, Row 7 can be defective in no more than three chips of the 38. This principle of a maximum of three defects applies to every row and every column. If the number of redundant memories is reduced from three to two, the maximum number of defective rows or columns in any position is limited to two.

Fig. 3a shows a second alternative embodiment of the memory system 200 in which the principles of the present invention are extended to the selection of redundant segments or fields of memory within a redundant memory 242, 244. Fig. 3b shows more detail of a block of redundant memory 242, 244 of Fig. 3a. The redundant memory includes two rows 280 and 282 of four segments of memory 284. In this illustrative embodiment, each of the eight segments of memory 284 are 128 bits wide and 256 bits deep. Thus, the memory 242, 244 is a 256K bit memory. The RAS signal selects the desired row 280 or 282. The CAS signal along with the address selects one of the segments and a particular bit within a segment. For example, if row 280 is selected, segments 1 and 2 or 3 and 4 could be selected by a change of one bit in the CAS address.

Fig. 3c shows the design of the CAS selector 240 of Fig. 3a which generates the CAS signals for segments of memory within the redundant memories as discussed above along with two address bits for each memory.

Fig. 4a shows a third alternative embodiment of the memory system 300 of the present invention. Here system 300 is adapted for connection to the address bus 338 and therefore the access time is longer because of the requirement that the PROMS receive control signals from a multiplexer (not shown) instead of the microprocessor 312. Each of the PROMS 316 and 318 include a latch 317 and 319, respectively. The latches 317 and 319 store the RAS and CAS address signals as the PROMS 316 and 318 may not be fast enough to respond to same within the time allotted.

Fig. 4b shows an illustrative implementation of the selector controller 340 of Fig. 4a. In operation, redundant memories RMA and RMB 342 and 344 work, at the beginning of every read or write operation, as if it is a read operation. In a read cycle, a data control circuit 345 connects memories Ml - Ml6 or redundant memories 342 and 344 with the computer data bus 338. In a write cycle, a timing control circuit 343 puts a write signal for one of the redundant memories only it is necessary, according to data from PROM A and PROM B. The timing and data control circuits may be implemented with 343 and 345 may be implemented with logic circuits.

Fig. 5a shows a fourth alternative embodiment of a memory system 400 of the present invention constructed in accordance with the present teachings. The embodiment of Fig. 5a provides wider or deeper multi-bit (16 bit) mostly good memories 420 with minimal required redundant memories 442 and 444 through the use of associated write multiplexers 460 and 464 and read multiplexers or decoders 462 and 466, respectively.

Fig. 5b shows an illustrative implementation of the controller 440 of Fig. 5a. The controller 440 includes essentially the same CAS selector as used in Fig. lb, Fig. 2b and Fig. 3b. A data selector 441 is added to control two multiplexers 443 and 445 and two demultiplexers 447 and 449. The data selector may be implemented with a logic circuit. In operation, the controller 440 connects RMA or RMB or both with the microprocessor data bus.

Thus, the present invention has been described herein with reference to a particular embodiment for a particular application. Those having ordinary skill in the art and access to the present teachings will recognize additional modifications applications and embodiments within the scope thereof.

It is therefore intended by the appended claims to cover any and all such applications, modifications and embodiments within the scope of the present invention. Accordingly,

WHAT IS CLAIMED IS:

Claims

1. A memory system for use with processor means for providing a memory bus and an address bus, said memory system comprising: a plurality of mostly good memory blocks connected to said address bus, each block having a defect at a defect address; programmable memory means, connected to said processor memory bus, for storing the addresses of said defects in said mostly good memories; redundant memory means for providing rows and columns of good memory at addresses corresponding to the addresses of said defects in said mostly good memories; and selector means for selectively activating said redundant memory means when an address is placed on said memory bus which corresponds to an address of a defect in one of said mostly good memories.

2. The invention of Claim 1 wherein said memory bus is directly connected to said processor.

3. The invention of Claim 2 including an address multiplexer for connecting said address bus to said memory bus.