WO1993004499A1 - An improved antifuse and method of manufacture thereof - Google Patents

An improved antifuse and method of manufacture thereof Download PDF

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Publication number
WO1993004499A1
WO1993004499A1 PCT/US1992/006913 US9206913W WO9304499A1 WO 1993004499 A1 WO1993004499 A1 WO 1993004499A1 US 9206913 W US9206913 W US 9206913W WO 9304499 A1 WO9304499 A1 WO 9304499A1
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WIPO (PCT)
Prior art keywords
layer
barrier layer
interconnection line
amorphous silicon
barrier
Prior art date
Application number
PCT/US1992/006913
Other languages
French (fr)
Inventor
Richard Klein
Pankaj Dixit
William P. Ingram, Iii
Laurence H. Cooke
Original Assignee
Crosspoint Solutions, Inc.
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Publication date
Application filed by Crosspoint Solutions, Inc. filed Critical Crosspoint Solutions, Inc.
Publication of WO1993004499A1 publication Critical patent/WO1993004499A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the thickness and the contours of the amorphous silicon layer are known to affect the programming of the antifuse. For example, the thicker the amorphous silicon layer the larger the voltage required to program the antifuse.
  • the amorphous silicon layer is deposited into vias in the intervening silicon dioxide layer which insulates the two interconnection lines from each other. I the amorphous silicon layer is folded, as in this case, the edge effects complicate the electrical performance of the antifuse.
  • the inherent height variation of the vias formed in the intervening silicon dioxide layer adversely affects the thickness uniformity of the amorphous silicon layer at the bottom of the vias.
  • the electrical performance, e.g., the programming voltages, of the resulting antifuses therefore, have large variations. This is undesirable.
  • a second insulating layer 16 of silicon dioxide is deposited on the first insulating layer 19 to cover the first interconnection line 20 and the antifuse stack 23.
  • the insulating layer 16 is formed from doped or undoped silicon dioxide, or silicate or siloxane films or combinations of these materials, to a thickness in the range from 5000 A to 15000 A.
  • the insulating layer 16 is planarized to make the top surface of the layer 16 as flat as possible.
  • a refractory metal may be used for the barrier layers 13 and 15, and optional barrier layers 11 and 17.
  • the term, "refractory metal,” is used to encompass refractory metals, their intermetallics, alloys, silicides, nitrides and combinations thereof.
  • a titanium- tungsten alloy works very well for all the barrier layers 11, 13, 15, and 17. Thicknesses range from 500 to 1500 A.

Abstract

A structure for antifuses between two vertically metal interconnection lines and method of manufacture is provided. On a portion of a first metal interconnection line an antifuse stack having at least an amorphous silicon layer (14) and a first barrier layer (15) on the amorphous silicon layer is placed. The first interconnection line and antifuse stack is covered with an insulating layer (16) having a via (27) which exposes the first barrier layer (15). The second metal interconnection line (18, 17) contacts the first barrier layer (15) through the via to form an antifuse between the first and second metal interconnection lines. A second barrier layer (13) placed beneath the amorphous silicon layer (14) may be formed as part of the first metal interconnection line or part of the antifuse stack. A compact self-aligned structure is also provided.

Description

AN IMPROVED ANTIFUSE AND METHOD OF MANUFACTURE THEREOF
BACKGROUND OF THE INVENTION
The invention relates generally to the field of programmable semiconductor structures in integrated circuit devices, and, more particularly, to antifuses which are typically found in user-programmable or field programmable gate arrays (FPGAs) .
Gate arrays are largely a matrix of integrated circuit structures, such as logic gates and their associated input and output structures which are isolated from one another. In conventional, or mask-programmable, gate arrays (MPGAs) the wiring interconnections are created by depositing, masking, and etching the metal interconnection layers and contact layers to connect the logic gates and input and output structures to perform the user-specified function. This is performed at the vendor's facility.
In a field programmable gate array (FPGA) , the FPGA is completely formed with a global set of vertical and horizontal wiring segments which are built into the device. With electrically programmable interconnect structures known as antifuses, the user defines the specified interconnection pattern for the particular application in mind very rapidly by programming these antifuses.
However, FPGAs heretofore have had certain disadvantages in performance and use. Ideally antifuse structures should have a very high resistance (to form essentially an open circuit) and low capacitance in the unprogrammed ("off") state, as well as a very low resistance (to form essentially a closed circuit) in the programmed ("on") state. Furthermore, antifuse structures should occupy minimal layout area, with very short programming times, and programming voltages which are not so high as to require additional process complexity to accommodate the high programming voltages. Because present antifuse structures do not meet all these requirements, FPGA have suffered in performance.
A more subtle disadvantage is that the performance of present day antifuse structures has required that the architecture of the FPGA be modified so that the FPGA, once programmed, does not behave like an identically-programmed MPGA. Because of the large numbers of users already familiar with the architecture and usage of MPGAs, it is desirable that the FPGA match a MPGA in gate density and performance. The electrical and physical characteristics of present antifuse structures impede progress toward a high- performance, low-cost FPGA, which matches MPGA performance levels.
An improved antifuse which overcomes these problems is disclosed in a patent application entitled by "AN IMPROVED ANTIFUSE CIRCUIT STRUCTURE FOR USE IN A FIELD PROGRAMMABLE GATE ARRAY AND METHOD OF MANUFACTURE THEREOF," U.S. Ser. No. 07/642,617, filed January 17, 1991 by Monta R. Holzworth et al. and assigned to the present assignee. This high-performance antifuse has many desirable operating characteristics. The antifuse has typically a high unprogrammed resistance of 1 x 109Ω, a low programmed resistance (R0N) of 100 ohms, a low programming voltage of 8-10 volts, and a short programming time of typically 100 microseconds. The antifuse can be programmed quickly and at a low voltage, compared to previous antifuses, which avoids additional process complexity. This allows the antifuse to be manufactured with or adapted to most standard processes, including those in CMOS, BiCMOS, NMOS and bipolar technologies. However, the antifuse has some shortcomings . including step coverage of the antifuse structure and possible sources of weaknesses in electrical performance. The present invention avoids some of these problems which may arise with this high-performance antifuse. The present invention provides for an antifuse which has very good step coverage and improved electrical performance in terms of consistency and reliability. As in the case of the previously mentioned high-performance antifuse, the antifuse of the present invention is built between two vertically separated metal interconnection lines and can be adapted for construction between any two vertically separated metal interconnection lines in the semiconductor process.
SUMMARY OF THE INVENTION The present invention provides for an improved interconnection line and antifuse structure on a semiconductor substrate. The structure has a first insulating layer on the substrate, a first metal interconnection line on the first insulating layer. An antifuse stack is formed on a portion of the first interconnection line. The antifuse stack is formed by an amorphous silicon layer and a first barrier layer on the amorphous silicon layer. The amorphous silicon layer rests on a second barrier layer which may be coextensive with the first interconnection line or with the antifuse stack.
A second insulating layer covers the first interconnection line and the antifuse stack. A via in the second insulating layer exposes a portion of the first barrier layer. A second metal interconnection line lies on the second insulating layer and contacts the portion of the first barrier layer through the via. In this manner an antifuse with a substantially flat amorphous silicon layer is formed between the first and second metal interconnectio lines.
A self-aligned, compact structure may also be formed with the layers of the antifuse stack extend coextensively with the sides of the first metal interconnection line.
The present invention also provides for a method of manufacturing interconnection line and antifuse structures. A first insulating layer is formed on the substrate. A first metal is deposited on the insulating layer. This is followed by the deposition of an amorphous silicon layer, and then by the deposition of a first barrier layer on the amorphous silicon layer. The first metal layer is defined to form a first interconnection line. The amorphous silicon layer and the first barrier layer are then defined to form an antifuse stack over a portion of the first interconnection line. A second barrier layer deposited prior to the deposition of the amorphous silicon layer may be defined by the first interconnection line defining step or it may be defined by the antifuse stack defining step.
A second insulating layer is formed over the first interconnection line and the antifuse stack. A via is defined in the second insulating layer to expose at least a portion of the first barrier layer of the stack. An second metal layer is then deposited over the second insulating layer for an electrical contact to the portion of the first barrier layer through the via and the second metal layer is defined to form a second interconnection line. An antifuse with a substantially flat amorphous silicon layer is formed between the first and second interconnection lines.
If the amorphous silicon layer and first barrier layer are defined with the first metal interconnection line defining step, then the antifuse stack is compactly self- aligned with the sides of the first metal interconnection line. BRIEF DESCRIPTION OF THE DRAWINGS
A detailed understanding of the present invention may be attained by a perusal of the following Description of the Preferred Embodiments with reference to the drawings below:
Fig. IA illustrates the initial top view in the process for manufacturing one embodiment of the present invention; Fig. IB illustrates a corresponding cross- sectional side view.
Fig. 2A shows a cross-sectional side view of the first interconnection line covered by amorphous silicon and barrier metal layers; Fig. 2B shows a top view after an antifuse stack structure has been defined on the first interconnection line; Fig. 2C shows a corresponding cross- sectional side view;
Fig. 3A shows a top view of a location of a via to the top of the antifuse stack; Fig. 3B shows a corresponding side view;
Fig. 4A shows a cross-sectional side view of the completed antifuse structure; Fig. 4B shows a corresponding top view of the completed structure;
Fig. 5A illustrates a top view of a defined first interconnection line in a process according to a second embodiment of the present invention; Fig. 5B illustrates a corresponding cross-sectional side view;
Fig. 6 illustrates a top view of a mask used to define an antifuse stack structure on the first interconnection line;
Fig. 7A shows a top view of the antifuse stack structure; Fig. 7B shows a corresponding cross-sectional side view;
Fig. 8A shows a top view of the second interconnection layer and the completed antifuse structure; and Fig. 8B illustrates a corresponding cross-sectional side view. DETAILED DESCRIPTION OF PREFERRED EMBODIMENT(S)
Figs. LA-b, 2A-C, 3A-B and 4A-B show the steps in manufacturing an antifuse structure between two metal interconnection lines according to the present invention. The manufacturing steps discussed herein are directed to only part of a complete process for manufacturing an integrated circuit in which antifuse are to be formed. Thus, many of the steps which are used to manufacture the complete integrated circuit, such as the formation of doped regions, or active regions, of the integrated circuit in th semiconductor substrate near the beginning of the process o the glass passivation layer depositions near the end of a process, for example, are not discussed. One familiar with integrated circuit processing technologies can easily recognize where the described manufacturing steps fit into complete process.
In U.S. Ser. No. 07/642,617 noted above, a layer of semiconductor material, specifically amorphous silicon, is deposited into a via in an insulating silicon dioxide layer between two conducting lines to form an antifuse at that location. Left unprogrammed, the amorphous silicon layer electrically isolates the two conducting lines. When subjected to a predetermined voltage between the two conducting lines, the amorphous silicon layer undergoes a transformation and the two lines are electrically connected The antifuse is programmed.
The thickness and the contours of the amorphous silicon layer are known to affect the programming of the antifuse. For example, the thicker the amorphous silicon layer the larger the voltage required to program the antifuse. For the antifuse of the previously filed patent application, the amorphous silicon layer is deposited into vias in the intervening silicon dioxide layer which insulates the two interconnection lines from each other. I the amorphous silicon layer is folded, as in this case, the edge effects complicate the electrical performance of the antifuse. Furthermore, the inherent height variation of the vias formed in the intervening silicon dioxide layer adversely affects the thickness uniformity of the amorphous silicon layer at the bottom of the vias. The electrical performance, e.g., the programming voltages, of the resulting antifuses, therefore, have large variations. This is undesirable.
In the present invention, the amorphous silicon is deposited in a substantially level layer. This level layer avoids irregular contours and sharp edges which cause problematical electrical performances.
At the starting point of a process according to the present invention, an insulating layer is deposited over a semiconductor substrate and areas with polysilicon layers. (In present CMOS process technology these polysilicon areas include the gate areas of the MOS transistors.) Typically, this insulating layer (having reference numeral 19 in Fig. IA and following drawings) is a doped or undoped silicon oxide, or other insulating material, which is deposited on the substrate having active, field oxide and deposited polysilicon areas.
A first metal interconnection line 20 is then formed on the insulating layer 19 which covers the semiconductor substrate 10. A first barrier layer 11 is optionally deposited over the layer 19, followed by an aluminum alloy layer 12, which is followed in turn by a second barrier layer 13. In some embodiments all three layers 11, 12 and 13 may be replaced by a single refractory metal layer. The term, "refractory metal," as used here is meant to encompass refractory metals, their intermetallics, alloys, suicides, nitrides and combinations thereof. For example, the single refractory metal layer may be formed from tungsten, titanium-tungsten alloy (TiW) , titanium suicide (TiSi) , titanium nitride (TiN) and so forth. The first metal interconnection line 20 is define by a masking and etching process. A top view of the substrate 10 covered by the insulating layer 19 on which th first interconnection line 20 is formed is shown in Fig. IA. A location where an antifuse is to be formed on the first interconnection line 20 is marked by an enlarged portion 21 of the interconnection line 20. Of course, if the interconnection line 20 is sufficiently wide to accommodate alignment tolerances of the antifuse structure to follow, then an enlarged portion 21 is not required.
A cross-sectional view of the line 20 is shown in Fig. IB. The optional first barrier layer 11 is used to prevent the aluminum layer 13 from spiking into the silicon of the substrate 10 where the first interconnection line 20 contacts various active regions in the substrate 10. If spiking is not a problem, the first barrier layer 11 may be omitted. The second barrier layer 13 acts as a diffusion barrier between the aluminum layer 12 and a layer 14 of amorphous silicon described below.
The layer 14 of amorphous silicon is then deposited over the top of the first interconnection line 20 and top surface of the insulating layer 19. Plasma-enhanced chemical vapor deposition (PECVD) is used to deposit the amorphous silicon at temperatures below 450 degrees C, which helps ensure the integrity and reliability of the aluminum layer 12. The amorphous silicon layer 14 is deposited in thicknesses ranging from 500 to 1500 Angstroms, with 800 Angstroms being the optimum thickness. Sputter deposition may also be used to deposit the amorphous silicon at such comparatively low temperatures.
The hydrogen content of the amorphous silicon layer 14 should also be kept in the range of 5-20% by composition so that the layer 14 has the optimum characteristics suitable for an antifuse. In a PECVD process, which uses silane and argon, this is achieved by increasing the flow of the inert gas, argon, over its nominal flow rate in the process or adjusting the temperature of deposition.
The amorphous silicon layer 14 is then covered by a third barrier layer 15 as shown in Fig. 2A. Then an antifuse mask is used to define the antifuse at predetermined locations on the first conducting line. With a sequence of etchants, the second and third barrier layers 13 and 15 and the amorphous silicon layer 14 are removed completely except over the enlarged portions 21 where the antifuses are to be located over the first interconnection line 20. Fig. 2B shows the alignment of the antifuse stack 23 formed by the remaining portions of the layers 13, 14 and 15 with respect to the enlarged portion 21. The cross- sectional result illustrated in Fig. 1C shows the antifuse stack 23 on the first interconnection line 20.
Alternatively, the etching sequence above may be stopped after the amorphous silicon layer 14 is etched. In this case the second barrier layer 13 is the top layer of the first interconnection line 20.
Then a second insulating layer 16 of silicon dioxide is deposited on the first insulating layer 19 to cover the first interconnection line 20 and the antifuse stack 23. Typically, the insulating layer 16 is formed from doped or undoped silicon dioxide, or silicate or siloxane films or combinations of these materials, to a thickness in the range from 5000 A to 15000 A. The insulating layer 16 is planarized to make the top surface of the layer 16 as flat as possible.
By a masking and etching step, a via 27 is created in the insulating layer 16 over each antifuse structure 23. Fig. 3A illustrates a top view of the via 27 over an antifuse stack 23 (the overlying insulating layer 16 is not shown) and Fig. 3B illustrates a cross-sectional side view. It should be noted that third barrier layer 15 acts as an etch stop to the etchant for the via 27 in the layer 16. Any etching of the amorphous silicon layer 14 typically adversely affects the performance of the resulting antifuse. The barrier layer 15 protects the amorphous silicon layer 14 from the etchant to maintain the integrity of the layer 14.
This is followed by a layer 18 of aluminum alloy with a thickness in the range from 6000 to 12000 A. By a masking and etching process, the layer 18 is etched to define a second metal interconnection line 22. Optionally, a fourth barrier metal layer 17 may be used in the process. This optional barrier metal layer 17 is deposited immediately prior to the deposition of the aluminum alloy layer 18 and etched with the layer 18. This layer 17 is typically used to improve the resistance against electromigration.
In the process described above, a refractory metal may be used for the barrier layers 13 and 15, and optional barrier layers 11 and 17. Here too, the term, "refractory metal," is used to encompass refractory metals, their intermetallics, alloys, silicides, nitrides and combinations thereof. In the present embodiment described, a titanium- tungsten alloy works very well for all the barrier layers 11, 13, 15, and 17. Thicknesses range from 500 to 1500 A.
Figs. 4A and 4B shows the completed structure of an antifuse between two interconnection lines 20 and 22. The antifuse stack 23 lies between the first interconnection line 20, formed by the barrier layer 11 and the aluminum layer 12, and the second interconnection line 22, formed by the fourth barrier layer 17 and the second aluminum alloy layer 18.
Fig. 4B also illustrates the amount of substrate area, delineated by the enlarged portion 21 of the first interconnection line 20, occupied by the antifuse. This antifuse area is set by the area of the via 27, which by standard engineering practice is the minimum area required to make a proper contact between the two interconnection lines 20 and 25. Given the area occupied by the via 27, the area occupied by the antifuse stack 23 must be larger by at least a predetermined amount to account for alignment tolerances between the mask for the via 27 and the antifuse mask, which defines the stack 23. If the via 27 falls off the edge of the antifuse stack 23, then the resulting antifuse will be short-circuited.
With the area of the stack 23 a certain size, the area where the stack 23 (and antifuse) is to be placed on the first interconnection line 20 is correspondingly larger by a predetermined amount to account for alignment tolerances between the placement of antifuse mask and the mask for the first interconnection line 20. In the process described above, the first interconnection line 20 is enlarged into the portion 21. If enlarged sufficiently, the portion 21 prevents the antifuse stack 23, i.e.., portions of the second barrier layer 13, amorphous silicon layer 14 and third barrier layer 15, from hanging over the side of the interconnection layer 20. This adversely affects the electrical characteristics of the antifuse, even to the point of inoperability.
An alternative embodiment of the present invention which occupies less area is presented in Figs. 5A-B, 6, 7A- B, and 8A-B. In these drawings the same reference numerals as used for the same elements in the previous drawings.
In this embodiment the first interconnection layer 20 is defined after the deposition of the first barrier layer 11, aluminum alloy layer 12, second barrier layer 13, amorphous layer 14 and the third barrier layer 15. Then the first interconnection line 20 is defined by masking and etching steps. Fig. 5A shows a top view of the covered substrate 10 at this stage; Fig. 5B shows a cross-sectional side view. Then with an antifuse mask denoted by a dotted line 24 in Fig. 6, the locations where antifuses are to be located on the interconnection line 20 are covered by the remaining portions of a photoresist layer after a photoresist exposure and development step. Then by sequential etching operations, the exposed portions of the third barrier layer 15, the amorphous silicon layer 14 and the second barrier layer 13 on the interconnection line 20 are removed. Only the portions of the third barrier layer 15, the amorphous silicon layer 14 and the second barrier layer 13 protected by the photoresist remain. It should be noted that from the dotted line 24 that the photoresist extends over the sides of the interconnection line 20 to protect the barrier layer 13 and 15, and especially the amorphous silicon layer 14, from undesirable side etching. The antifuse mask defined by the dotted line 24 extends from either side of the interconnection line 20 to compensate for alignment tolerances.
Alternatively the second barrier layer 13 may left on to form the top layer of the first interconnecting layer 20, as in the previous embodiment.
The photoresist layer is then removed. The results are shown in Fig. 7A in a top view and Fig. 7B in a side view. Since the sides of the third barrier layer 15, the amorphous silicon layer 14 and the second barrier layer 13 had been formed with the first interconnection layer 20, the sides of the antifuse stack is self-aligned with the layer 20.
As described previously, the second insulating layer 16 can then be deposited and planarized. The via 27 is made in the layer 16 and the aluminum layer 18 and optional fourth barrier layer 17 are deposited and defined as the second interconnection layer 22. Fig. 8A is a top view, and Fig. 8B a side view, of the intersection of the first and second interconnection layer 20 and 22 with the antifuse between.
It should be noted that in the antifuses according to the embodiments ofthe present invention, the amorphous silicon layer 14, the barrier layer 13 and 15 are substantially flat. This permits better process control over the programming voltages of the antifuse with more consistent and reliable performance.
While the above is a complete description of the preferred embodiments of the invention, various alternatives, modifications and equivalents may be used. It should be evident that the present invention is equally applicable by making appropriate modifications to the embodiments described above. Therefore, the above description should not be taken as limiting the scope of the invention which is defined by the appended claims.

Claims

WHAT IS CLAIMED IS:
1. An improved interconnection line and antifuse structure on a semiconductor substrate, said structure comprising: a first insulating layer on said substrate; a first metal interconnection line on said first insulating layer; an antifuse stack on a portion of said first interconnection line, said antifuse stack having an amorphous silicon layer and a first barrier layer on said amorphous silicon layer; a second insulating layer covering said first interconnection line and said antifuse stack, said second insulating layer having a via exposing a portion of said first barrier layer; and a second metal interconnection line on said second insulating layer, said second interconnection line contacting said portion of said first barrier layer through said via; whereby an antifuse is formed between said first and second metal interconnection lines.
2. The structure as in claim 1 further comprising a second barrier layer immediately below said amorphous silicon layer.
3. The structure as in claim 2 wherein said second barrier layer is coextensive with said first interconnection line.
4. The structure as in claim 2 wherein said second barrier layer is coextensive with said amorphous silicon layer.
5. The structure as in claim 1 wherein said first barrier layer is relatively highly resistant to etchants of said second insulating layer whereby said amorphous silicon layer is protected during etching of said second insulating layer.
6. The structure as in claim 1 wherein said first barrier layer comprises a refractory metal.
7. The structure as in claim 6 wherein said first barrier layer comprises TiW.
8. The structure as in claim 6 wherein said first barrier layer comprises TiN.
9. The structure as in claim 1 wherein said first metal interconnection line comprises a refractory metal.
10. The structure as in claim 9 wherein said first metal interconnection line comprises tungsten.
11. The structure as in claim 2 wherein said second barrier layer comprises a refractory metal.
12. The structure as in claim 11 wherein said second barrier layer comprises TiW.
13. The structure as in claim 11 wherein said second barrier layer comprises TiN.
1 . The structure as in claim 1 wherein said portion of said first interconnection line on which said antifuse stack is located extends laterally beyond said first barrier layer and said amorphous silicon layer.
15. The structure as in claim 1 wherein said first barrier layer and said amorphous silicon layer are laterally coextensive with said portion of said first interconnection line where said antifuse stack is located.
16. An improved interconnection line and antifus structure on a semiconductor substrate, said structure comprising: a first insulating layer on said substrate; a first metal interconnection line on said first insulating layer; an antifuse stack on a portion of said first interconnection line, said antifuse stack having a first barrier layer on said first interconnection line, an amorphous silicon layer on said first barrier layer and a second barrier layer on said amorphous silicon layer; a second insulating layer covering said first interconnection line and said antifuse stack, said second insulating layer having a via exposing a portion of said second barrier layer; and a second metal interconnection line on said second insulating layer, said second interconnection line contacting said portion of said second barrier layer through said via; whereby an antifuse is formed between said first and second metal interconnection lines.
17. The structure as in claim 16 wherein said first metal interconnection line comprises a first aluminum layer and said first barrier layer is an effective diffusion barrier between said aluminum layer and said amorphous silicon layer.
18. The structure as in claim 16 wherein said second barrier layer is relatively highly resistant to etchants of said second insulating layer whereby said amorphous silicon layer is protected during etching of said second insulating layer.
19. The structure as in claim 16 wherein said second metal interconnection line comprises a second aluminum layer and said second barrier layer is an effective diffusion barrier between said aluminum layer and said amorphous silicon layer.
20. The structure as in claim 16 wherein at least one of said barrier layers comprises TiW.
21. The structure as in claim 20 wherein all of said barrier layers comprise TiW.
22. The structure as in claim 16 wherein at least one of said barrier layers comprises TiN.
23. The structure as in claim 22 wherein all of said barrier layers comprise TiN.
24. The structure as in claim 16 wherein said portion of said first interconnection line on which said antifuse stack is located extends laterally beyond said second barrier layer and said amorphous silicon layer.
25. The structure as in claim 16 wherein said second barrier layer and said amorphous silicon layer are laterally coextensive with said portion of said first interconnection line where said antifuse stack is located.
26. A method of manufacturing an interconnection line and antifuse structure, said method comprising forming a first insulating layer on said substrate; depositing a first metal layer on said first insulating layer; depositing an amorphous silicon layer over said first metal layer; depositing a first barrier layer on said amorphous silicon layer; defining said first metal layer to form a first interconnection line; defining said amorphous silicon layer and said first barrier layer to form an antifuse stack over a portion of said first interconnection line; forming a second insulating layer over said first interconnection line and said antifuse stack; defining a via in said second insulating layer to expose at least a portion of said first barrier layer; depositing an aluminum layer over said second insulating layer for an electrical contact to said portion of said first barrier layer through said via; and defining said aluminum layer to form a second interconnection line; whereby an antifuse is formed between said first and second interconnection lines.
27. The method as in claim 26 further comprising depositing a second barrier layer before depositing said amorphous silicon layer.
28. The method as in claim 27 wherein said first interconnection line defining step includes defining said second barrier layer.
29. The method as in claim 27 wherein said antifuse defining step includes defining said second barrier layer.
30. The method as in claim 26 wherein said via defining step includes etching said via in said second insulating layer and said first barrier layer depositing step includes selecting a material highly resistant to etchants in said via etching step.
31. The method as in claim 26 wherein said first barrier layer depositing step includes selecting a refractory metal for said first barrier layer.
32. The method as in claim 31 wherein said selecting step includes selecting TiW for said first barrier layer.
33. The method as in claim 31 wherein said selecting step includes selecting TiN for said first barrier layer.
34. The method as in claim 26 wherein said first metal layer depositing step includes selecting a refractory metal for said first interconnection line.
35. The method as in claim 34 wherein said refractory metal selecting step includes selecting tungsten.
36. The method as in claim 27 wherein said second barrier layer depositing step includes selecting a refractory metal for said second barrier layer.
37. The method as in claim 36 wherein said refractory metal selecting step includes selecting TiW for said second barrier layer.
38. The method as in claim 36 wherein said refractory metal selecting step includes selecting TiN for said second barrier layer.
39. The method as in claim 26 wherein said first interconnection line defining step is performed before said depositing steps of said first barrier layer and said amorphous silicon layer.
40. The structure as in claim 26 wherein said interconnection line defining step is performed after said depositing steps of said first barrier layer and said amorphous silicon layer.
41. A method of manufacturing an interconnection line and antifuse structure, said method comprising forming a first insulating layer on said substrate; depositing a first metal layer over said first insulating layer; depositing a first barrier layer on said first insulating layer and said first metal layer; depositing an amorphous silicon layer on said first barrier layer; depositing a second barrier layer on said amorphous silicon layer; defining said first metal layer to form a first interconnection line; defining said first barrier layer, said amorphous silicon layer and said second barrier layer to form an antifuse stack over a portion of said first interconnection line; forming a second insulating layer over said first interconnection line and said antifuse stack; defining a via in said second insulating layer to expose at least a portion of said second barrier layer; depositing a second metal layer over said second insulating layer for an electrical contact to said portion of said second barrier layer through said via; and defining said second metal layer to form a second interconnection line; whereby an antifuse is formed between said first and second interconnection lines.
42. The method as in claim 41 wherein said first metal depositing step includes selecting aluminum as said first metal layer and said second barrier layer depositing step includes selecting a material for an effective diffusion barrier between amorphous silicon and aluminum.
•43. The method as in claim 41 wherein said second barrier layer depositing step includes selecting a material which protects said amorphous silicon layer during said via defining step.
44. The method as in claim 41 wherein said second metal depositing step includes selecting aluminum as said second metal layer and said second barrier layer depositing step includes selecting a material for an effective diffusion barrier between amorphous silicon and aluminum.
45. The method as in claim 41 further comprising selecting at least one of said barrier layers to comprise TiW.
46. The method as in claim 45 further comprising selecting all of said barrier layers to comprise TiW.
47. The method as in claim 41 further comprising selecting at least one of said barrier layers to comprise TiN.
48. The method as in claim 47 further comprising selecting all of said barrier layers to comprise TiN.
49. The method as in claim 41 wherein said first interconnection line defining step is performed before said depositing steps of said second barrier layer and said amorphous silicon layer.
50. The method as in claim 41 wherein said interconnection line defining step is performed after said depositing steps of said second barrier layer and said amorphous silicon layer.
PCT/US1992/006913 1991-08-19 1992-08-17 An improved antifuse and method of manufacture thereof WO1993004499A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US74729891A 1991-08-19 1991-08-19
US747,298 1991-08-19

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WO1993004499A1 true WO1993004499A1 (en) 1993-03-04

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PCT/US1992/006913 WO1993004499A1 (en) 1991-08-19 1992-08-17 An improved antifuse and method of manufacture thereof

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Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0661745A1 (en) * 1993-12-21 1995-07-05 Actel Corporation Metal-to-metal antifuse including etch stop layer
US5519248A (en) * 1993-07-07 1996-05-21 Actel Corporation Circuits for ESD protection of metal-to-metal antifuses during processing
US5576576A (en) * 1992-11-04 1996-11-19 Actel Corporation Above via metal-to-metal antifuse
US5592016A (en) * 1995-04-14 1997-01-07 Actel Corporation Antifuse with improved antifuse material
WO1997015068A2 (en) * 1995-10-04 1997-04-24 Actel Corporation Improved metal-to-metal via-type antifuse and methods of programming
US5670818A (en) * 1990-04-12 1997-09-23 Actel Corporation Electrically programmable antifuse
US5672905A (en) * 1992-08-26 1997-09-30 At&T Global Information Solutions Company Semiconductor fuse and method
EP0823733A2 (en) * 1996-08-08 1998-02-11 Matsushita Electronics Corporation Antifuse element and method for manufacturing the same
US5753528A (en) * 1992-02-26 1998-05-19 Actel Corporation Method of fabricating metal-to-metal antifuse with improved diffusion barrier layer
US5763299A (en) * 1995-06-06 1998-06-09 Actel Corporation Reduced leakage antifuse fabrication method
US5770885A (en) * 1990-04-12 1998-06-23 Actel Corporation Electrically programmable antifuse incorporating dielectric and amorphous silicon interlayers
US5789795A (en) * 1995-12-28 1998-08-04 Vlsi Technology, Inc. Methods and apparatus for fabricationg anti-fuse devices
US5793094A (en) * 1995-12-28 1998-08-11 Vlsi Technology, Inc. Methods for fabricating anti-fuse structures
US5804500A (en) * 1995-06-02 1998-09-08 Actel Corporation Fabrication process for raised tungsten plug antifuse
US5856234A (en) * 1993-09-14 1999-01-05 Actel Corporation Method of fabricating an antifuse
US5899707A (en) * 1996-08-20 1999-05-04 Vlsi Technology, Inc. Method for making doped antifuse structures
US5913137A (en) * 1993-07-07 1999-06-15 Actel Corporation Process ESD protection devices for use with antifuses
US5963825A (en) * 1992-08-26 1999-10-05 Hyundai Electronics America Method of fabrication of semiconductor fuse with polysilicon plate

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US5070384A (en) * 1990-04-12 1991-12-03 Actel Corporation Electrically programmable antifuse element incorporating a dielectric and amorphous silicon interlayer
US5100827A (en) * 1991-02-27 1992-03-31 At&T Bell Laboratories Buried antifuse

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US5100827A (en) * 1991-02-27 1992-03-31 At&T Bell Laboratories Buried antifuse

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Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5770885A (en) * 1990-04-12 1998-06-23 Actel Corporation Electrically programmable antifuse incorporating dielectric and amorphous silicon interlayers
US5670818A (en) * 1990-04-12 1997-09-23 Actel Corporation Electrically programmable antifuse
US5753528A (en) * 1992-02-26 1998-05-19 Actel Corporation Method of fabricating metal-to-metal antifuse with improved diffusion barrier layer
US5963825A (en) * 1992-08-26 1999-10-05 Hyundai Electronics America Method of fabrication of semiconductor fuse with polysilicon plate
US5672905A (en) * 1992-08-26 1997-09-30 At&T Global Information Solutions Company Semiconductor fuse and method
US5576576A (en) * 1992-11-04 1996-11-19 Actel Corporation Above via metal-to-metal antifuse
US5913137A (en) * 1993-07-07 1999-06-15 Actel Corporation Process ESD protection devices for use with antifuses
US5519248A (en) * 1993-07-07 1996-05-21 Actel Corporation Circuits for ESD protection of metal-to-metal antifuses during processing
US5856234A (en) * 1993-09-14 1999-01-05 Actel Corporation Method of fabricating an antifuse
EP0661745A1 (en) * 1993-12-21 1995-07-05 Actel Corporation Metal-to-metal antifuse including etch stop layer
US5592016A (en) * 1995-04-14 1997-01-07 Actel Corporation Antifuse with improved antifuse material
US5804500A (en) * 1995-06-02 1998-09-08 Actel Corporation Fabrication process for raised tungsten plug antifuse
US5763299A (en) * 1995-06-06 1998-06-09 Actel Corporation Reduced leakage antifuse fabrication method
WO1997015068A3 (en) * 1995-10-04 1997-06-19 Actel Corp Improved metal-to-metal via-type antifuse and methods of programming
US5741720A (en) * 1995-10-04 1998-04-21 Actel Corporation Method of programming an improved metal-to-metal via-type antifuse
WO1997015068A2 (en) * 1995-10-04 1997-04-24 Actel Corporation Improved metal-to-metal via-type antifuse and methods of programming
US5789795A (en) * 1995-12-28 1998-08-04 Vlsi Technology, Inc. Methods and apparatus for fabricationg anti-fuse devices
US5793094A (en) * 1995-12-28 1998-08-11 Vlsi Technology, Inc. Methods for fabricating anti-fuse structures
EP0823733A3 (en) * 1996-08-08 1998-07-15 Matsushita Electronics Corporation Antifuse element and method for manufacturing the same
US5913138A (en) * 1996-08-08 1999-06-15 Matsushita Electronics Corporation Method of manufacturing an antifuse element having a controlled thickness
EP0823733A2 (en) * 1996-08-08 1998-02-11 Matsushita Electronics Corporation Antifuse element and method for manufacturing the same
US5899707A (en) * 1996-08-20 1999-05-04 Vlsi Technology, Inc. Method for making doped antifuse structures

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