WO1993026039A1 - Using a nanochannel glass mask to form semiconductor devices - Google Patents

Using a nanochannel glass mask to form semiconductor devices Download PDF

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Publication number
WO1993026039A1
WO1993026039A1 PCT/US1993/004563 US9304563W WO9326039A1 WO 1993026039 A1 WO1993026039 A1 WO 1993026039A1 US 9304563 W US9304563 W US 9304563W WO 9326039 A1 WO9326039 A1 WO 9326039A1
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WO
WIPO (PCT)
Prior art keywords
mask
glass
substrate
semiconductor material
acid
Prior art date
Application number
PCT/US1993/004563
Other languages
French (fr)
Inventor
Ronald J. Tonucci
Brian L. Justus
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The Government Of The United States Of America, As Represented By The Secretary Of The Navy
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Publication of WO1993026039A1 publication Critical patent/WO1993026039A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2654—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/20—Masks or mask blanks for imaging by charged particle beam [CPB] radiation, e.g. by electron beam; Preparation thereof
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/12—Production of screen printing forms or similar printing forms, e.g. stencils
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02395—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/122—Single quantum well structures
    • H01L29/127—Quantum box structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66469—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with one- or zero-dimensional channel, e.g. quantum wire field-effect transistors, in-plane gate transistors [IPG], single electron transistors [SET], Coulomb blockade transistors, striped channel transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/944—Shadow
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/962—Quantum dots and lines

Definitions

  • the present invention relates to semiconductor lithography .
  • Electron and ion beam direct writing on energy sensitive surfaces have been developed to produce a mask capable of defining structures as small as 10 ran.
  • the beams are tightly focused which requires a large acceleration of the charged particles composing the beam.
  • the interaction of the particles with the substrate usually causes damage to the substrate, which in most cases is detrimental to small device fabrication.
  • scattering of the particles in the substrate back into the lithographic material usually reduces the sharpness and contrast of the mask, lowering the mask resolution.
  • Photoresistive material Another type of lithographic mask involves photoresistive material. Photons pass through the transparent portions of an otherwise opaque mask and reproduce the pattern on photoresistive material, forming a resist mask. Resolution of the pattern on the resist is ultimately limited by the wavelength of the photons used to form it (i.e. minimum resolution > wavelength/2) . A pattern with structures 10 n in width and a 50% variation in definition would require photons with wavelength less than 10 nm, a demanding region of the spectrum in which to work.
  • RIE reactive ion etching
  • a third type of mask is one where deposition of desired material is physically blocked or passed in regions by prefabricated mask laid down on the substrate. To date the smallest structures within these masks are on the order of 10's of microns in size.
  • Devices that utilize tunneling of electrons or elementary excitations such as excitons are very sensitive to barrier heights and widths.
  • Arrays of devices that require identical barriers i.e. identical device characteristics
  • Variations of less than 10 percent in size or position of the quantum confined array element are sufficient to wash out the optical signature of both cooperative effects and energy shifts due to confinement.
  • Recent attempts at defining quantum confined arrays of wires or dots have relied on a variety of masking, etching and growth techniques. Due to the small size requirements for quantum confinement (often ⁇ 50 nm) , these processes usually contaminate the quantum material by damage or extraneous material deposition, which is generally detrimental to device performance.
  • the present invention provides a method for depositing a pattern of deposited material on or within a substrate, comprising the steps of: interposing a glass mask between a source and a substrate with or without a resist, the mask having empty channels therethrough which are arranged in a pattern and which have an average diameter of less than 1 micron; and depositing a material selected from the group of sources consisting of ions, electrons, photons, metals and semiconductor materials through the glass mask into or onto the substrate with or without a resist.
  • the present invention provides a method for forming a semiconductor device, comprising the steps of: growing a first layer of first semiconductor material over a second semiconductor material substrate to form a base; interposing a glass mask between the base and a source of the first semiconductor material; depositing additional first semiconductor material through the glass mask and onto the base to form an array of pedestals; removing the mask; depositing a second layer of the second semiconductor material to form a cap on top of each pedestal and to form a connected layer of the second semiconductor material completely covering the base; and depositing a layer of the first semiconductor material over the second layer of the second semiconductor material to form an array of quantum dots suspended over a quantum well structure having holes therein.
  • the present invention provides a method for forming a semiconductor device comprising the steps of: interposing a glass mask between a semiconductor material substrate and a source of molten metal dopant, the mask having channels therethrough which are arranged in a pattern and which have an average diameter of less than 1 micron; depositing the metal dopant through the mask and onto the substrate of semiconductor material ; removing the mask; ion implanting additional metal dopant into the substrate; removing metal dopant on the surface of the substrate; and annealing the doped substrate to .form a semiconductor device.
  • the present invention provides a method of forming a semiconductor device comprising the steps of: forming a glass block of an acid inert glass having acid etchable glass rods extending therethrough, the acid etchable glass rods having a diameter of less than 1 micron, the acid inert glass having a lower melting point than the acid etchable glass; partially etching the acid etchable rods so that an exposed surface of the acid inert glass block extends above the ends of the acid etchable rods; bonding the exposed ends of the acid etchable rods to a substrate; etching away the acid etchable rods from the acid inert glass to form a mask on the substrate; and depositing a coating selected from the group consisting of metals and semiconductor materials through the mask onto the substrate to form a semiconductor device or ion implantation mask.
  • the present invention also provides semiconductor devices made by the above methods.
  • Figure 1 illustrates the reduction in size of an acid etchable rod inside a hollow inert glass rod.
  • Figure 2 illustrates stacked rods which have been redrawn several times.
  • Figure 3 is a right perspective view of a mask of the invention.
  • Figure 4(a) is a scanning electron micrograph of a mask made according to the present invention having 450 nanometer channel diameters.
  • Figure 4(b) is a scanning electron micrograph of a mask of the present invention having 90 nanometer channel diameters.
  • Figure 4(c) is a scanning electron micrograph of a mask of the present invention having 40 nanometer channel diameters.
  • Figure 5(a) is a top view of a nanochannel mask of solid homogeneous hexagonal rods of either acid-etchable or inert glass demonstrating a square array.
  • Figure 5(b) is a top view of a nanochannel mask composed of solid homogeneous hexagonal rods of either acid- etchable or inert glass demonstrating a hexagonal array.
  • Figure 6(a) is a top plan view of a nanochannel mask composed of solid homogeneous hexagonal rods of either etchable or inert glass . demonstrating connecting structures.
  • Figure 6(b) is an alternate embodiment showing the use of solid rods of inert acid-etchable glasses in a split D configuration.
  • Figure 6(c) is an alternate embodiment showing the use of solid rods of inert acid-etchable glasses in a square configuration.
  • Figure 6(d) is an alternate embodiment showing the use if solid rods of different sizes wherein the rods are either inert or acid-etchable.
  • Figure 7 illustrates a method for fabricating a semiconductor device containing quantum dots.
  • Figure 8 is a schematic cross-section of a semiconductor device of the present invention containing a uniform array of quantum dots suspended in a lattice of matched AlGaAs deposited on a substrate of GaAs.
  • Figure 9 is a cross sectional view of a glass array of the present invention prior to etching.
  • Figure 10 is a cross sectional view of the array Figure 9 after being partially etched.
  • Figure 11 is a cross sectional view of the partially etched array of Figure 10 after being bonded to a substrate.
  • Figure 12 is a cross sectional view of the array of Figure 11 after glass shaded in Figure 11 has been etched away.
  • Figure 13 illustrates the traslation of a mask over a substrate allowing the massively parallel fabrication of complex nanometer scale circuits.
  • the nanochannel mask of the present invention is a patterned arrangement of sub-micron sized holes or channels in a glass matrix. It is used where the deposition of desired materials (ions, electrons, photons, etc.) is physically blocked or passed in regions by overlaying the mask on a chemically active or energy sensitive surface above the substrate, or on a substrate directly. A multitude of complex configurations are possible.
  • the fabrication process involves
  • the mask is formed as a uniform array of equally spaced rods of acid etchable glass in a hexagonal 2-dimensional close packing arrangement.
  • the hexagonal close packing arrangement of hexagonal glass fibers, with acid etchable channels of greater than 1 micron is a well known technology and is frequently used in the first processing step of microchannel plates.
  • fabrication starts by insertion of a cylindrical acid etchable glass rod 2, the channel glass, into an inert hexagonal glass tube 4, the matrix glass, whose inner dimensions match that of the rod.
  • the pair is then fused by heating the glasses close to the melting point.
  • the pair is then drawn to reduce the overall cross-section to that of a fine filament.
  • the filaments are then stacked, fused again and redrawn under vacuum as is shown in Figure 2. This process is continued until appropriate channel diameters and the desired number of array elements are achieved. Annealing of the glasses is necessary if the glasses chosen are susceptible to work hardening.
  • FIG. 3 shows a scanning electron micrograph (SEM) of a hexagonal close packing (HCP) arrangement of channel glasses in relief after acid etching.
  • SEM scanning electron micrograph
  • HCP hexagonal close packing
  • Figure 4(b) shows a similar SEM micrograph with 90 nanometer channel diameters.
  • the rough appearance of the channel boundaries and apparent cracking of the surface is due to the approximately 8 nanometer thick incomplete layer of gold deposited on the nanochannel mask surface to avoid charging effects during SEM analysis and is not indicative of the nanochannel mask itself.
  • Figure 4(c) shows a similar SEM micrograph with 40 nanometer channel diameters.
  • the fabrication process is very suitable to mass production requirements.
  • the wafer-like nanochannel mask is generally only a few millimeters thick and is sectioned from a fused matrix bar several feet long. The fused matrix bar is cut from a longer matrix bar which continuously flows from the final drawing process.
  • the mask Up to 100 feet of identical fused matrix bar can be fabricated in a single run, from which more than 50,000 identical nanochannel masks can be cut.
  • the mask In order to produce a mask which can withstand the acid etching treatment, after the wafer-like mask has been cut from the fused stack of fibers, the mask should be annealed at an elevated temperature, preferably about 425°C for about 2 hours in order to relieve stress in the matrix.
  • the packing arrangement or geometry of the array can be adjusted. Also, by adjusting the shape of the circumference of the channel glass, the channel shape can be altered. More intricate patterns can be fabricated by stacking dissimilar filaments next to each other.
  • the fabrication process for the nanochannel mask array of the present invention yields extremely regular channels whose diameters are adjustable in size from microns to several nanometers.
  • the difference between the relative etch rates of the etchable glass to the inert glass needs to be very large. While in porous glass having larger pore sizes, the etch rate of the etchable glass is 1,000 to 10,000 times the etch rate of the inert glass, in the present invention, the etch rate of the etchable glass is preferably 10 5 to 10 7 the etch rate of the inert glass. Because of the microscopic size of the channels formed in the mask, it is also important that the two glasses not diffuse into each other while they are drawn. Therefore, a minimum of heat and time should be used while the glasses are being drawn.
  • a preferred inert glass is corning glass 0120, 8161 or 0080.
  • Corning Glass 0120 is a potash soda lead glass.
  • Preferred etchable glasses are EG-1, EG-2 and EG-4 manufactured by Detector Technology. Using Corning Glass 0120 as the inert glass and EG-2 as the etchable glass, masks have been prepared having average channel diameters of less than 400 A, preferably less than 100 A.
  • the acid used in the acid etching of the etchable glass is preferably an organic acid such as acetic acid which does not leave a residue on the acid inert glass.
  • the acid etching solution is at a concentration of 0.1 to 2%.
  • an array is composed of solid homogeneous hexagonal rods of either etchable or inert glass. Examples of such masks are illustrated in Figures 5(a) and 5(b) .
  • the dark regions are composed of acid etchable pixels or rods 10 and the light- regions are composed of inert pixels or rods 12.
  • fabrication of nanochannel glass includes the step of extruding D-shaped rods with small grooves along the center of the flat face, as shown on Figure 6(b) .
  • the groove may be cut instead of being formed by the die used in the extrusion to make the D-shaped rod.
  • An acid-etchable glass fiber or rod drawn down to 100 microns in diameter or smaller is placed in the groove of the D-shaped rod and another D-shaped rod is attached.
  • the rods are stacked for drawing sequences as already described. Nanometer dimensions of the channel diameters can now be accomplished in just two additional draws, minimizing the interdiffusion of the glass types.
  • the matrix glass chosen for the D- shaped rod must have a lower working temperature than the etchable iber so the matrix can" flow and close the area around the fiber during the vacuum drawing process without fiber distortion.
  • a hexagonal rod is used since it has a closed packing geometry.
  • dark regions are composed of acid-etchable pixels or rods 10 and the light regions are composed of inert pixels or glass rods 12.
  • the fabrication method utilizes the radius of the corners of long glass bars with rectangular or square cross-sections.
  • Figure 6(c) illustrates the square embodiment with dark regions composed of acid-etchable pixels or rods 10 and light regions composed of inert pixels or glass rods 12. The edges can be ground for greater accuracy.
  • nanochannel glass is fabricated using solid bars 10 of acid-etchable glass in between much larger rods 12 of inert glass.
  • FIGS. 6(b) , 6(c) and 6(d) illustrate alternative glass fabrication methods using solid rods of different shapes and sizes. Examples of how the nanochannel mask can be used for quantum confined semiconductor device fabrication are described below.
  • a thin array nanochannel mask 26 is positioned over the AlGaAs base and additional AlGaAs (200-500 A thick) is laid down by MBE to form an array of pedestals 28.
  • Mask 26 is removed and a thin layer of GaAs (50-400 A thick) is laid down forming a GaAs cap on top of each pedestal and a connected GaAs layer completely covering the base.
  • a thick layer of AlGaAs is then deposited over the GaAs leaving an array of quantum dots 20 suspended over a quantum well structure 30 with holes punched into it.
  • the interaction of the quantum well 30 with the quantum dot array 20 can be varied by adjusting the pedestal height (potential tunnel diode devices) .
  • Another example of patterning a quantum dot array using the nanochannel mask for fabrication involves the deposition of a protective layer just over a quantum well structure.
  • a metal such as aluminum
  • a metal is deposited through the nanochannel mask onto the quantum well substrate. After some accumulation has occurred, the mask is removed.
  • Aluminum is implanted into the substrate by ion implantation entering only those regions of the well not covered by the prior aluminum accumulation. The aluminum pedestals protect the lattice matched surfaces underneath them. The surface aluminum is then removed and the AlGaAs system is annealed by standard techniques, forming AlGaAs in the regions of the well previously unprotected.
  • the dark regions of Figure 6(a) are composed of acid etchable rods 10 with an etchable rate R 1 and the light regions composed of rods 12 with etchable rate R 2 where R. > R 2 .
  • fabrication can be accomplished by bonding an array 40 onto a substrate 42 after a slight acid etch to the contact surface 44 of array 40. As shown in Figure 12, further acid etching removes remaining etchable glass 10. Materials such as aluminum can then be deposited on substrate 42 as described above for other deposition processes. After deposition, glass 12 is etched away and substrate 42 is heated to remove any residual oxide layers.
  • the nanochannel mask of the present invention can be configured for a variety of other lithographic techniques. If the dark shaded glass 10 of Figure 6 is composed of a glass identical to the unshaded glass 12, except that the dark shaded glass 10 is doped with a material with a high absorption or scattering cross-section for X-rays (such as lead) , then a thin section of the mask can be used to define patterns optically, via x-rays, on energy sensitive surfaces. No etching of the glass is required. An inverted or negative lithographic mask can be fabricated in a similar way by applying the dopant material to the unshaded rods.
  • Refinements include etching the dark pixels, leaving them as hollow tubes (unshaded glass doped) or filling the empty tubes with fully concentrated appropriate material to block the x-rays (unshaded glass not doped) .
  • Longer wavelength photons > ⁇ /2) can also be applied by an evanescent wave approach.
  • the nanochannel mask of the present invention can be used for large scale parallel fabrication of complex circuits by translating the mask over a substrate while deposition of a source through the mask is occuring.
  • Figure 13 shows the translation of the mask 130 relative to substrate 132.
  • Arrow 134 indicates translation or movement in the X plane whereas arrow 136 indicates mask translation in the Y plane.
  • Source 138 which can be in the form material or energy, passes through nanochannels 140 in mask 130 to expose resist 142, deposit material, or to effect another reaction on substrate 132.
  • L o w energy electrons or ions can also be used to define patterns on energy sensitive surfaces with the nanochannel mask.
  • Very thin masks with empty channels can be fabricated by the dual etching process (with etchable rates R 1 and R 2 ) described above and used in conjunction with collimated beams of low energy ions or electrons.
  • An electrically conductive glass can be chosen to pull away excess charge during processing. With broad spatial beam profiles, the entire pattern may be fabricated at once. The low energy mode of operation greatly reduces substrate damage and back scattering, greatly increasing pattern contrast and definition.
  • the nanochannel mask used in the method of the present invention combines the ease of simultaneous large scale (>10 7 elements) patterning of nanometer sized elements with the accuracy and precision of ion and electron beam direct writing, without the usual substrate damage associated with these techniques.
  • the high temperature stability of the nanochannel mask makes nanometer scale lithography viable in molecular beam epitaxy (MBE) type applications for the first time. Fabrication of a new class of materials and devices that rely on both the shift in energy due to quantum confinement and cooperative effects between quantum confined elements in large arrays can now be realized.
  • nanochannel masks include quantum enhanced laser materials of bulk proportions with adjustable output frequencies dependent upon the degree of confinement, ultra small (quantum) electronic devices, far infrared filters (derived from cooperative effects) and nonlinear optoelectronic devices to name a few.
  • the most unique properties of the nanochannel mask are: the high temperature stability of the glass, the very small size of the channels and the accuracy and precision to which these small channels can be arranged to form very large and complex mask structures.
  • Regular arrays can be fabricated with extremely good geometric uniformity and very low variance in channel dimensions. Channel packing densities can approach I0 2 / c ra and channel diameters can be made under 10 nanometers (100 A) with great precision.
  • the fabrication process allows complex formations to be repeated many times within the mask which is important in memory and logic circuits.
  • glass is a noncrystalline substance formed usually by the fusion of the constituent materials by melting
  • Masks for ion implantation should be about 1 to 20 microns.
  • Masks for particle deposition should be as thin as possible prefably on the order of a few tens of nanometers, especially on the order of a few nanometers.
  • Example I The inert glass used was a hexagonal tube of Corning Glass 0120 glass.
  • the etchable glass used was Detector Technology's
  • the glasses were fused under vacuum during the drawing process at a temperature of 625 to 750°C and were drawn down to fine filaments of 0.01 to 0.2 inches (0.03 to 0.5 cm) and cut to lengths of 1 to 3 feet (30 to 90 cm) .
  • the filaments were stacked into bundles, approximately 1.5 inches flat to
  • composition was annealed after each draw.
  • the glass was-then cut to the desired length, polished and etched in a weak acid such as 1% HCL, HNo 3 or acetic acid to remove the channel glass and leave behind the porous matrix glass and cladding.
  • a weak acid such as 1% HCL, HNo 3 or acetic acid to remove the channel glass and leave behind the porous matrix glass and cladding.
  • Example II Hexagonal monofilaments of Corning 0120 glass and Detector Technology's EG-2 were used as the inert glass and etchable glass filaments, respectively.
  • the monofilaments typically 0.01 to 0.1 inches (0.025 to 0.25 cm) in width were stacked in predetermined pattern which can be used to make arrays. After the monofilaments are stacked, the process is essentially the same as described in example I.
  • An advantage to using this technique is that one less draw is required in which the dissimilar filaments are in contact with each other at elevated temperatures, greatly reducing the diffusion of glasses into one another and yielding a stronger matrix as well as finer resolution, especially at glass dimensions around 10 nanometers.
  • Another advantage is that individual pixel replacement is possible with a variety of glass types making very complex structures possible.

Abstract

The present invention provides a method for depositing a pattern of deposited material on or within a substrate, comprising the steps of: interposing a glass mask (26, 130) between a source (138) and a substrate (24, 132), the mask having channels (140) therethrough which are arranged in a pattern and which have an average diameter of less than 1 micron; and depositing a material selected from the group of sources (138) consisting of ions, electrons, photons, metals and semiconductor materials through the glass mask into or onto the substrate. The present invention also provides semiconductor devices made by this method.

Description

USING A NANOCHANNEL GLASS MASK TO FORM SEMICONDUCTOR DEVICES
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The present invention relates to semiconductor lithography .
Prior art
Considerable effort over the past two decades has been expended to develop techniques to fabricate materials with ultrasmall dimensions, usually embedded in a protective or interactive matrix. The constraints on size are highly dependent upon the specific application, however the ultimate goal is to produce materials that can be engineered from macroscopic dimensions to atomic proportions in size. Attempts at small device fabrication of solid materials have taken two general approaches. The first utilizes a macroscopic deposition of materials followed by removal of excess material on a microscopic scale, and the second involves a variety of specialized growth techniques, such as molecular beam epitaxy and metallo-organic chemical vapor deposition (MOCVD) , where the "device" is incorporated into the structure during the growth process. Although great progress has been made, a host of problems still need to be resolved. There is no good way to manufacture highly uniform and symmetric arrays containing greater than 103 elements of quantum confined materials. Further, if the elements are quantum confined optical devices, they have the additional constraint that their performance is especially susceptible to material damage.
The semiconductor industry relies oτ a variety of lithographic mask types to define regions where deposition, or lack of deposition, of dissimilar materials will occur. Electron and ion beam direct writing on energy sensitive surfaces have been developed to produce a mask capable of defining structures as small as 10 ran. To obtain high resolution, the beams are tightly focused which requires a large acceleration of the charged particles composing the beam. After the particles pass through the lithographic medium defining a pattern, they pass into the substrate and stop, where they deposit their remaining kinetic energy. The interaction of the particles with the substrate usually causes damage to the substrate, which in most cases is detrimental to small device fabrication. In addition, scattering of the particles in the substrate back into the lithographic material usually reduces the sharpness and contrast of the mask, lowering the mask resolution.
Another type of lithographic mask involves photoresistive material. Photons pass through the transparent portions of an otherwise opaque mask and reproduce the pattern on photoresistive material, forming a resist mask. Resolution of the pattern on the resist is ultimately limited by the wavelength of the photons used to form it (i.e. minimum resolution > wavelength/2) . A pattern with structures 10 n in width and a 50% variation in definition would require photons with wavelength less than 10 nm, a demanding region of the spectrum in which to work.
Once the resist mask is fabricated , it is possible to add or remove materials defined by the mask. Addition of materials such as metals generally preserves the resolution of the mask. However, removal of substrate materials below the mask requires techniques such as reactive ion etching (RIE) , chemical etching, etc. These processes usually distort the image of the mask as the etching process continues deeper into the substrate. In addition, the interaction of the RIE particles with the substrate usually causes damage to the substrate, which in most cases is detrimental to small device fabrication.
A third type of mask is one where deposition of desired material is physically blocked or passed in regions by prefabricated mask laid down on the substrate. To date the smallest structures within these masks are on the order of 10's of microns in size.
Devices that utilize tunneling of electrons or elementary excitations such as excitons, are very sensitive to barrier heights and widths. Arrays of devices that require identical barriers (i.e. identical device characteristics) then become extremely sensitive to the overall composition of the array in the elements within the array. Variations of less than 10 percent in size or position of the quantum confined array element are sufficient to wash out the optical signature of both cooperative effects and energy shifts due to confinement. Recent attempts at defining quantum confined arrays of wires or dots have relied on a variety of masking, etching and growth techniques. Due to the small size requirements for quantum confinement (often < 50 nm) , these processes usually contaminate the quantum material by damage or extraneous material deposition, which is generally detrimental to device performance. Where material damage is intentionally invoked to define the structure of the device, component boundaries tend to be vague, compromising large scale geometries. Arrays fabricated by controlled growth techniques over substrates, tend to be extremely labor and time intensive, and exhibit good uniformity over a relatively small region of the array. Chemical etching of free standing arrays utilizing masking techniques tend to be fragile and curve definition is extremely process and material dependent.
Summary of the invention the present invention provides a method for depositing a pattern of deposited material on or within a substrate, comprising the steps of: interposing a glass mask between a source and a substrate with or without a resist, the mask having empty channels therethrough which are arranged in a pattern and which have an average diameter of less than 1 micron; and depositing a material selected from the group of sources consisting of ions, electrons, photons, metals and semiconductor materials through the glass mask into or onto the substrate with or without a resist.
In another embodiment the present invention provides a method for forming a semiconductor device, comprising the steps of: growing a first layer of first semiconductor material over a second semiconductor material substrate to form a base; interposing a glass mask between the base and a source of the first semiconductor material; depositing additional first semiconductor material through the glass mask and onto the base to form an array of pedestals; removing the mask; depositing a second layer of the second semiconductor material to form a cap on top of each pedestal and to form a connected layer of the second semiconductor material completely covering the base; and depositing a layer of the first semiconductor material over the second layer of the second semiconductor material to form an array of quantum dots suspended over a quantum well structure having holes therein.
In another embodiment the present invention provides a method for forming a semiconductor device comprising the steps of: interposing a glass mask between a semiconductor material substrate and a source of molten metal dopant, the mask having channels therethrough which are arranged in a pattern and which have an average diameter of less than 1 micron; depositing the metal dopant through the mask and onto the substrate of semiconductor material ; removing the mask; ion implanting additional metal dopant into the substrate; removing metal dopant on the surface of the substrate; and annealing the doped substrate to .form a semiconductor device. In another embodiment, the present invention provides a method of forming a semiconductor device comprising the steps of: forming a glass block of an acid inert glass having acid etchable glass rods extending therethrough, the acid etchable glass rods having a diameter of less than 1 micron, the acid inert glass having a lower melting point than the acid etchable glass; partially etching the acid etchable rods so that an exposed surface of the acid inert glass block extends above the ends of the acid etchable rods; bonding the exposed ends of the acid etchable rods to a substrate; etching away the acid etchable rods from the acid inert glass to form a mask on the substrate; and depositing a coating selected from the group consisting of metals and semiconductor materials through the mask onto the substrate to form a semiconductor device or ion implantation mask.
The present invention also provides semiconductor devices made by the above methods.
Brief description of drawings
Figure 1 illustrates the reduction in size of an acid etchable rod inside a hollow inert glass rod.
Figure 2 illustrates stacked rods which have been redrawn several times. Figure 3 is a right perspective view of a mask of the invention.
Figure 4(a) is a scanning electron micrograph of a mask made according to the present invention having 450 nanometer channel diameters. Figure 4(b) is a scanning electron micrograph of a mask of the present invention having 90 nanometer channel diameters.
Figure 4(c) is a scanning electron micrograph of a mask of the present invention having 40 nanometer channel diameters.
Figure 5(a) is a top view of a nanochannel mask of solid homogeneous hexagonal rods of either acid-etchable or inert glass demonstrating a square array.
Figure 5(b) is a top view of a nanochannel mask composed of solid homogeneous hexagonal rods of either acid- etchable or inert glass demonstrating a hexagonal array. Figure 6(a) is a top plan view of a nanochannel mask composed of solid homogeneous hexagonal rods of either etchable or inert glass. demonstrating connecting structures.
Figure 6(b) is an alternate embodiment showing the use of solid rods of inert acid-etchable glasses in a split D configuration.
Figure 6(c) is an alternate embodiment showing the use of solid rods of inert acid-etchable glasses in a square configuration.
Figure 6(d) is an alternate embodiment showing the use if solid rods of different sizes wherein the rods are either inert or acid-etchable.
Figure 7 illustrates a method for fabricating a semiconductor device containing quantum dots.
Figure 8 is a schematic cross-section of a semiconductor device of the present invention containing a uniform array of quantum dots suspended in a lattice of matched AlGaAs deposited on a substrate of GaAs. Figure 9 is a cross sectional view of a glass array of the present invention prior to etching.
Figure 10 is a cross sectional view of the array Figure 9 after being partially etched.
Figure 11 is a cross sectional view of the partially etched array of Figure 10 after being bonded to a substrate.
Figure 12 is a cross sectional view of the array of Figure 11 after glass shaded in Figure 11 has been etched away.
Figure 13 illustrates the traslation of a mask over a substrate allowing the massively parallel fabrication of complex nanometer scale circuits.
Detailed description of the invention
The nanochannel mask of the present invention is a patterned arrangement of sub-micron sized holes or channels in a glass matrix. It is used where the deposition of desired materials (ions, electrons, photons, etc.) is physically blocked or passed in regions by overlaying the mask on a chemically active or energy sensitive surface above the substrate, or on a substrate directly. A multitude of complex configurations are possible. The fabrication process involves
■ an arrangement of dissimilar glasses of which at least one glass is acid etchable. In one embodiment of the invention, the mask is formed as a uniform array of equally spaced rods of acid etchable glass in a hexagonal 2-dimensional close packing arrangement. The hexagonal close packing arrangement of hexagonal glass fibers, with acid etchable channels of greater than 1 micron is a well known technology and is frequently used in the first processing step of microchannel plates.
As is shown in Figure 1, fabrication starts by insertion of a cylindrical acid etchable glass rod 2, the channel glass, into an inert hexagonal glass tube 4, the matrix glass, whose inner dimensions match that of the rod. The pair is then fused by heating the glasses close to the melting point. The pair is then drawn to reduce the overall cross-section to that of a fine filament. The filaments are then stacked, fused again and redrawn under vacuum as is shown in Figure 2. This process is continued until appropriate channel diameters and the desired number of array elements are achieved. Annealing of the glasses is necessary if the glasses chosen are susceptible to work hardening. By adjusting the ratio of the diameter of the etchable glass rod to that of the outside dimension of the hexagonal inert glass tubing, the center to center spacing of the rods and their diameters in the finished product become independently adjustable parameters. A section of the final product is shown in Figure 3 in which channels 6 extend through a matrix 8. Figure 4(a) shows a scanning electron micrograph (SEM) of a hexagonal close packing (HCP) arrangement of channel glasses in relief after acid etching. The sample contains approximately 5 x 106 channels arranged in a highly regular two dimensional array. The channels are extremely uniform in size throughout the entire area of the array with a diameter of approximately 450 nanometers and the center to center spacing is approximately 750 nanometers. Figure 4(b) shows a similar SEM micrograph with 90 nanometer channel diameters. The rough appearance of the channel boundaries and apparent cracking of the surface is due to the approximately 8 nanometer thick incomplete layer of gold deposited on the nanochannel mask surface to avoid charging effects during SEM analysis and is not indicative of the nanochannel mask itself.Figure 4(c) shows a similar SEM micrograph with 40 nanometer channel diameters. The fabrication process is very suitable to mass production requirements. The wafer-like nanochannel mask is generally only a few millimeters thick and is sectioned from a fused matrix bar several feet long. The fused matrix bar is cut from a longer matrix bar which continuously flows from the final drawing process. Up to 100 feet of identical fused matrix bar can be fabricated in a single run, from which more than 50,000 identical nanochannel masks can be cut. In order to produce a mask which can withstand the acid etching treatment, after the wafer-like mask has been cut from the fused stack of fibers, the mask should be annealed at an elevated temperature, preferably about 425°C for about 2 hours in order to relieve stress in the matrix.
By adjusting the geometry of the outer wall of the tubing so that it has a square, rectangular, triangular, etc. , cross- section, the packing arrangement or geometry of the array can be adjusted. Also, by adjusting the shape of the circumference of the channel glass, the channel shape can be altered. More intricate patterns can be fabricated by stacking dissimilar filaments next to each other. The fabrication process for the nanochannel mask array of the present invention yields extremely regular channels whose diameters are adjustable in size from microns to several nanometers.
In order to allow for etching of channels as small as those used in the present invention, the difference between the relative etch rates of the etchable glass to the inert glass needs to be very large. While in porous glass having larger pore sizes, the etch rate of the etchable glass is 1,000 to 10,000 times the etch rate of the inert glass, in the present invention, the etch rate of the etchable glass is preferably 105 to 107 the etch rate of the inert glass. Because of the microscopic size of the channels formed in the mask, it is also important that the two glasses not diffuse into each other while they are drawn. Therefore, a minimum of heat and time should be used while the glasses are being drawn. Although the exact drawing temperature is dependent on the glasses used, the drawing temperature is generally between 625 and 750°c. A preferred inert glass is corning glass 0120, 8161 or 0080. Corning Glass 0120 is a potash soda lead glass. Preferred etchable glasses are EG-1, EG-2 and EG-4 manufactured by Detector Technology. Using Corning Glass 0120 as the inert glass and EG-2 as the etchable glass, masks have been prepared having average channel diameters of less than 400 A, preferably less than 100 A.
Preferably, although acids such as nitric acid and hydrochloric acid can be used to etch the acid etchable glass, the acid used in the acid etching of the etchable glass is preferably an organic acid such as acetic acid which does not leave a residue on the acid inert glass. Preferably, the acid etching solution is at a concentration of 0.1 to 2%. In another embodiment of the nanochannel mask, an array is composed of solid homogeneous hexagonal rods of either etchable or inert glass. Examples of such masks are illustrated in Figures 5(a) and 5(b) . The dark regions are composed of acid etchable pixels or rods 10 and the light- regions are composed of inert pixels or rods 12.
An example of a mask with connecting structures is shown in Figure 6(a) . In another embodiment, fabrication of nanochannel glass includes the step of extruding D-shaped rods with small grooves along the center of the flat face, as shown on Figure 6(b) . For tighter tolerances, the groove may be cut instead of being formed by the die used in the extrusion to make the D-shaped rod. An acid-etchable glass fiber or rod drawn down to 100 microns in diameter or smaller is placed in the groove of the D-shaped rod and another D-shaped rod is attached. The rods are stacked for drawing sequences as already described. Nanometer dimensions of the channel diameters can now be accomplished in just two additional draws, minimizing the interdiffusion of the glass types. Extremely smooth, high definition channel walls can be fabricated in this fashion. The matrix glass chosen for the D- shaped rod must have a lower working temperature than the etchable iber so the matrix can" flow and close the area around the fiber during the vacuum drawing process without fiber distortion. In practice, a hexagonal rod is used since it has a closed packing geometry. As earlier, dark regions are composed of acid-etchable pixels or rods 10 and the light regions are composed of inert pixels or glass rods 12. In another embodiment, the fabrication method utilizes the radius of the corners of long glass bars with rectangular or square cross-sections. Figure 6(c) illustrates the square embodiment with dark regions composed of acid-etchable pixels or rods 10 and light regions composed of inert pixels or glass rods 12. The edges can be ground for greater accuracy. The assembly is clamped and drawn under vacuum to produce a fine square filament. The filaments can be restacked and redrawn or combined with other materials in a predetermined complex pattern. As before, channel diameters with nanometer dimensions can be fabricated in just two draws, thus greatly reducing the time the dissimilar glasses are in contact at elevated temperatures. Any other close packing geometry of glass bars, such as triangular, hexagonal, etc., can also be used. In still another embςdiment, illustrated in Figure 6(d), nanochannel glass is fabricated using solid bars 10 of acid-etchable glass in between much larger rods 12 of inert glass.
Squares, slabs and other structures can be inserted into the matrix if the physical properties (melting point viscosity at working temperatures, thermal expansion coefficient, etc.) of the inserted glass are chosen properly. Many other, more complex and intricate patterning of mask fabrication is possible. Figures 6(b) , 6(c) and 6(d) illustrate alternative glass fabrication methods using solid rods of different shapes and sizes. Examples of how the nanochannel mask can be used for quantum confined semiconductor device fabrication are described below.
When the semiconductor substrate/nanochannel mask system is used in conjunction with molecular beam epitaxy (MBE) fabrication techniques, islands of semiconductor material can be patterned over the existing substrate and the mask removed for further processing. This "direct writing" method is shown in figures 7 and 8 for a GaAs/AlGaAs system to fabricate a device containing a uniform array of quantum dots 20 suspended in a lattice 22 of matched AlGaAs deposited on a substrate 24 of GaAs. AlGaAs 22 is grown over a GaAs substrate 24 to act as a suitable base. A thin array nanochannel mask 26 is positioned over the AlGaAs base and additional AlGaAs (200-500 A thick) is laid down by MBE to form an array of pedestals 28. Mask 26 is removed and a thin layer of GaAs (50-400 A thick) is laid down forming a GaAs cap on top of each pedestal and a connected GaAs layer completely covering the base. A thick layer of AlGaAs is then deposited over the GaAs leaving an array of quantum dots 20 suspended over a quantum well structure 30 with holes punched into it. The interaction of the quantum well 30 with the quantum dot array 20 can be varied by adjusting the pedestal height (potential tunnel diode devices) . Another example of patterning a quantum dot array using the nanochannel mask for fabrication involves the deposition of a protective layer just over a quantum well structure. Again using the AlGaAs system as an example, a metal, such as aluminum, is deposited through the nanochannel mask onto the quantum well substrate. After some accumulation has occurred, the mask is removed. Aluminum is implanted into the substrate by ion implantation entering only those regions of the well not covered by the prior aluminum accumulation. The aluminum pedestals protect the lattice matched surfaces underneath them. The surface aluminum is then removed and the AlGaAs system is annealed by standard techniques, forming AlGaAs in the regions of the well previously unprotected. This produces a quantum dot array of GaAs embedded in a lattice matched host of AlGaAs. Multiple quantum wells can be used in a similar fashion to define a three dimensional array of quantum dots and a "thick" quantum well can be used to fabricate arrays of quantum wires.
For extended connected linear regions or regions where the mask is required to form a closed connected geometry, such as the top part of the R shown in Figure 6(a) , a different mask fabrication process is required. In such a case, the dark regions of Figure 6(a) are composed of acid etchable rods 10 with an etchable rate R1 and the light regions composed of rods 12 with etchable rate R2 where R. > R2. As shown in Figures 9, 10 and 11, fabrication can be accomplished by bonding an array 40 onto a substrate 42 after a slight acid etch to the contact surface 44 of array 40. As shown in Figure 12, further acid etching removes remaining etchable glass 10. Materials such as aluminum can then be deposited on substrate 42 as described above for other deposition processes. After deposition, glass 12 is etched away and substrate 42 is heated to remove any residual oxide layers.
The nanochannel mask of the present invention can be configured for a variety of other lithographic techniques. If the dark shaded glass 10 of Figure 6 is composed of a glass identical to the unshaded glass 12, except that the dark shaded glass 10 is doped with a material with a high absorption or scattering cross-section for X-rays (such as lead) , then a thin section of the mask can be used to define patterns optically, via x-rays, on energy sensitive surfaces. No etching of the glass is required. An inverted or negative lithographic mask can be fabricated in a similar way by applying the dopant material to the unshaded rods. Refinements include etching the dark pixels, leaving them as hollow tubes (unshaded glass doped) or filling the empty tubes with fully concentrated appropriate material to block the x-rays (unshaded glass not doped) . Longer wavelength photons (>λ/2) can also be applied by an evanescent wave approach. The nanochannel mask of the present invention can be used for large scale parallel fabrication of complex circuits by translating the mask over a substrate while deposition of a source through the mask is occuring. Figure 13 shows the translation of the mask 130 relative to substrate 132. Arrow 134 indicates translation or movement in the X plane whereas arrow 136 indicates mask translation in the Y plane. Source 138, which can be in the form material or energy, passes through nanochannels 140 in mask 130 to expose resist 142, deposit material, or to effect another reaction on substrate 132. By translating the mask in the X and/or Y planes, it is possible to fabricate complex circuits and various geometric shapes, using the invention described herein. L o w energy electrons or ions can also be used to define patterns on energy sensitive surfaces with the nanochannel mask. Very thin masks with empty channels can be fabricated by the dual etching process (with etchable rates R1 and R2) described above and used in conjunction with collimated beams of low energy ions or electrons. An electrically conductive glass can be chosen to pull away excess charge during processing. With broad spatial beam profiles, the entire pattern may be fabricated at once. The low energy mode of operation greatly reduces substrate damage and back scattering, greatly increasing pattern contrast and definition.
The nanochannel mask used in the method of the present invention combines the ease of simultaneous large scale (>107 elements) patterning of nanometer sized elements with the accuracy and precision of ion and electron beam direct writing, without the usual substrate damage associated with these techniques. The high temperature stability of the nanochannel mask makes nanometer scale lithography viable in molecular beam epitaxy (MBE) type applications for the first time. Fabrication of a new class of materials and devices that rely on both the shift in energy due to quantum confinement and cooperative effects between quantum confined elements in large arrays can now be realized. These include quantum enhanced laser materials of bulk proportions with adjustable output frequencies dependent upon the degree of confinement, ultra small (quantum) electronic devices, far infrared filters (derived from cooperative effects) and nonlinear optoelectronic devices to name a few. The most unique properties of the nanochannel mask are: the high temperature stability of the glass, the very small size of the channels and the accuracy and precision to which these small channels can be arranged to form very large and complex mask structures. Regular arrays can be fabricated with extremely good geometric uniformity and very low variance in channel dimensions. Channel packing densities can approach I02/cra and channel diameters can be made under 10 nanometers (100 A) with great precision. The fabrication process allows complex formations to be repeated many times within the mask which is important in memory and logic circuits. In addition, up to 50,000 identical thin masks can be produced in a single run. This makes the nanochannel mask and its fabrication process well suited to industrial mass production techniques. In general, a variety of devices can 5 be fabricated using the nanochannel mask which are unique or surpass existing devices in their functions and performance.
F o r purposes herein, glass is a noncrystalline substance formed usually by the fusion of the constituent materials by melting
10 followed by cooling to yield a supercooled solution which most closely resembles a rigid liquid. Electronic strucktures noted herein, such as masks, have thickness on the order of up to millimeter whereas wafer-like masks should be as thin as possible up to a few nanometers, preferably about 1 to 50
15 nanometers. Masks for ion implantation, should be about 1 to 20 microns. Masks for particle deposition should be as thin as possible prefably on the order of a few tens of nanometers, especially on the order of a few nanometers.
The formation of the nanochannel glass mask will now be
20 described by way of the following examples.
Example I The inert glass used was a hexagonal tube of Corning Glass 0120 glass. The etchable glass used was Detector Technology's
25 EG-2. The glasses were fused under vacuum during the drawing process at a temperature of 625 to 750°C and were drawn down to fine filaments of 0.01 to 0.2 inches (0.03 to 0.5 cm) and cut to lengths of 1 to 3 feet (30 to 90 cm) . The filaments were stacked into bundles, approximately 1.5 inches flat to
30 flat, drawn and restacked and redrawn until the desired channel diameter was achieved. Just before the final draw, a cladding was added for strength and to facilitate handling by placing the bundle inside a hollow tube (usually Corning 0120 glass) and drawing under vacuum. To relieve the stress, the glass
35. composition was annealed after each draw. The glass was-then cut to the desired length, polished and etched in a weak acid such as 1% HCL, HNo3 or acetic acid to remove the channel glass and leave behind the porous matrix glass and cladding. Example II Hexagonal monofilaments of Corning 0120 glass and Detector Technology's EG-2 were used as the inert glass and etchable glass filaments, respectively. The monofilaments, typically 0.01 to 0.1 inches (0.025 to 0.25 cm) in width were stacked in predetermined pattern which can be used to make arrays. After the monofilaments are stacked, the process is essentially the same as described in example I. An advantage to using this technique is that one less draw is required in which the dissimilar filaments are in contact with each other at elevated temperatures, greatly reducing the diffusion of glasses into one another and yielding a stronger matrix as well as finer resolution, especially at glass dimensions around 10 nanometers. Another advantage is that individual pixel replacement is possible with a variety of glass types making very complex structures possible.

Claims

What is claimed is:
1. A method for depositing a pattern of deposited material on or within a substrate, comprising the steps of: interposing a glass mask between a source and a substrate, the mask having channels therethrough which are arranged in a pattern which have an average diameter of less than 1 micron; and depositing a material selected from the group of sources consisting of ions, electrons, photons, metals and semiconductor materials through the glass mask into or onto the substrate.
2. A method for depositing a pattern of semiconductor material according to claim 1, wherein the channels through the mask have an average diameter of less than about 400 A.
3. A method for forming a semiconductor device, comprising the steps of: growing a first layer of first semiconductor material over a second semiconductor material substrate to form a base; interposing a glass mask between the base and a source of the first semiconductor material; depositing additional first semiconductor material through the glass mask and onto the base to form an array -of pedestals; removing the mask; depositing a second layer of the second semiconductor material to form a cap on top of each pedestal and to form a connected layer of the second semiconductor material completely covering the base; and depositing a layer of the first semiconductor material over the second layer of the second semiconductor material to form an array of quantum dots suspended over a quantum well structure having holes therein.
4. A method for forming a semiconductor device according to claim 3, wherein the first semiconductor material comprises algaas and the second material comprises gaas.
5. A semiconductor device made according to the process of claim 3. 6. A method for forming a semiconductor device comprising the steps of: interposing a glass mask between a semiconductor material substrate and a source of dopant, the mask having channels therethrough which are arranged in a pattern and which have a average diameter of less than 1 micron; depositing the dopant through the mask and onto the substrate of semiconductor material; removing the mask; ion implanting additional dopant into the substrate; removing dopant on the surface of the substrate; and annealing the doped substrate to form a semiconductor device.
7. A method according to claim 6, wherein the metal dopant • is aluminum and the substrate comprises heterostructures.
8. A semiconductor device made according to the process of claim 6.
9. A method of forming a semiconductor device comprising the steps of: forming a glass block of an acid inert glass having acid etchable glass rods extending therethrough, the acid etchable glass rods having a diameter of less than 1 micron, the acid inert glass having a lower melting point than the acid etchable glass; partially etching the acid etchable rods so that an exposed surface of the acid inert glass block extends above the ends of the acid etchable rods; bonding the exposed ends of the acid etchable rods to a substrate; etching away the acid etchable rods from the acid inert glass to form a mask on the substrate; and depositing a coating selected from the group consisting of metals and semiconductor materials through the mask onto the substrate to form a semiconductor device.
10. A semiconductor device made according to the method of claim 9. AMENDED CLAIMS
[received by the International Bureau on 14 September 1993 (14.09.93); original claims 3, 4, 6 and 9 amended; other claims unchanged (2 pages)]
1. A method for depositing a pattern of deposited material on or within a substrate, comprising the steps of: interposing a glass mask between a source and a substrate, the mask having channels therethrough which are arranged in a pattern which have an average diameter of less than 1 micron; and depositing a material selected from the group of sources consisting of ions, electrons, photons, metals and semiconductor materials through the glass mask into or onto the substrate.
2. A method for depositing a pattern of semiconductor material according to claim 1, wherein the channels through the mask have an average diameter of less than about 400 A.
3. A method for forming a semiconductor device, comprising • the steps of: growing a first layer of first semiconductor material over a second semiconductor material substrate to form a base; interposing a glass mask between the base and a source of the first semiconductor material, the mask having channels therethrough which are arranged in a pattern which have an average diameter of less than 1 micron; depositing additional first semiconductor material through the glass mask and onto the base to form an array of pedestals; removing the mask; depositing a second layer of the second semiconductor material to form a cap on top of each pedestal and to form a connected layer of the second semiconductor material completely covering the base; and depositing a layer of the first semiconductor material over the second layer of the second semiconductor material to form an array of quantum dots suspended over a quantum well structure having holes therein.
4. A method for forming a semiconductor device according to claim 3, wherein the first semiconductor material comprises AlGaAs and the second material comprises GaAs.
5. A semiconductor device made according to the process of claim 3.
SUBSTITUTESHEET
6. A method for forming a semiconductor device comprising the steps of: interposing a glass mask between a semiconductor material substrate and a source of metal dopant, the mask having channels therethrough which are arranged in a pattern and which have a average diameter of less than 1 micron; depositing the dopant through the mask and onto the substrate of semiconductor material; removing the mask; ion implanting additional dopant into the substrate; removing dopant on the surface of the substrate; and annealing the doped substrate to form a semiconductor device.
7. A method according to claim 6, wherein the metal dopant is aluminum and the substrate comprises heterostructures.
8. A semiconductor device made according to the process of claim 6.
9. A method of forming a semiconductor device comprising the steps of: forming a glass block of an acid inert glass having acid etchable glass rods extending therethrough, the acid etchable glass rods having a diameter of less than 1 micron, the acid inert glass having a lower melting point than the acid etchable glass; partially etching the acid etchable rods so that an exposed surface of the acid inert glass block extends above the ends of the acid etchable rods; bonding the exposed ends of the acid inert glass block to a substrate; etching away the acid etchable rods from the acid inert glass to form a mask on the substrate; and depositing a coating selected from the group consisting of metals and semiconductor materials through the glass block onto the substrate to form a semiconductor device.
10. A semiconductor device made according to the method of claim 9.
SUBSTITUTE SHEET
PCT/US1993/004563 1992-06-12 1993-05-19 Using a nanochannel glass mask to form semiconductor devices WO1993026039A1 (en)

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