WO1994015363A1

WO1994015363A1 - Non-volatile semiconductor memory cell

Info

Publication number: WO1994015363A1
Application number: PCT/US1993/012485
Authority: WO
Inventors: Shih-Chiang Yu
Original assignee: Yu Shih Chiang
Priority date: 1992-12-28
Filing date: 1993-12-20
Publication date: 1994-07-07
Also published as: EP0676088A1; EP0676088A4; JPH07509813A; JP2749449B2

Abstract

A non-volatile memory cell (2) including a floating gate (16) dielectrically disposed between a first control gate (12) and a second control gate (14). Addressing of the memory cell (2) for programming, de-programming and reading involves the simultaneous energization of both the control gates (12 and 14). The energization of only one control gate, but not both, can not activate the memory cell (2). A memory cell array comprising the memory cells of the present invention can be arranged in a matrix format. Addressing of each of the memory cell (2) in the array is simply the simultaneous energization of a pair of control gates (12 and 14) perpendicularly criss-crossing the underlying memory cell. Further modifications in the design of the memory cell (2) enable the memory cell to be programmed with negative threshold voltages, thereby relaxing the manufacturing tolerances, and consequently reduces the production cost.

Description

Non-Volatile Semiconductor Memory Cell

Technical Field

This invention relates to electronic memory devices. More specifically, this invention is related to memory devices of the non-volatile type fabricated in a semiconductor substrate.

Contrary to volatile memory devices, non-volatile devices retain their informational contents even with power loss. Examples of circuits utilizing non-volatile devices are Electrical Programmable Read Only Memory (EPROM) , Electrical Erasable and Programmable Read Only Memory (EEPROM) , and more recently, flash memory used for substituting hard disks in computer systems.

Background Art

Heretofore, memory cells used in non-volatile memory circuits are generally of the type with a floating gate dielectrically disposed between a channel and a control gate. A high voltage applied to the control gate enables the control gate to capacitively couple the floating gate to attract charges into or out of the floating gate. Accumulation or depletion of charges in the dielectrically isolated floating gate forms the basis of informational storage. Examples of such memory cell are found in United States Patent No. 5,057,886, entitled "Non-Volatile Memory with Improved Coupling Between Gates" to Riemenschneider et al., 15 October, 1990; and European Patent No. 0459319A2, entitled "Floating Gate Field Effect Transistor Structure and Method for Manufacturing the Same" to Chen, 13 November 1991.

The aforementioned memory cells are normally arranged in a matrix of rows and columns. Addressing of such memory cells is quite complicated. Essentially, it involves the selection of the memory cells in the entire row or column. The memory cells of the selected row or column is then individually addressed for programming, deprogramming or reading. Very often, elaborated decoding circuitries are required, and special timing circuits are also needed for the generating of proper sequential timing pulses for addressing. There are non-volatile memory cell with a floating gate controlled by more than one control gate developed in the past. Examples are United States Patents No. 5,153,691, entitled "Apparatus for a Dual Thickness Floating Gate Memory Cell" to Guterman, 6 October, 1992; and United States Patents No. 4,910,565, entitled "Electrically Erasable and Electrically Programmable Read-only Memory* to Masuoka et al. , 20 May, 1990.

However, each of the control gate is assigned a dedicated duty of either programming of deprogramming, but not both. Addressing of the memory cells can not be randomly accessed and is still complicated.

Disclosure of the Invention

In accordance with the present invention, there is provided a non-volatile memory semiconductor cell capable of being addressed swiftly at random, and without any reliance on complicated addressing schemes. Equally important, the inherent unique design enables the minimization of inter- layer vias which are known to be large in physical size. As a result, higher number of cells can be integrated within a unit of semiconductor space.

The present invention achieves these ends by disposing a floating gate in between two control gates within a memory cell. The floating gate can only be triggered into the charging or discharging processes by the simultaneous energization of the two control gates. The energization of only one of the control gates, but not both, can not provoke the floating gate into action. The control gates are preferably disposed perpendicular to each other atop the semiconductor substrate. Memory cells of the present invention can be arranged in a matrix of rows and columns. Addressing of any of the memory cells in the matrix is simply the simultaneous energization of a pair of selected controlled gates.

Various embodiments with different applications can be derived from the aforementioned arrangement. Different arrangements between the control gates and the floating gate also allows the mon-volatile memory cell to be programmed with negative threshold voltages, thereby substantially relaxing the manufacturing tolerances and costs.

Brief Description of Drawings

Fig. 1 is a top plan view showing a first embodiment of memory cell of the present invention; Figs. 2 & 3 are cross-sectional side views taken along lines

2-2 and 3-3, respectively, of Fig. 1;

Fig. 4 is a schematic representation of the memory cell shown in Figs. 1-3;

Fig. 5 is a table of potential values for the various operations of memory cell shown in Figs. 1-3;

Figs. 6A is a top plan view of a memory cell array comprising memory cells shown in Figs. 1-3;

Figs 6B-6C are cross-sectional side views taken along lines

6B-6B and 6C-6C, respectively, of Fig. 6A; Figs. 7A-7H are sequential drawings showing the process of fabrication of the memory array shown in Figs. 6A-6C;

Fig. 8 is a schematic representation of the memory cell array shown in Fig. 6A; Fig. 9 is a cross-sectional side view of the memory cell shown in Figs. 1-3 with slight modification in design;

Fig. 10 is a schematic representation of the memory cell shown in Fig. 9; Fig. 11 is a cross-sectional side view of the memory cell shown in Figs. 1-3 with another modification in design;

Fig. 12 is a schematic representation of the memory cell shown in Fig. 11;

Fig. 13 is a top plan view showing a second embodiment of the memory cell of the present invention;

Figs. 14 & 15 are cross-sectional side views taken along lines 14-14 and 15-15, respectively, of Fig. 13;

Fig. 16 is a schematic representation of the memory cell shown in Figs. 13-15; Fig. 17 is a table of potential values for the various operations of memory cell shown in Figs. 13-15;

Fig. 18 is a schematic representation of a memory cell array comprising memory cells shown in Figs. 13-15;

Fig. 19 is a cross-sectional side view of the memory cell shown in Figs. 13-15 with slight modification in design;

Fig. 20 is a schematic representation of the memory cell shown in Fig. 19;

Fig. 21 is a cross-sectional side view of the memory cell shown in Figs. 13-15 with another modification in design; Fig. 22 is a schematic representation of the memory cell shown in Fig. 21;

Fig. 23 is a top plan view showing a third embodiment of memory cell of the present invention;

Figs. 24 & 25 are cross-sectional side views taken along lines 24-24 and 25-25, respectively, of Fig. 23;

Fig. 26 is a schematic representation of the memory cell shown in Figs. 23-25;

Fig. 27 is a table of potential values for the various operations of memory cell shown in Figs. 23-25; Fig. 28 is schematic representation of a memory cell array comprising memory cells shown in Figs. 23-25;

Fig. 29 is a cross-sectional side view of the memory cell shown in Figs. 23-25 with slight modification in design; Fig. 30 is a schematic representation of the memory cell shown in Fig. 29;

Fig. 31 is a top plan view showing a fourth embodiment of memory cell of the present invention;

Figs. 32-34 are cross-sectional side views taken along lines 32-32, 33-33, and 34-34, respectively, of Fig. 31;

Fig. 35 is a schematic representation of the memory cell shown in Figs. 31-34;

Fig. 36 is a table of potential values for the various operations of memory cell shown in Figs. 31-34; Fig. 37 is a schematic representation of a memory cell array comprising memory cells shown in Figs. 31-34;

Fig. 38 is a cross-sectional side view of the memory cell shown in Figs. 31-34 with a variation in design; and

Fig. 39 is a cross-sectional side view of another memory cell as shown in Fig. 38 with another variation in design.

Modes for Carrying Out the Invention

Reference is now made to Figs. 1-4, which show the first embodiment of the present invention generally designated by reference numeral 2. Fig. 1 is the top plan view of non-volatile memory cell 2, while Figs. 2 and 3 are cross-sectional side views taken along line 2-2 and 3-3 of Fig. 1, respectively. In this embodiment, formed in a P- type semiconductor substrate 4, for example, are N-type source 6 and drain 8 defining a channel 10 therebetween. Source 6, drain 8 and channel 10 formed in semiconductor substrate 4 form a basic Metal Oxide Semiconductor (MOS) transistor 11. Functionally, channel 10 is divided into a first portion 10A and a second portion 10B. Dielectrically overlying first portion 10A of channel 10 is a first control gate 12. There is also a second control gate 14 dielectrically disposed atop first control gate 12. Dielectrically formed between first and second control traces 12 and 14 is a floating gate 16 having a first segment 16A and a second segment 16B. First segment 16A is formed in between control traces 12 and 14 while second segment 16B dielectrically overlies the second portion 10B of channel 10. Various insulating layers electrically isolate the different gates and the semiconductor substrate 2. In this embodiment, the insulating layers are thermally grown silicon dioxide (SiO^) . For examples, formed first control gate 12 and first portion 10A of channel 10 is insulating layer 18A, while between second segment 16B of floating gate 16 and second portion 10B of channel 10 is insulating layer 18E. Disposed between first segment 16A of floating gate 16 and first control gate 12 is insulating layer 18B. Second control gate 14 overlies floating gate 16 via insulating layer 18C. It should be noted that in this embodiment, first control gate 12 and second control gate 14 are elongated in shape and are dielectrically disposed atop the semiconductor substrate 4 substantially perpendicular to each other. This arrangement is clearly shown in Fig. 1. There are also doped isolating regions 20 formed in semiconductor substrate 2 adjacent drain 8 for the prevention of layer inversions caused by the possible overlying metal traces with biased potentials. Alternatively, isolating regions 20 can be formed of insulators such as silicon dioxide. Fig. 4 shows the schematic representation of memory cell 2.

The non-volatile memory cell 2 is capable of three operations, namely, programming, deprogramming and reading. In this embodiment, programming involves the process of trapping electrons in floating gate 16 such that the trapped electrons diecectrially inverts the underlying channel 10 and raise the threshold voltage Vth of MOS transistor 11 to be more than 5 Volts. Conversely, deprogramming involves the process of repelling electrons from floating gate 16 such that the positively charged floating gate 16 couplingly attracts and accumulates electrons in the underlying channel 10 and lowers the threshold voltage Vth of MOS transistor 11 to between 2 Volts and 3 Volts. Reading is a process detecting the threshold voltages of MOS transistor 11. Programming and deprogramming can be accomplished through different methods of charge tunneling into or out of floating gate 16, namely. Source Side Injection (SSI), Hot Electron Injection (HEI) and Fowler-Nordheim Tunneling (FNT) . In terms of performance, SSI is by far is the best candidate and is also relatively low in power consumption. SSI is ideal for applications in which speed is of paramount importance, such as flash memory. FNT is the least power consuming but is also relatively slow in speed. In this embodiment, to suit various applications, programming can be achieved via the SSI, HEI and FNT effects. While deprogramming is normally performed simultaneously with a block of memory cells, to reduce power consumption, the FNT method is therefore adopted.

Fig. 5 is a table of potential values applied to the control gates 12 and 14, source 6, drain 8 and substrate 4 for the various operations. Each method is herein briefly described.

For SSI to take place, first and second control gates 12 and 14 are first energized to 2 Volts and 12 Volts, respectively. Drain 8 is tied to 6 Volts and source 6 is clamped down at 0 Volt. Assume there are coupling efficiencies of 20% and 50% between floating gate 16 and each of the control gates 12 and 14, respectively. Floating gate 16 is therefore capacitively coupled with 0.4 Volt by first control gate 12, in addition to 6.0 Volts coupled by second control gate 14. That is, floating gate 16 is capacitively coupled with a total of 6.4 Volts by the two control gates 12 and 14. This is sufficient to turn second portion 10B of channel 10 on. As a result, the 6 Volts sitting at drain 8 is directly reflected at region 21 in channel 10, since second portion 10B is conductive. However, fist control gate 12 is at 2 Volts. The result is that first portion 10A of channel 10 is also turned on and is conductive. Consequently, 0 Volt in source 6 is also directly reflected in an area adjacent region 21 in channel 10. In reality, the vicinity of region 21 is a small and confined space with a very steep potential gradient. As a consequence, the electrons are highly energized with some flow in region 21 in the direction from source 6 to drain 8 and others side-track and jump into floating gate 16. After the de-energization of the control traces 12 and 14. Electrons are trapped inside floating gate 16. The trapped electrons couplingly repel the electrons in second portion 10B of channel 10, thereby inverting second portion 10B of channel 10 and raised the threshold voltage Vth of MOS transistor 11 to be more than +5 Volts. Memory cell 13 is said to be programmed.

For HEI to take place, both control gates 12 and 14 need to be energized to 12 Volts each. Drain 8 is set at 6 Volts and source 6 is clamped at 0 Volt. As with the case as before, assume there is a 20% and a 50% coupling efficiency between floating gate 16 and each of the control gates 12 and 14, respectively. Floating gate 16 is capacitively coupled with a voltage of 8.4 Volts. First and second portions 10A and 10B of channel 10 are fully turned on, resulting in the 0 Volt potential at source 6 directly reflected at region 25 in channel 10. Consequently, a steep potential gradient develops around the vicinity of region 25, enabling electrons to travel in the direction from source 6 to drain 8, with some highly energized electrons side-tracking and jumping into floating gate 16. It should be noted that electron tunneling via HEI consumes more power than via SSI.

For FNT to take into effect, both control gates can be energized to 20 Volts. Drain 8 is left floating electrically while source 6 is clamped to 0 Volts. Due to capacitive coupling and with a 20% and a 50% coupling efficiency between floating gate 16 and each of the control gates 12 and 14, respectively, floating gate 16 is capacitively coupled with 'a voltage of 14 Volts. This voltage level is high enough for FNT tunneling to take place, during which electrons are injected into floating gate 16 through insulating layer 18E. It should be noted that there are no electron travelling from source 6 to drain 8 during the FNT process since drain 8 is floating electrically.

For the reading of information stored in memory cell 2, both control gates 12 and 14 need to be energized to 5 Volts. The drain is set at 2 Volts while the source is tied to the ground potential. With a 20% and a 50% coupling efficiency between floating gate 16 and each of the control gates 12 and 14, respectively, floating gate 16 is capacitively coupled with a voltage of 3.5 Volts. First portion 10A of channel 10 is turned on due to the overlying first control trace 12 being biased at 5 Volts. If memory cell 2 is previously de-programmed with MOS transistor 11 at a threshold voltage Vth of below +3 Volts, current will flow from drain to source (opposite to the direction of electron flow). Memory cell 2 is said to be read with a logic "0", for example. However, if MOS transistor 11 is previously programmed with a threshold voltage of above +5 Volts, the 3.5 Volts coupled in floating gate 16 is insufficient to turn second portion 10B of channel 10 on. The result is that no current can flow from drain 8 to source 6. Memory cell 2 is said to be read with a logic "1", for example.

It here should be emphasized again that memory cell 2 can be addressed for programming, deprogramming or reading only with the simultaneous energization of both the first and second control gates. The energization of only one control gate, but not both, is insufficient to activate memory cell 2. This forms the basis of matrix addressing which is superior than most prior art addressing methods.

For a consistent illustration, in this description and in the appended claims, ^• the. terms "simultaneously" or

"simultaneous" are construed as the occurrence of more than one event overlappingly in the time domain. Thus, in this case, when the two control gates are described as simultaneously energized, the timing of energization for each of the control gates may be different. However, there is always an overlap of time when both the control gates are energized. Fig. 6A shows memory cells 2 arranged in a partial matrix of 3 rows and 4 columns. Figs. 6B and 6C are cross- sectional side views taken along lines 6B-6B and 6C-6C, respectively, of Fig. 6A. First control gates 12 of each of the memory cells 2 in a same row are electrically connected together and form X-control traces 22A-22C. Similarly, second control gates 14 of each of the memory cells 2 are electrically connected together and forms Y-control traces 24A-24D. As an illustration, suppose memory cell 2A in the second row and the third column needs to be identified for programming, deprogramming or reading. X-control trace 22C and Y-control trace 24C must be energized in accordance with the potential table shown in Fig. 5 for the respective operations. All other memory cells with either one, of both control traces de-energized can not be activated. With this arrangement, any of the memory cells 2 in the matrix can be addressed swiftly and randomly for programming, deprogramming and reading. This is in sharp contrast with most prior art memory cell arrays in which addressing of an specific cell involves the access of the entire row or column, and the particular cell of the selected row or column is then individually activated. These type of prior art arrays requires very complicated addressing circuitries and timing schemes. The novel addressing mechanism in the present invention also allows the elimination of inter-layer vias commonly used in many prior art memory cell arrays. Vias are known to be space ^•consuming and are obstacles for high density integration.

Figs. 7A-7H are sequential drawings showing the steps of fabrication of a memory array of the present invention. Figs. 7B, 7D, 7F, and 7H are cross-sectional side view of Figs. 7A, 7C, 7E,.and 7G, respectively. To begin with, as shown in Figs. 7A-7B, a P-type semiconductor substrate 4 is selected and is thermally grown with an insulating oxide 18 to a thickness of approximately 500 Angstroms. A layer of polysilicon is then deposited atop insulating oxide 18 to a thickness of approximately 4500 Angstroms, and further doped to a resistance of 4 Ohms. The conventional masking and etching methods are then employed for the formation of first control gates 12. A thin layer of insulating oxide 18B of approximately 100 Angstroms is then grown atop first control gates 12. the resultant structure up to this step is shown in Figs. 7C-7D. Another polysilicon layer of approximately 2500 Angstroms is again deposited onto the semiconductor substrate. This polysilicon layer is then doped to a resistance of 7 Ohms. The conventional steps of masking and etching then follow for the definition of floating gates 16. Selected locations in insulating layer 18 is then etched away, and the substrate 4 is then subjected to ion implantation for the formation of sources 6 and drains 8. In this embodiment, the implanted ions are Arsenic (As) . The resultant structure up to this step is shown in Figs. 7E-7F. Thereafter, a thermally grown insulating layer is formed atop the resultant structure. One more layer of polysilicon with a thickness of approximately 4500 Angstroms is also deposited on the top of the insulating layer. The polysilicon is then doped to a resistance of about 4 Ohms. Conventional masking and etching steps are again employed for the definition of second control traces 16. The finished structure is shown in Figs. 7G-7H.

Processing steps, such as those relating to peripheral circuits of the memory array, or the metallization for interconnections, are beyond the scope of the present invention and is therefore not included in here. However, it should be noted that the fabrication step described above may be conducted in a different sequence to suit the requirements of the peripheral circuits.

Fig. 8 shows the memory array of Fig. 6 in schematic format. Fig. 9 shows a memory cell 26 with a slight variation with respect to the embodiment shown in Figs. 1-3. In memory cell 26, second segment 28B of floating gate 28 is somewhat perpendicular to the channel 10. This feature allows a slight reduction of cell size. Fig. 10 shows the schematic representation of memory cell 26 shown in Fig. 9.

Fig. 11 shows another memory cell 30 with another variation with respect to the memory cell 2 shown in Figs.

1-3. In memory cell 30, floating gate 32 comprises a third segment 32C dielectrically disposed atop source 6. Third segment 32C of floating gate 32 further speed up the deprogramming process by tunneling electrons directly into the source. In this case, the de-programming process requires both control gates 12 and 14 energized to -20 Volts. The source 6 is tied to 0 Volt while the drain 8 is left floating electrically. Assume a 20% and a 50% coupling efficiency between floating gate 32 with each of the control gates 12 and 14, respectively, floating gate 32 is capacitively coupled with 14 Volts, which is sufficient to trigger the FNT effect. The tunneling of charges takes place between third segment of floating gate 32C and source 6 mainly because source 6 is at the lowest potential.

As was described in the previous embodiments in which the threshold voltage Vth of MOS transistor 11 is at a +5 Volts for logic "1", and at +3 Volts for logic "0". A threshold voltage set below 0 Volt is undesirable as a transistor with threshold voltage below 0 Volt is inherently turned on with a conductive channel. An inherently "ON" memory cell placed in a memory array negatively affect the operations of the array. To maintain the threshold voltage Vth of transistor 11 in memory cell 2 to be above the positive threshold voltage level, tight manufacturing tolerance must be imposed. Specifically, the thickness of insulating layers 18A-18E must be precisely monitored, and the alignment of masking for the floating gates and the control gate needs to be accurate. This inherently raises manufacturing cost.

The unique designs of the subsequent embodiments enable the threshold voltages of each of the memory cell to be programmed below 0 Volt. As a result, substantial manufacturing costs can be saved.

Figs. 13-15 shows yet another embodiment of the present invention. The memory cell of this embodiment is designated by reference numeral 34. This embodiment is characterized by the second control gate overlying a portion of the channel. This feature serves a special purpose which will be explained later.

As with the previous embodiment, formed in semiconductor substrate 36 is a MOS transistor 37 which comprises source 38 and drain 40 with a channel 48 disposed therebetween. Channel 48 includes a first portion 48A, a second portion 48B and a third portion 48C. Atop first portion 48A of channel 48 is the first control gate 42. Dielectrically formed above first control gate 42 is the second control gate 44. Between first and second control gates 42 and 44 is the floating gate 46. Floating gate 46 comprises a first segment 46A dielectrically disposed between first and second control gates 42 and 44, a second segment 46B dielectrically overlying the second portion 48B of channel 48, and a third segment 46C dielectrically disposed atop source 38. ^• Isolations beyond the channel region is accomplished by isolation regions 50 shown in Figs. 13 and 15. As with the memory cells of the previous embodiment, memory cell 34 is capable of programming, deprogramming and reading. The table of potentials for the various operations is shown in Fig. 17. In terms of operational details, there are a lot of similarities between this embodiment and the previous embodiments. Only the differences are therefore elaborated.

Depending on the performance vs power requirement, programming of memory cell 34 can be accomplished via SSI,

HEI or FNT. Deprogramming of memory cell 34 is achieved via FNT with electrons flowing into source 38 through third segment 46C of floating gate 46.

The main characteristic of this embodiment is a portion of second control trace 44 overlying the third portion 48C of channel 48. This feature allows MOS transistor 37 to be de-programmed with a threshold voltage of negative values, such as -2 Volts as in this embodiment. In contrast with many prior art memory cell array in which the de-programmed threshold voltage must be maintained above the positive value. The reason is that if the threshold voltage falls below 0 volt, the transistor is at a "ON" state with a conductive channel, resulting in the source and the drain being electrically connected together. The consequence is two fold. First, the memory cells are normally arranged in a matrix format with the transistor drains in each of the matrix columns connected together to form a bit line, while the transistor sources are shorted to ground potential. A conductive transistor with a shorted channel in any of the column will yield a false read operation in the particular column. In addition, an electrically shorted channel in any of the transistors in that column effectively clamps the bit line to the ground potential, which practically renders the memory cell to be non-programmable. For these reasons, the de-preprogrammed threshold voltage must be maintained above the 0 volt in most prior art structures. Extra circuitries for checking and refreshing must be implemented to ensure that this criterion is met. This imposed restriction places further complication in design and cost. Reference is now directed to Fig. 16 which shows the schematic representation of the memory cell 34 illustrated in Figs. 13-15. For the ease of understanding, memory cell 34 is functionally partitioned into 3 transistors 34A, 34B, and 34C. The corresponding partitions are also shown in Fig. 14 and is identified with parentheses. As shown in Figs. 14 and 16, transistor 34C is controlled by second control gate 44 alone, while transistor 34B is controlled by floating gate 46. Transistor 34A is controlled by first control gate 42. The principles of programming and de- programming in this embodiment is substantially the same as the previous embodiment and is not repeated in here. During the read operation, voltage potentials of 1 Volt, 3 Volt, 3 Volt and 0 Volt are applied to drain 40, second control gate 44, first control gate 42 and source 38, respectively. Suppose MOS transistor 37 is programmed with a 6 Volt threshold voltage, which constitutes a logic "0" in this embodiment. The 3 Volts voltage at both the first and second control gates 42 and 44 turns transistor 34A and 34C on. However, the coupled potential in floating gate 46 is only 2.1 Volts, in which 0.6 Volt comes from the capacitive coupling of first control trace 42 with a coupling efficiency of 20%, and 1.5 Volts come from the capacitive coupling of second control trace 44 with a coupling efficiency of 50%. Therefore, transistor 34C can not be turned on. As a consequence, the digital bit "0" is read, for example. In a similar manner, suppose that MOS transistor 37 is de-programmed with a -2 Volts threshold voltage. With the voltages at first and second control gates 42 and 44 at 3 Volts, transistors 34A, 34B and 34C are all turned on. Consequently, the digital bit "1" is read, for example.

Fig. 18 is a schematic representation of the memory cells 34 shown in Figs. 13-15 connected in a array of rows and columns. As with the array of the previous embodiment. First control gates 42 of each of the memory cells 34 in a same row are electrically connected together and form Y- control traces 54A-54D. Similarly, second control gates 44 of each of the memory cells 34 are electrically connected together and forms X-control traces 52A-52B.

The restriction that memory cell 34 must maintain a positive threshold voltage is no longer demanded in this embodiment. The reason is due to the unique design of memory cell 34 in which transistor 34C is off when it is not addressed. With transistors 34C of the non-addressed memory cells off, the voltage of the bit line will not be pulled down during the read operation, and the word line will not be clamped down during the programming or deprogramming of other cells. Again, it also needs to be emphasized that only the memory cell 34 under both the energized X-control trace 52 and the Y-control trace 54 can be addressed for programming, deprogramming or reading. Memory cells under only one energized control trace, but not both, can not be activated. The reason is when either one of the control traces 52 or 54 is not energized, the coupled potential at floating gate 46 is not sufficiently high enough to cause any tunneling effect during the programming or de¬ programming operations, or turn on transistor 34C during the read operation.

Figs. 19 and 20 shows another memory cell 56 with slight design modification.with respect to memory cell 34 shown in Figs. 13-15. In memory cell 56, floating gate 58 comprises first and second segments 58A and 58B. Tunneling of electrons during programming and de-programming occurs between the second segment 58B of floating gate 58 and channel 60. The other characteristics of memory cells 56 are substantially the same as memory cell 34 mentioned previously. Fig. 21 and 22 shows yet another memory cell 62 with floating gate 64 having a first segment 64A and a second segment 64B. Second segment 64B of floating gate 64 is placed adjacent to the source 66. The other characteristics and operations of memory cell 62 are substantially the same as the memory cell 56 as was mentioned.

The process of manufacturing memory cell 34 is substantially the same as before but with only slight modifications.

Figs. 23-26 shows a third embodiment of the present invention. The memory cell of this embodiment is signified by reference numeral 70 and is characterized by a diffusion region in a portion of the channel. This arrangement, in conjunction with the adoption of the negative logic convention, enable memory cell 70 to be programmed with a negative threshold voltage having advantages as were previously mentioned. Memory cell 70 is also ideal for applications where a high density array is required. Specifically, the array with the drain of the memory cell connected in series with the source of the adjacent cell as shown in Fig. 28. The operational mechanism of the array will be discussed later.

Referring now to Figs. 23-26, as in the previous embodiments, formed in a P-type semiconductor substrate 72, for example, are N-type source 76 and drain 78. Between source 76 and drain 78 is a N-type electrically floating region of diffusion 74. A channel 80 is also formed between the drain 78 and diffusion region 74. Source 76, drain 78 and channel 80 formed in semiconductor substrate 72 constitutes a MOS transistor 82. Dielectrically overlying N-type diffusion region 74 is a first control gate 86. There is also a second control gate 88 dielectrically formed atop first control gate 86. Dielectrically disposed between first and second control gates 86 and 88 is a floating gate 90. Floating gate 90 is functionally divided into a first segment 90A and a second segment 90B. First segment 90A of floating gate is formed in between control traces 86 and 88 while second segment 90B of floating gate 90 dielectrically overlies channel 80. Various insulating layers electrically isolates the different gates and the semiconductor substrate 2.

The three operations of memory cell 70 is summarized as shown in Fig. 27. There are a number of similarities between this embodiment and the previous embodiments. For a concise description, only the differences are illustrated.

In this embodiment, when the threshold voltage Vth of

MOS transistor 82 is programmed to 2 Volts, memory cell 70 is said to be programmed with a logic "1". Conversely, when the threshold voltage Vth of MOS transistor 82 is programmed to -2 Volts, memory cell 70 is said to be programmed with a logic "0". During the read operation, voltage values of 0 Volt, 3 Volts, 5 Volts and 0 Volt are applied to first control gate 86, second control gate 88, drain 78 and source 76, respectively. At the same time, voltage values of 5 Volts, 0 Volt, 5 Volts, and 0 Volt are applied to first control gate, second control gate, drain and source, respectively, of other non-addressed cells. With a coupling efficiencies of approximately 20% and 50% between floating gate 90 and each of the control gates 86 and 88, respectively, floating gate 90 of the selected memory cell 70 is capacitively coupled with about 1.5 Volts. Thus, if MOS transistor 82 is previously programmed with a +2 Volt threshold voltage, 1.5 Volts coupled in floating gate 90 is insufficient to turn channel 80 on. No current can flow and a logic "1" is read, for example. Conversely, if MOS transistor 82 is previously programmed with a threshold voltage of -2 Volts, 1.5 Volts in floating gate 90 is sufficient to turn channel 80 on. Current flows from drain 78 to source 76 and a logic "0" is read, for example.

Fig. 28 shows a memory array of memory cells 70 arranged in a matrix of rows and columns. As is shown, the source 38 and drain 40 of each of the adjacent cells are connected together. First control gates 86 of each of memory cells 70 in a row are electrically connected together to form X-control traces 71A-71D. Second control gates 88 of each of memory cells 70 in a column are electrically connected together to form Y-control traces 73A-73D. Each of the memory cell in the array can be addressed by the simultaneous energization of the selected X-control and Y- control traces.

Figs. 29-30 show a variation in design with respect to the memory cell 70 shown in Figs. 23-25. Memory cell 92 comprises a floating gate 94 having a first segment 94A, a second segment 94B and a third segment 94C. N-type diffusion region 96 serves an electrical bridge between source 98 and drain 100 during the read operation.

Figs. 31-34 shows a fourth embodiment of the present invention. The memory cell of this embodiment is signified by reference numeral 102 and is characterized by a floating gate over-riding two control gates. As with the previous embodiment, memory cell 102 is capable of being programmed with a negative threshold voltage and is also ideal for applications where a high density array is required.

Referring now to Figs. 31-36, in this embodiment, formed in a P-type semiconductor substrate 110, for example, are N-type source 106 and drain 108. A channel 104 is formed between source 106 and drain 108 (Fig. 35) . Source 106, drain 108 and channel 104 constitutes a MOS transistor 112. A floating gate 120 is dielectrically disposed atop channel 104. Floating gate 120 comprises a first segment 120A, a second segment 120B and a third segment 120C. Second segment 120B and third segment 120C of floating gate 120 over-ride first and third control gates 114 and 116, respectively, as shown in Fig. 32. First and third control gates 114 and 116 are electrically shorted together. Atop floating gate 120 is a second control gate 118. Cell to cell isolations are accomplished by P-type isolation regions 115.

The three operations of memory cell 102 is summarized in a table shown in Fig. 36. As with the previous cases, there are a number of similarities between this embodiment and the previous embodiments. For a concise and clear illustration, only the differences are high-lighted.

In this embodiment, the negative logic convention is used. When the threshold voltage Vth of MOS transistor 112 is programmed to 2 Volts, memory cell 102 is said to be programmed with a logic "1". Conversely, when the threshold voltage Vth of MOS transistor 112 is programmed to -2 Volts, memory cell 102 is said to be programmed with a logic "0". During the read operation, voltage values of 0 Volt, 0 Volts, 5 Volts and 0 Volt are applied to first control gate 114 (also electrically tied to third control gate 116) , second control gate 118, drain 108 and source 106, respectively. At the same time, voltage values of 0 Volt, 5 Volts, 5 Volts, and 0 Volt are applied to first control gate (also electrically shorted to third control gate) , second control gate, drain and source, respectively, of other non-addressed cells. With first control gate 114 and second control gate 118 at -0 Volt, floating gate 120 of the selected memory cell 102 is capacitively coupled with 0 Volt. Thus, if MOS transistor 112 is previously programmed with a 2 Volt threshold voltage, 0 Volt coupled in floating gate 120 is insufficient to turn channel 104 on. No current can flow and a logic "1" is read, for example. Conversely, if MOS transistor 112 is previously programmed with a threshold voltage of -2 Volts, 0 Volt in floating gate 120 is sufficient to turn channel 104 on. Current flows from drain 114 to source 106 and a logic "0" is read, for example.

Fig. 37 shows a memory array of memory cells 102 arranged in a matrix of rows and columns. The X-control traces 81A-81D comprise of second control gates 118 of each of the memory cells in a row connected together. In a similar manner, the Y-control trace 83A-83D comprise of first and third control gates 114 and 116 of each of the memory cells in a column connected together. Each of the memory cell in the array can be addressed by the simultaneous energization of the selected X-control and Y- control traces.

Fig. 38 shows a variation in design with respect to the memory cell 102 shown in Figs. 31-34. The main differences are that field oxide regions 128 in memory cell 126 replace P-type isolation regions 115 in memory cell 102 as the isolations among cells, and first and third control traces 114 and 116 overlies field oxide regions 128. The rest of the structure and the modes of operation of memory cell 126 are substantially similar to the memory cell 102. Fig. 39 shows another variation in design with respect to memory cell 126 shown in Fig. 38. The memory cell, signified by reference numeral 130, comprises floating gate 120 over-riding only one control gate 116. As with the memory cell shown in Fig. 38, field oxide regions 128 are used as isolations between cells. Again, operations of memory cell 130 are substantially similar to memory cells 102 and 126 and need no further repetitions in illustration. The process of fabrication of memory cells 70 and 102 are substantially the same as the previous embodiments with only minor modifications. For example, in the fabrication of memory cell 70, diffusion region 74 must be implanted before the formation first control trace 86. In the making of memory cell 102, photolithographic masks need to be slightly altered such that first and third control traces 116 and 114 can be formed simultaneously. The minor modifications in technique are well known in the art and therefore need no further illustrations. While the present invention has been shown and de¬ scribed with reference to preferred embodiments thereof, it will be understood by those skilled in the art that these and other changes in form and detail may be made therein without departing from the scope and spirit of the invention as defined by the appended claims.

Claims

Claims What is claimed is:

1. A non-volatile semiconductor memory cell formed in a semiconductor substrate having a source, a drain spaced from the source, and a channel disposed between said drain and the source, wherein the improvement comprising: a first control gate dielectrically disposed atop a first portion of the channel; a second control gate dielectrically disposed atop said first control gate; and a floating gate having a first segment thereof diecectrically disposed between said first and second control gates, and a second segment thereof dielectrically disposed atop a second portion of the channel; wherein when said first and second control gates are substantially simultaneously energized to a first set of potential values, electrical charges are couplingly induced in said floating gate from the substrate, allowing said floating gate to couplingly vary the conductivity of the channel after the de-energization of said control gates, and wherein when said first and second control gates are substantially simultaneously energized to a second set of potential values, electrical charges are couplingly induced out of said floating gate to the substrate, allowing said floating gate to couplingly vary the conductivity of the channel after the de-energization of said control traces.

2. The non-volatile semiconductor memory cell as set forth in claim 1 wherein said first and second control gates being elongated in shape and are dielectrically disposed atop the semiconductor substrate substantially perpendicular to each other.

3. The non-volatile memory cell as set forth in claim 1 wherein said floating gate further comprising a third segment thereof dielectrically overlying at least a portion of the source.

4. The non-volatile memory cell as set forth in claim 3 wherein said second control gate further comprising a second portion thereof dielectrically disposed atop a third portion of the channel.

5. The non-volatile memory cell as set forth in claim 1 wherein said second control gate further comprising a second portion thereof dielectrically disposed atop a third portion of the channel.

6. The non-volatile memory cell as set forth in claim 1 wherein said first control gate being dielectrically disposed atop a doped semiconductor region formed in the channel.

7. The non-volatile memory cell as set forth in claim 6 where said floating gate further comprising a third segment thereof dielectrically disposed atop a third portion of the channel.

8. The non-volatile memory cell as set forth in claim 1 wherein said first control gate being disposed atop an isolation region formed in the semiconductor substrate adjacent the channel.

9. The non-volatile memory cell as set forth in claim 1 further comprising a third control gate dielectrically disposed atop the semiconductor substrate substantially parallel to said first control gate, each of said first control gate and said third control gate being disposed atop an isolation region formed in the semiconductor substrate adjacent the channel, and wherein said floating gate further including a third segment thereof dielectrically disposed atop said third control gate.

10. The non-volatile memory cell as set forth in claim 8 or claim 9 wherein said isolation region is a field oxide region or a doped semiconductor region.

11. The non-volatile memory cell as set forth in any of claims 1-7 wherein when said first and second control gates are energized to said first set of potential values, electrical charges are couplingly induced in said floating gate from the substrate by the source side injection effect, and wherein when said first and second control gates are energized to said second set of potential values, electrical charges are couplingly induced out of said floating gate to the substrate by the Fowler-Nordheim tunneling effect.

12. The non-volatile memory cell as set forth in any of claims 1-9 wherein when said first and second control gates are energized to said first set of potential values, electrical charges are couplingly induced in said floating gate from the substrate by the hot electron injection effect, and wherein when said first and second control gates are energized to said second set of potential values, electrical charges are couplingly induced out of said floating gate to the substrate by the Fowler-Nordheim tunneling effect.

13. The non-volatile memory cell as set forth in any of claims 1-9 wherein when said first and second control gates are energized to said first set of potential values. electrical charges are couplingly induced in said floating gate from the substrate by the Fowler-Nordheim tunneling effect, and wherein when said first and second control gates are energized to said second set of potential values, electrical charges are couplingly inducted out of said floating gate to the substrate by the Fowler-Nordheim tunneling effect.

14. A memory cell array formed in a semiconductor substrate including a plurality of non-volatile memory cells, each of the non-volatile memory cell comprising: a source formed in the semiconductor substrate; a drain formed in the semiconductor substrate spaced from said source; a channel disposed between said drain and said source; a first control gate dielectrically disposed atop said channel; a second control gate dielectrically disposed atop said first control trace and substantially perpendicular therewith; and a floating gate dielectrically disposed between said first and second control gates; wherein said plurality of non-volatile memory cells being disposed in the semiconductor substrate in a matrix of rows and columns with each of said second control gates in each of said rows of said matrix being electrically connected together, and with each of said first control gates of in each of said columns being electrically connected together, thereby allowing each of said non¬ volatile memory cells to be selectively programmed when the selected first and second control gates are substantially simultaneously energized to a first set of potential values, and thereby allowing each of said non-volatile memory cells to be selectively de-programmed when the selected first and second control gates are substantially simultaneously energized to a second set of potential values.

15. A method of forming a non-volatile memory cell of the type in which tunneling of charges occurs between a semiconductor substrate and a floating gate disposed atop the semiconductor substrate, the improvement comprising the steps of: forming a first control gate dielectrically overlying the substrate; forming the floating gate dielectrically overlying said first control gate; and forming a second control gate dielectrically overlying said floating gate and disposing said second control gate substantially perpendicular to said first control gate.

16. The method of forming a non-volatile memory cell as set forth in claim 15 further comprising the step of forming a source and a drain in the semiconductor substrate before the step of forming said second control gate.