Búsqueda Imágenes Maps Play YouTube Noticias Gmail Drive Más »
Iniciar sesión
Usuarios de lectores de pantalla: deben hacer clic en este enlace para utilizar el modo de accesibilidad. Este modo tiene las mismas funciones esenciales pero funciona mejor con el lector.

Patentes

  1. Búsqueda avanzada de patentes
Número de publicaciónWO1995012144 A1
Tipo de publicaciónSolicitud
Número de solicitudPCT/CA1993/000468
Fecha de publicación4 May 1995
Fecha de presentación29 Oct 1993
Fecha de prioridad29 Oct 1993
Número de publicaciónPCT/1993/468, PCT/CA/1993/000468, PCT/CA/1993/00468, PCT/CA/93/000468, PCT/CA/93/00468, PCT/CA1993/000468, PCT/CA1993/00468, PCT/CA1993000468, PCT/CA199300468, PCT/CA93/000468, PCT/CA93/00468, PCT/CA93000468, PCT/CA9300468, WO 1995/012144 A1, WO 1995012144 A1, WO 1995012144A1, WO 9512144 A1, WO 9512144A1, WO-A1-1995012144, WO-A1-9512144, WO1995/012144A1, WO1995012144 A1, WO1995012144A1, WO9512144 A1, WO9512144A1
InventoresNigel M. Coe
SolicitanteLitton Systems Canada Limited
Exportar citaBiBTeX, EndNote, RefMan
Enlaces externos:  Patentscope, Espacenet
Repairable bus structure for amlcd array
WO 1995012144 A1
Resumen
In an AMLCD array comprising a plurality of thin film transistors (1) having drain electrodes, gate electrodes and source electrodes, a plurality of transparent pixel output pads connected to respective ones of the drain electrodes, a plurality of gate buses (4) connected to respective ones of the gate electrodes, and a plurality of source buses (6) connected to respective ones of the source electrodes, the improvement comprising a plurality of shunt circuits (12) connected to at least one of the plurality of source buses (6) and gate buses (4) for bypassing respective ones of the thin film transistors (1) in the event of a short circuit between any of the source buses and the gate buses.
Reclamaciones  (El texto procesado por OCR puede contener errores)
I CLAIM:
1. In an AMLCD array comprising a plurality of thin film transistors having drain electrodes, gate electrodes and source electrodes, a plurality of transparent pixel output pads connected to respective ones of said drain electrodes, a plurality of gate buses connected to respective ones of said gate electrodes, and a plurality of source buses connected to respective ones of said source electrodes, the improvement comprising a plurality of shunt circuits connected to at least one of said plurality of source buses and gate buses for bypassing respective ones of said thin film transistors in the event of a short circuit between any of said source buses and said gate buses.
2. The improvement of claim 1, wherein said plurality of shunt circuits are connected to said plurality of source buses across each of said thin film transistors.
3. The improvement of claim 1, wherein said plurality of shunt circuits are connected to said plurality of gate buses across each of said thin film transistors.
4. The improvement of claim 1, wherein each of said shunt circuits comprises a generally D-shaped track of conductive material extending around a respective one of said thin film transistors.
5. The improvement of claim 1, wherein each of said shunt circuits is collinear with a respective one of said source buses, and a respective one of said thin film transistors is disposed adjacent said shunt circuits.
6. An AMLCD array, comprising: a) a plurality of thin film transistors each having a drain electrode, a gate electrode and a source electrode; b) a plurality of transparent pixel output pads connected to respective ones of said thin film transistors via each said drain electrode; c) a plurality of gate buses connected to respective ones of said thin film transistors via each said gate electrode; d) a plurality of source buses connected to respective ones of said thin film transistors via each said source electrode; and e) a plurality of shunt circuits connected to at least one of said plurality of source buses and gate buses for bypassing respective ones of said thin film transistors in the event of a short circuit between any of said source buses and said gate buses.
7. The improvement of claim 6, wherein said plurality of shunt circuits are connected to said plurality of source buses across each of said thin film transistors.
8. The improvement of claim 6, wherein said plurality of shunt circuits are connected to said plurality of gate buses across each of said thin film transistors.
9. The improvement of claim 6, wherein each of said shunt circuits comprises a generally D-shaped track of conductive material extending around a respective one of said thin film transistors.
10. The improvement of claim 6, wherein each of said shunt circuits is collinear with a respective one of said source buses, and a respective one of said thin film transistors is disposed adjacent said shunt circuits.
Descripción  (El texto procesado por OCR puede contener errores)

REPAIRABLE BUS STRUCTURE FOR AMLCD ARRAY

Field of the Invention

This invention relates in general to Active Matrix Liquid Crystal Displays (AMLCDs) , and more particularly to a repairable bus structure for AMLCD arrays. Background of the Invention

Thin film transistor-based active matrix liquid crystal displays are now in production at a number of large electronics companies. These displays, used for high resolution applications such as avionics as well as low resolution applications such as in personal televisions and lap-top computer screens, present video information by modulating light intensity on a pixel-by- pixel basis. Source and gate buses are arranged to form a rectangular grid of pixels. Each pixel contains a Thin Film Transistor (TFT) switch which uses amorphous silicon or cadmium selenide as the semiconductor, and which has a drain electrode connected to a pixel output pad in the form of a transparent electrode. By scanning the gate bus, which functions as a select line, data may be written to a given pixel through the associated TFT onto the transparent electrode. The voltage appearing on the transparent electrode modulates light via the LCD effect. Since the metal gate and source buses are separated only by a gate insulator, gate-to-source electrical short circuits are possible if the gate insulator breaks down or is damaged at the intersection of the two buses. According to prior art techniques, in order to repair such a condition, one or the other of the metal buses must be cut on both sides of the short circuit, which leaves a discontinuous bus structure. In order to repair this bus structure, a wire or other circuit path must connect the two opposite ends of the bus together from outside of the array since the array is encapsulated. As such, only one repair can be effected per bus. Summary of The Invention

According to the present invention, a circuit bypass or shunt is provided at each bus intersection or crossover point in the pixel array of an AMLCD. Thus, according to the invention, an alternate circuit path is present at each crossover. More importantly, the bus shunts according to the present invention are accessible through the transparent rear side of the array, without obstruction caused by the black light shield layer or the colour filter of the AMLCD.

Brief Description of the Drawings

A detailed description of the preferred embodiment and of the prior art is provided herein below, with reference to the following drawings, in which: Figure 1 is a plan view showing a prior art TFT array for AMLCD;

Figure 2 is a plan view of a shunt repairable AMLCD array according to a preferred embodiment of the present invention; Figure 3 is a rear view of a repairable shunt TFT according to the preferred embodiment;

Figure 4 is a plan view of a shunt repairable AMLCD array according to an alternative embodiment of the present invention; and Figure 5 is a rear view of a repairable shunt TFT according to the alternative embodiment of Figure 4. Detailed Description of the Preferred Embodiment and Prior Art

Figure 1 shows the structure of an AMLCD incorporating a plurality of inverted TFTs 1 arranged on a transparent insulating substrate, such as glass, in the form of a matrix. Gate electrodes of each TFT 1 are commonly connected though gate buses 4 so as to form select lines of the array. Source electrodes of each TFT 1 are commonly connected to source buses 6 to form data lines of the array. A drain electrode of each TFT 1 is connected to an output pad comprising a transparent electrode 8 which is formed as a rectangular pixel output pad between the gate buses 4 and source buses 6 of the array. A layer of semiconductor material overlaps the source and drain electrodes and forms a thin-film semiconductor channel there between.

As discussed above, in the event of a short circuit between the gate bus 4 and source bus 6, one of the buses must be broken on both sides of the affected TFT 1, and a wire or other circuit path must be connected between opposite ends of the bus, outside of the array, in order to preserve functioning of the buses.

Turning to Figures 2 and 3, according to the present invention each source bus 6 incorporates a plurality of circuit shunts 12 extending around each TFT 1. As shown in Figure 3, the shunt 12 may be accessed from beneath the AMLCD array, from either side of the underlying gate bus 4. Thus, in the event of an accidental short circuit, the source bus 6 may be broken on both sides of the affected TFT, by directing a low power laser (eg. an excimer laser) through the transparent substrate and then focussing the light on the portions of the bus to be broken. The cross-sectional dimensions of the laser light may be adjusted using a suitable aperture in order to precisely illuminate the bus to be broken (eg. a 10 micron trace) , while not illuminating other parts of the circuit. Appropriate backlighting may be employed on the laser platform to which the circuit is mounted to ensure proper visibility of the circuit parts, in a well known manner. The laser light melts the metal bus where the light is focussed and the shunt 12 provides an automatic alternate circuit path around the TFT 1, without any requirement for additional wires, etc.

With reference to Figures 4 and 5, an alternative embodiment of the invention is shown in which the shunt 12' is collinear with the source bus 6, instead of traversing a D-shaped path as in the preferred embodiment of Figures 2 and 3. However, in the embodiment of Figures 4 and 5, the principal circuit path of source bus 6 to the TFT 1 is shown as being generally D-shaped, although any suitable shape of shunt may be utilized.

The shunt repairable AMLCD of the present invention may be fabricated using well known methodology. In fact the only departure from standard AMLCD fabrication techniques is that the masks for patterning the source bus 6 and transparent electrode 8 must be appropriately shaped to create the shunt 12 (Figure 2 and 3) or shunt 12*' (Figures 4 and 5) when deposited on the gate oxide. An AMLCD array constructed in accordance with the present invention may suffer more than one short circuit failure on any given bus, and still be able to function with the remaining TFTs, as contrasted with the prior art.

Other embodiments and variations of the invention are possible. For example, although the embodiments of Figures 2 - 5 show the shunt 12 as forming part of the source bus 6, it is contemplated that the shunt may advantageously incorporated into the gate bus instead of, or in the case of large displays in addition to, the shunt forming part of the source bus 6. This and all other such modifications and embodiments are believed to be within the sphere and scope of the claims appended hereto.

Citas de patentes
Patente citada Fecha de presentación Fecha de publicación Solicitante Título
EP0200138A2 *21 Abr 19865 Nov 1986Asahi Glass Company Ltd.Thin film transistor, method of repairing the thin film transistor and displaying apparatus having the thin film transistor
FR2649523A1 * Título no disponible
JPH0496023A * Título no disponible
JPS63221325A * Título no disponible
US4853755 *17 Mar 19881 Ago 1989Alps Electric Co., Ltd.Method for manufacturing a thin-film transistor array and a thin-film transistor array manufactured by the method
Otras citas
Referencia
1 *M. YAMANO ET AL.: "The 5-Inch Size Full Color Liquid Crystal Television Addressed by Amorphous Silicon Thin Film Transistors", IEEE TRANSACTIONS ON CONSUMER ELECTRONICS, vol. 31, no. 1, February 1985 (1985-02-01), NEW YORK, US, pages 39 - 46, XP011158360
2 *PATENT ABSTRACTS OF JAPAN vol. 13, no. 17 (P - 813)<3365> 17 January 1989 (1989-01-17)
3 *PATENT ABSTRACTS OF JAPAN vol. 16, no. 327 (P - 1387) 16 July 1992 (1992-07-16)
Citada por
Patente citante Fecha de presentación Fecha de publicación Solicitante Título
EP1882978A1 *24 Jul 200730 Ene 2008Samsung Electronics Co., Ltd.Liquid crystal display
Clasificaciones
Clasificación internacionalG02F1/1362, G02F1/13
Clasificación cooperativaG02F2001/136268, G02F1/136259, G02F1/1309, G02F2001/13629
Clasificación europeaG02F1/13B4
Eventos legales
FechaCódigoEventoDescripción
4 May 1995AKDesignated states
Kind code of ref document: A1
Designated state(s): CA JP KR US
29 Ago 1996NENPNon-entry into the national phase in:
Ref country code: CA