WO1995018407A1

WO1995018407A1 - Solid state memory system

Info

Publication number: WO1995018407A1
Application number: PCT/GB1994/002825
Authority: WO
Inventors: Alexander Roger Deas
Original assignee: Memory Corporation Plc
Priority date: 1993-12-24
Filing date: 1994-12-28
Publication date: 1995-07-06
Also published as: GB9326499D0; AU1322895A

Abstract

A storage device that connects to a standard computer system and communicates with a computer system bus, being capable of receiving, storing and retrieving data intended for a magnetic disk drive; the storage device comprising: a main memory; a cache memory; block transfer buffer means to store 512 bytes of data; interface means to receive and store address, data and control information from computer system; look-up table means for storing one physical block address corresponding to each address sent by computer system, and to indicate whether the physical block address is for cache or main memory; additional memory means for storing information on the addresses of cache and also main memory which are unused and suitable for writing to; control means to access a record in look-up table means using address sent by computer system, and to determine a physical block address corresponding to standard address format.

Description

SOLID STATE MEMORY SYSTEM
The invention relates to a solid state memory system which is applicable in particular, though not exclusively, to non byte-erasable EEPROM technologies.

Many common memory storage devices are based on rotating storage media such as the magnetic disk drive. The magnetic disk drive contains a number of thin platters which are stacked in a vertical manner and rotate about a spindle.

Each platter consists of a metal, glass or plastics e. g. polycarbonate disk which is covered on both sides with magnetic recording material. A number of concentric tracks are located on each side of the platter, with each track organised into sectors. A sector is the smallest unit that can be written to or read from.

To read from or write to the hard disk, the platters within the disk must be rotated and the arms, which usually straddle the platters, must be moved to the correct location. The hard disk system uses a comparatively large amount of power because of the physical movement involved, i. e. the need to rotate the platters and move the arms.

This consideration is of particular importance when hard disks are to be used in portable computers. Portable computers rely on batteries to provide the power to actuate the disk drive; however, these batteries only last a short time if the disk drive is used frequently. For this reason many portable computers have means for stopping the disk drive rotating if it has not been used for a certain period of time, for example thirty seconds. Another disadvantage associated with the hard disk is the comparatively slow access time for reading or writing data. A further disadvantage associated with disk drive units is that they are not robust because they have moving parts which can be jarred; thus there is the possibility of a hard disk crash if the drive unit is knocked. Hard disk drives are also comparatively heavy.

To overcome these disadvantages, solid state memory devices are sometimes used as storage media. Solid state devices have the advantages of light weight, low power consumption, high reliability, robustness, and high performance.

If volatile memory is used as the solid state media, however, power must be applied to the cells more or less continuously to ensure that data is not lost once the computer is turned off. Non-volatile memory can be used, but the disadvantage associated with some types of nonvolatile memory is that individual bits or bytes cannot have their logic values changed in isolation from the neighbouring bits or bytes. In other words, comparatively large areas of the memory need to be erased at a time.

Those types of non-volatile memory which are bit or byte erasable are larger than the non-byte erasable type; therefore, they provide lower memory capacity for the same physical area. Another disadvantage associated with nonvolatile memory is that it tends to take longer to write to non-volatile memory than to volatile memory, and a particularly significant problem is the slow erasing of some EEPROM, in particular flash EPROM, memories, coupled to the further problem of limited life in the sense of only being able to withstand a limited number of erasure cycles.

Much computer software and hardware currently available is designed to work only with hard disk drives. Therefore, it is important to be able to provide a memory system which appears to be a hard disk, even though it is actually a solid state memory device. One problem in making Flash
EPROM memory appear like a hard disk is that Flash memory is normally manufactured with a more or less large predetermined minimum erasable data block size, whereas a hard disk stores data in relatively small sectors of predetermined size, typically 512 bytes.

The prior art includes references to the idea of having a solid state memory which can take the place of a hard disk.

However, these systems rely on the Flash memory having the correct sector size, hence the designs are constrained to use Flash memory of that sector size, i. e. Flash memory customized for the application. For emulating a hard disk, a Flash memory system would be obliged to use a sector size equal to that of the disk (typically 512 bytes). EP392895A claims a device which emulates a hard disk, by using an
EEPROM with a minimum erasable block size corresponding to a logical hard disk sector size of 512 bytes.

It is an object of the present invention to avoid or minimize one or more of the above disadvantages. It is a further object to provide a memory system that performs the necessary memory management and converts addresses which are intended for a hard disk (Logical Disk Sector Address also sometimes referred to as Logical Block Address) to a suitable format for use with a solid state memory (Physical
Address).

According to the present invention there is provided a solid state mass data storage system for connection to an input/output connection interface of a host computer system, the connection interface being configured for coupling to a disk drive and the storage system being arranged to emulate such a disk drive, the system comprising: a primary memory arranged to store data in minimum erasable size data blocks which are larger than the sectors of the emulated disk drive; a cache arranged for storing data temporarily and having a storage capacity of at least one said minimum erasable size data block; memory mapping means for storing mapping data for mapping logical disk sector addresses of the emulated disk drive to respective physical addresses in the primary memory or the cache;

and host computer interface means for coupling to the host computer input/output connection interface and having control means arranged for determining from the memory mapping means in the case of receipt of read instructions from the host computer, the physical address corresponding to a received logical disk sector address and enabling the host computer to access data stored at that physical address, and, in the case of receipt of write instructions from the host computer, for writing received data having a given logical address to the cache or the primary memory, according to predetermined memory management criteria, at an existing corresponding physical address or, if required by said criteria, at a new physical address and updating the memory mapping means to indicate the new corresponding physical address,

the control means being further arranged for copying selectively at least one said minimum erasable size data block to the cache from the primary memory and erasing selectively that data block from the primary memory, in accordance with said predetermined memory management criteria and updating the memory mapping means accordingly, to allow subsequent copying and remapping of data to be stored from said cache to said primary memory, as and when required.

An advantage of the present invention is that it enables a solid state memory card system based on a Flash memory of relatively large minimum erasable data block size to replace a hard disk, without any loss of functionality or performance, and it gives the added benefits associated with solid state memory, namely: low power consumption, low weight, high reliability and sturdiness.

Embodiments of the present invention may provide a storage device that connects to a standard computer system in a manner to communicate with a computer system bus, said storage device being capable of receiving and storing data intended for a magnetic disk drive and also being capable of retrieving said data in response to a read request on said system bus.

A prefered embodiment of the present invention comprises a main memory containing one or more FLASH EPROMs, each of said FLASH EPROMs containing a plurality of minimum erasable size data blocks containing a large plurality of addressable sectors; a cache memory which can be written to faster than said main memory; data transfer buffer means to store at least one sector sized data segment; interface means to receive and store address, data and control information from said standard computer system; look-up table means for storing one physical sector address corresponding to each logical disk sector address sent by said standard computer system, and to indicate whether said physical address is for said cache memory or said main memory;

additional memory means for storing information on the addresses of said cache memory which are unused and suitable for writing to, and for storing memory management information including information on the addresses of said main memory which are unused and suitable for writing to; control means to determine when said interface means has received a read or write request from said standard computer system, to access a record in said look-up table means using the logical disk sector address sent by said standard computer system, to determine a physical address corresponding to said standard address format, in the case when a read command is requested to ensure that the appropriate block of data from said main memory or said cache memory is contained in the block transfer buffer means,

and when a write command is requested to ensure that the appropriate data is transferred from said interface means to said data transfer buffer means then to said cache memory, and to update the relevant entries in said additional memory means.

For a better understanding of the present invention and to show how the same may be carried into effect, reference will now be made, by way of example, without loss of generality to the accompanying drawings, in which:
Figure 1 shows a block diagram of a solid state memory system arranged to emulate a hard disk drive; and
Figure 2 shows a memory map for a cache device of the system of Figure 1.

Figure 1 shows in block diagram form: a Disk Interface 1 that conforms to the disk interface standard which is being emulated by the memory system (e. g. IDE or SCSI), a Data
Transfer Buffer 2, a Microcontroller 3, a Cache device 4 containing the look-up tables and a cache or temporary data store, a Flash EPROM semiconductor memory array 5, an
Address Bus 6 between the host processor and the memory system, a bi-directional Data Bus 7 between the host processor and the memory system, a Control Bus 8 between the host processor and the memory system, a second Address Bus 9 between the Disk Interface Block 1 and the Data Transfer
Buffer 2, a second bi-directional Data Bus 10 between the
Disk Interface Block 1 and the Data Transfer Buffer 2, a second Control Bus 11 between the Disk Interface Block 1 and the Data Transfer Buffer 2,

a third Address Bus 12 from the
Microcontroller 3 which goes to the Disk Interface 1, the
Cache device 4, and Flash Memory Array 5, a third bidirectional Data Bus 13 from the Microcontroller 3 which goes to the Disk Interface 1, the Data Transfer Buffer 2, the Cache device 4 and the Flash Memory Array 5, and a third Control Bus 14 from the Microcontroller 3 which goes to the Disk Interface 1, the Data Transfer Buffer 2, the
Cahce device 4 and Flash Memory Array 5. The Disk
Interface 1, the Data Transfer Buffer 2, and the
Microcontroller 3 collectively make the Interface and
Control Block (ICB) 15 which may conveniently be implemented as a single ASIC (Application Specific Inteprated Circuit).

The Microcontroller 3 and software used therein could be replaced by firm-ware in the form a state-machine which performs the functions of the Microcontroller, although the state-machine may perform some tasks concurrently whereas the Microcontroller performs tasks sequentially.

The Disk Interface 1 is responsible for communicating directly with the host processor. For this function it has numerous registers (depending on the disk standard being emulated) some of which will contain unique logical disk sector address information in Cylinder, Head, and Sector (CHS) addressing mode or Logical Block Address (LBAD) mode which is an option for ATA standard. It will contain mode control registers to specify which addressing mode will be used, e. g. CHS or Logical Block Address. It may convert this logical disk sector access address to a form suitable for use with the look-up table stored within the Cache device 4. The Logical Block Address refers to the addressing mode of the drive as being by linear mapping of sectors on the drive. The ATA standard defines an integrated bus interface between disk drives and host processors.

The Disk Interface 1 will contain latches to store the address and bi-directional data information and also control decode circuitry. On receipt of addressing information and/or a read or write signal from the host processor the
Disk Interface will inform the microcontroller 3 of the read or write request.

The Data Transfer Buffer 2 may be a dual ported memory, or it may be a memory with extra logic to make it act as a dual ported memory, or it may be a bi-directional FIFO (First In
First Out) buffer arrangement. For the FIFO implementation the Address Bus 9 between the Disk interface 1 and Data
Transfer Buffer 2 would not be necessary. The Data Transfer
Buffer 2 holds data from at least one sector of main memory (typically 512 bytes). Any data sent from or to the host goes via the Data Transfer Buffer 2.

The Microcontroller 3 is programmed to perform the mapping algorithm and other associated tasks. It responds to control signals from the Disk Interface 1 to transfer data between the various buffers, memories, and stores in the system as necessary to effect read and write commands initiated by the host.

The Cache device 4 may be an array of perfect working memory devices or it may be an array of partially working devices with the necessary logic and spare memory to provide full memory function. This memory contains information on the physical address or location in Flash memory that corresponds to the logical disk sector address (including cylinder and head information as appropriate) generated by the host processor. For every possible logical disk sector address combination there exists in the look-up table a corresponding physical address in the Flash memory, or possibly, during use of the storage system for reading or writing, in the cache of the Cache device 4.

The Flash memory array 5 may be an array of perfect working memory devices or it may be an array of partially working devices.

The host processor interface comprises: a standard computer
Address Bus 6 which is used to determine which register within the standard disk interface is being accessed; a standard bi-directional Data Bus 7 which is used to transfer information between the interface and the host; and a standard Control Bus 8 which is used to determine, among other things, the direction and speed of the information interchange.

The Disk Interface to Data Transfer Buffer interface consists of an Address Bus 9, a bi-directional Data Bus 10, and a Control Bus 11, which is used to determine the direction of the information interchange.

The Microcontroller interface goes between the
Microcontroller 3 and the Disk Interface 1, the Data
Transfer Buffer 2, the Cache device 4, and the Flash Memory
Array 5. It comprises an Address Bus 12, a bi-directional
Data Bus 13, and a Control Bus 14 that determines the direction of the information interchange and which one of the Disk Interface, the Data Transfer Buffer, the Cache device, or the Flash Memory Array is being accessed.

The Cache device 4 is a memory device containing a relatively large temporary store Cache 22 (see Fig. 2) for data due to be written to the Flash Memory Array 5 although it is quite possible that data stored in the Cache may be changed or even deleted entirely by the host before the memory management criteria have provided for rewriting of that data to the Flash Memory. The Cache device 4 could be volatile memory, such as SRAM, which can be written to, in some cases, much faster than the Flash EPROM main memory.

The cache device 4 also conveniently contains (as shown in
Fig. 2) mapping information which may be in the form of a look-up table containing logical disk sector addresses and current corresponding physical addresses (Logical Block
Attributes LBA) 20, as well as memory management information comprising a Buffer Free List (BFL) 16, a Ranked List of Age (RLA) 17, a Flash Free List (FFL) 18, Physical Block
Attributes (PBA) 20, and Erase-block Attributes (EBA) 21.

In more detail:
The Buffer Free List 16 contains a list of all Cache memory sectors that are not currently being used. This list may be ranked in order of the physical address of the sectors or it may be in the form of a linked list. If it is in the form of a linked list then together with each address there is a pointer which points to the next free sectors.

The Ranked List of Age 17 is a list of currently used sectors of Cache memory which are ordered with respect to the last time that the sector was accessed.

The Flash Free List 18 is a list of all Flash memory sectors that are not currently being used and are free to be written to. This list may be an ordered list or it may be a linked list.

The Logical Block Attributes 19 contains information required for mapping Logical Disk sector Address accesses to current Physical Address accesses. The information for each Logical disk sector address is the Physical Address (PBAD) and an InBuffer flag. The InBuffer flag indicates whether a sector accessed is in the cache 4 or in Flash memory 5.

The Physical Block Attributes 20 contains two flags for each sector of Flash memory that is not in the Flash Free List.

These flags are Used and Erased. Used indicates whether or not the sector holds valid data. Erased indicates whether or not a previously used sector has been written to all zeros.

The Erase-block Attributes 21 counts how many times each minimum erasable size data block has been erased. The minimum erasible size data block is determined in the manufacture of the EEPROM and can have any convenient value.

In general it would be at least 100K bytes, though considerably larger sizes e. g. 1M byte may be used with suitable memory management. It will of course be appreciated that the look-up table and at least some of the memory management information require to be stored in nonvolatile memory, conveniently in part of the EEPROM 5 itself before powering-down of the storage system (unless the cache device is battery backed) and read into the cache device 4 upon powering-up of the storage system under the control of the microcontroller 3.

The operation of this embodiment of the design will now be described in detail, without loss of generality.

A host processor, for example a microprocessor or
Microcontroller, (not shown) requests either a read from or write to the disk which is being emulated by the data storage system. The host processor uses the communications interface protocol specified by the disk standard being emulated. Typical read and write operations shall now be described in detail.

During the read operation the host processor stores the logical disk sector address of the sector to be read, in the corresponding registers of the Disk Interface. The host processor then writes a read command to the ICB 15. The
Microcontroller 3 in the ICB 15 responds to this command by performing the following tasks:
I. it reads the logical disk sector address from the disk interface registers 1
II. it searches the look-up table 19 in the cache device 4 for this address
III. it reads the Physical Address associated with this logical address (this may point to either Flash memory 5 or' the cache 22 in the Cache device 4)
IV. it copies the 512 byte data segment from the Flash memory 5 or the Cache 4 and stores it in the Data Transfer
Buffer 2
V. it indicates to the host that the data is ready by writing to a disk interface register.

If a state-machine and hard logic is used to perform the functions of the Microcontroller 3 then the search in step (II) would be a hardware parallel access. Some or all of the above operations may be performed in parallel. The above operations may or may not be performed in the sequence shown.

During the write operation the host processor stores the logical disk Sector address (or the Logical Block Address) of the data segment to be written in the corresponding registers of the Interface and Control Block 15. The host processor then writes a write command to the ICB 15. The
Microcontroller 3 in the ICB 15 responds to this command by performing the following tasks:
I. it reads the logical disk sector address from the disk interface registers
II. it searches the look-up table 19 list for this address using a suitable algorithum programmed into the microcontroller 3 to obtain the corresponding physical address
III. it determines whether or not the current physical address is in the cache 22 and whether or not there is room in the cache 22. If the physical address is in the cache 22 then it carries out the sub tasks under task IV.

If the block is not in the cache 22 and there is not room in the cache 22 for the block, then it carries out the sub tasks under tasks V and VI. If the block is not in the cache 22 and there is room in the cache 22 for this block, then it carries out the sub tasks under task VI.

IVa. the sector containing old data in the cache 22 is overwritten with the new data
IVb. if the disk standard dictates, the host is notified that the operation is complet.

Va. the sector containing the oldest segment of data within the cache 22, according to the Ranked List of Age 17, is written to a free sector of Flash 5, according to the Flash
Free List 18
Vb. the Look-up table 19 is updated with the physical address of the Flash memory sector used in Va
Vc. the Ranked List of Age 17, the Flash Free List 18, and the Buffer Free List 16 are updated
VIa. the new data segement is written to a free sector of cache 22 according to the Buffer Free List 16
VIb. the Look-up table 19 is updated with the physical address of the sector in cache 22 which was written to in
VIa
VIc. the Buffer Free List 16 is updated.

When the memory system is not handling host initiated functions, such as read and write operations, the Interface
Control Block (ICB) Microcontroller 3 can perform certain supervisory actions.

The Microcontroller 3 notes the sectors that have been marked as unused and writes each cell to logic zero.

The Microcontroller 3 also counts unused sectors in a minimum erasable size data block to identify sparsely occupied blocks. If the number of unused sectors is above a predetermined threshold the following cleanup operation is carried out:
I. all used sectors are copied to another minimum erasable size data block
II. the sparsely occupied block is erased and all successfully erased blocks (i. e. those blocks which don't fail the verify test) are put on the Flash Free List 18
The normal Flash Erase process is desirably modified in the following manner to reduce stress on the Flash memory device. The cells of all unused sectors will be written to logic zero if the process has not already been carried out by the supervisory functions. This is in accordance with the normal Flash erase algorithm. The Erase-block command will be issued to the Flash memory device only once.

This differs from the normal Flash erase cycle. Any blocks containing cells that have not been erased will be written to logic zero and marked as unused but not free. The remaining blocks will be marked as free and added to the
Flash Free List 18.

In conventional systems if one cell failed to erase properly the entire device would be rendered unusable. However, due to the mapping system employed within this invention, if one cell failed to erase properly then only one sector of Flash (typically 512 bytes) would be unusable. The remainder of the device would be used as normal.

When a destination sector of Flash memory 5 is written to, its data is verified by comparing it to the original source data. If the destination and source data are not identical then the destination block is written to logic zero, marked as unused but not free, and another destination block is selected from the Flash Free List 18.

In conventional systems any cell which fails to write properly renders the entire device unusable. Due to the mapping system employed within this invention, only one block of Flash (typically 512 bytes) is unusable. The remainder of the device is used as normal.

Data in the temporary store 22 is transferred to the Flash memory array 5 as an instant action when there is no free space in the temporary store 22. Data may also be transferred from the Read/Write buffer 4 to Flash memory 5 by the supervisory mechanism when the free space in the temporary store 22 falls below a predetermined threshold.

In the former case, only one block of data will be written to the Flash memory array 5, freeing one block of memory in the Read/Write buffer 4. In the latter case, the data transfer would cease when the free space in the temporary store 22 exceeded another predetermined threshold (not necessarily the same predetermined threshold used to start the transfer procedure).

A PCMCIA form of the Memory System will normallyincorporate a battery backup which will perform one of two functions.

In one embodiment the battery will power the Read/Write buffer while the card is not connected to the host. In the other embodiment the battery will power the system for as long as it takes to write the information stored in the
Read/Write buffer to Flash Memory when the card is removed from the host.

It will be appreciated that various modifications may be made to the above embodiment within the scope of the present invention. Thus for example other criteria could be used in the memory management in addition to and/or instead of some of the criteria mentioned hereinbefore in accordance with general practice in the management of cache e. g. using data file size and/or random elements.

Claims

CLAIMS 1. A solid state mass data storage system for connection to an input/output connection interface of a host computer system, the connection interface being configured for coupling to a disk drive and the storage system being arranged to emulate such a disk drive, the system comprising: a primary memory arranged to store data in minimum erasable size data blocks which are larger than the sectors of the emulated disk drive; a cache arranged for storing data temporarily and having a storage capacity of at least one said minimum erasable size data block; memory mapping means for storing mapping data for mapping logical disk sector addresses of the emulated disk drive to respective physical addresses in the primary memory or the cache;

2. A storage system according to claim 1, wherein the memory mapping means is arranged to store a list of all sectors in the cache and the primary memory which are free, the control means being arranged, upon receipt of write instructions, to determine from the memory mapping means whether or not there is room in the cache to store a received data segment, and, in the case that there is room, to write the received data segment to a sector in the cache for temporary storage therein, and, in the case that there is not room, to make room by transferring a data segment currently stored in a sector in the cache to a free sector in the primary memory.

3. A storage system according to claim 2, wherein one or both of the cache and primary memory free sector lists are arranged as a linked list, each entry in the list including a pointer identifying the next free sector in the cache primary memory.

4. A storage system according to claim 2 or 3, wherein the memory mapping means is arranged to store a list of currently occupied sectors in the cache ordered according to the last time when the data in those sectors was accessed, the control means being arranged to transfer the data in that block which has not been accessed for the longest period in order to create free sectors in the cache.

5. A storage system according to any one of claims 2 to 4, wherein the control means is arranged to write the cells of all unused sectors of the primary memory to zero, to write any cells failing to erase to zero, and to list as unused but not free any blocks containing cells which do not erase to zero.

6. A storage device according to any one of the preceeding claims, wherein the control means is arranged to compare a sector of data in the primary memory with the corresponding sector in the cache following copying the data therein for the purpose of transfering its physical address to the primary memory and if a discrepancy exists, to list the sector in the primary memory as unused but not free and to transer the data from said cache sector to another sector in the primary memory.

7. A storage system according to any one of the preceeding claims, wherein the memory mapping means is arranged to store the number of times which each minimum erasable size data block of the primary memory has been erased, the control means being arranged to consult the memory mapping means in accordance with said predetermined memory management criteria in order to minimise the number of times which each minimum erasable size data block of the primary memory is erased.

8. A storage system according to any one of the preceeding claims, wherein each physical address stored in the memory mapping means comprises a root address and a flag which indicates whether the corresponding sector is stored in the cache or in the primary memory.

9. A storage system according to any one of the preceeding claims wherein said host computer interface means includes data transfer buffer means for holding data for writing pending re-mapping of the logical address thereof to a corresponding physical address, and, where required, remapping of an existing physical address to a new physical address.

10. A storage system according to claim 9, wherein the data buffer means is a SRAM.

11. A storage system according to claim 9 or 10, wherein the data buffer means is a bidirectional first-in-first-out (FIFO) buffer.

12. A storage system according to claim 9 or 10, wherein the buffer means is a dual ported memory.

13. A storage system according to any one of the preceeding claims, wherein the primary memory is a flash EPROM memory.

14. A storage system according to any one of the preceeding claims, wherein the sector size of the disk drive being emulated is 512 bytes.

15. A storage system according to any one of the preceeding claims, wherein the control means comprises a microprocessor and software.

16. A storage system according to any one of claims 1 to 14, wherein the control means comprises a state machine.

17. A storage system according to any one of the preceding claims, wherein the memory mapping means comprises a portion of the cache device.

18. A storage system according to any one of the preceeding claims, wherein the cache device is a SRAM.

19. A storage system according to any one of the preceeding claims, which is implemented in the form of a PCMCIA type card.

20. A mass storage memory system comprising a disk-compatible memory system interface means coupled to an EEPROM memory means and control processor means formed and arranged for controlling reading and writing of data between said interface and said EEPROM memory, said EEPROM memory comprising a plurality of large individually erasable blocks of data storage cells each of said large blocks being substantially larger than a disk sector, and said EEPROM memory being provided with fast temporary data storage means capable of being rewritten substantially faster than said EEPROM memory, for storing at least some data prior to writing thereof to the EEPROM memory, said control processor means being formed and arranged for:

maintaining mapping information providing current physical addresses corresponding to logical disk sector addresses and located somewhere within said EEPROM memory and said temporary data store, and buffering writing of at least some data having a given logical address, to said EEPROM memory, by initially writing said data to said temporary data store and updating the mapping information for said data to indicate the current physical address thereof in said temporary data store, said data being subsequently rewritten to said EEPROM memory with further updating of the mapping information for said data to indicate the new physical address thereof in said EEPROM memory.

21. A method of storing data generated by a host computer having an input/output connection interface configured for coupling to a disk drive, into a mass storage system arranged to emulate such a disk drive, the method comprising: storing in the storage system mapping data mapping logical disk sector addresses of the emulated disk drive to respective current physical addresses in a primary memory and a cache of the storage system, wherein the primary memory stores data within minimum erasable size blocks which are larger than the sectors of the emulated drive; on receipt of read instructions including a logical sector address from the host computer, determining from the mapping data a physical address in the primary memory or the cache corresponding to the received logical address and reading a sector of data from that physical address for transfer to the host computer;

on receipt of a write instruction including a logical disk sector address from the host computer, writing a received sector of data to the cache or primary memory according to predetermined memory management criteria at a physical address corresponding to the received sector address or, if necessary, at a new physical address and updating the memory mapping means to indicate the new corresponding physical address, wherein, when the physical address corresponds to a primary location, data is temporarily stored in the cache prior to transfer to the primary memory;

and, when required, copying selectively at least one said minimum erasable size data blocks to the cache from the primary memory and erasing selectively that minimum erasable size data block from the primary memory, in accordance with the predetermined memory management criteria, and updating the memory mapping means, thereby to allow further data to be transferred from the cache to the primary memory.

22. A solid state mass storage system including an interface for coupling to a disk compatible input/output part of a host computer, a data transfer buffer coupled to the interface, a flash EPROM memory having a minimum erasable block size and a read/white memory block which provides a tempory data store both of which are coupled to the data transfer buffer, wherein the read/write memory block contains look-up tables which enable the flash memory to become functionally identical to a hard disk drive with a predetermined sector size.