WO1995035581A3 - Non-volatile sidewall memory cell method of fabricating same - Google Patents
Non-volatile sidewall memory cell method of fabricating same Download PDFInfo
- Publication number
- WO1995035581A3 WO1995035581A3 PCT/IB1995/000359 IB9500359W WO9535581A3 WO 1995035581 A3 WO1995035581 A3 WO 1995035581A3 IB 9500359 W IB9500359 W IB 9500359W WO 9535581 A3 WO9535581 A3 WO 9535581A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- memory cell
- volatile
- array
- cell method
- line direction
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052710 silicon Inorganic materials 0.000 abstract 2
- 239000010703 silicon Substances 0.000 abstract 2
- 238000001459 lithography Methods 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
- H01L29/7885—Hot carrier injection from the channel
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
- H01L21/30612—Etching of AIIIBV compounds
- H01L21/30617—Anisotropic liquid etching
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/05—Etch and refill
Abstract
A non-volatile memory cell and array of such cells is provided. The memory cell includes a single transistor floating gate cell fabricated on a sidewall of a silicon pillar etched into a silicon substrate. The memory cells are arranged in an array of rows extending in a bit line direction and columns extending in a word line direction. A substantially smaller cell and array size is realized by limiting the dimension of the pillar and the bit line in the word line direction to be the minimum line width as limited by the lithography.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP95916816A EP0714554A1 (en) | 1994-06-17 | 1995-05-16 | Non-volatile sidewall memory cell method of fabricating same |
JP8501865A JPH09504655A (en) | 1994-06-17 | 1995-05-16 | Nonvolatile sidewall memory cell and manufacturing method thereof |
KR1019960700804A KR960704358A (en) | 1994-06-17 | 1995-05-16 | Non-volatile sidewall memory cell method of fabricating same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/261,511 US5432739A (en) | 1994-06-17 | 1994-06-17 | Non-volatile sidewall memory cell method of fabricating same |
US08/261,511 | 1994-06-17 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO1995035581A2 WO1995035581A2 (en) | 1995-12-28 |
WO1995035581A3 true WO1995035581A3 (en) | 1996-02-08 |
Family
ID=22993634
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB1995/000359 WO1995035581A2 (en) | 1994-06-17 | 1995-05-16 | Non-volatile sidewall memory cell method of fabricating same |
Country Status (6)
Country | Link |
---|---|
US (2) | US5432739A (en) |
EP (1) | EP0714554A1 (en) |
JP (1) | JPH09504655A (en) |
KR (1) | KR960704358A (en) |
TW (1) | TW275715B (en) |
WO (1) | WO1995035581A2 (en) |
Families Citing this family (71)
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US5929476A (en) * | 1996-06-21 | 1999-07-27 | Prall; Kirk | Semiconductor-on-insulator transistor and memory circuitry employing semiconductor-on-insulator transistors |
US5990509A (en) * | 1997-01-22 | 1999-11-23 | International Business Machines Corporation | 2F-square memory cell for gigabit memory applications |
US5792690A (en) | 1997-05-15 | 1998-08-11 | Vanguard International Semiconductor Corporation | Method of fabricating a DRAM cell with an area equal to four times the used minimum feature |
US6191470B1 (en) | 1997-07-08 | 2001-02-20 | Micron Technology, Inc. | Semiconductor-on-insulator memory cell with buried word and body lines |
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US5907170A (en) * | 1997-10-06 | 1999-05-25 | Micron Technology, Inc. | Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor |
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US6127226A (en) * | 1997-12-22 | 2000-10-03 | Taiwan Semiconductor Manufacturing Company | Method for forming vertical channel flash memory cell using P/N junction isolation |
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US6204529B1 (en) * | 1999-08-27 | 2001-03-20 | Hsing Lan Lung | 8 bit per cell non-volatile semiconductor memory structure utilizing trench technology and dielectric floating gate |
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US7550800B2 (en) * | 2003-06-06 | 2009-06-23 | Chih-Hsin Wang | Method and apparatus transporting charges in semiconductor device and semiconductor memory device |
US7115942B2 (en) * | 2004-07-01 | 2006-10-03 | Chih-Hsin Wang | Method and apparatus for nonvolatile memory |
US6958513B2 (en) * | 2003-06-06 | 2005-10-25 | Chih-Hsin Wang | Floating-gate memory cell having trench structure with ballistic-charge injector, and the array of memory cells |
US7613041B2 (en) * | 2003-06-06 | 2009-11-03 | Chih-Hsin Wang | Methods for operating semiconductor device and semiconductor memory device |
US7297634B2 (en) * | 2003-06-06 | 2007-11-20 | Marvell World Trade Ltd. | Method and apparatus for semiconductor device and semiconductor memory device |
US7759719B2 (en) * | 2004-07-01 | 2010-07-20 | Chih-Hsin Wang | Electrically alterable memory cell |
US20080203464A1 (en) * | 2004-07-01 | 2008-08-28 | Chih-Hsin Wang | Electrically alterable non-volatile memory and array |
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US7411244B2 (en) * | 2005-06-28 | 2008-08-12 | Chih-Hsin Wang | Low power electrically alterable nonvolatile memory cells and arrays |
US7927948B2 (en) | 2005-07-20 | 2011-04-19 | Micron Technology, Inc. | Devices with nanocrystals and methods of formation |
KR100697291B1 (en) * | 2005-09-15 | 2007-03-20 | 삼성전자주식회사 | Non volatile semiconductor memory device and method of fabricating the same |
US7554151B2 (en) * | 2005-11-03 | 2009-06-30 | Atmel Corporation | Low voltage non-volatile memory cell with electrically transparent control gate |
US7859026B2 (en) * | 2006-03-16 | 2010-12-28 | Spansion Llc | Vertical semiconductor device |
US8501581B2 (en) * | 2006-03-29 | 2013-08-06 | Micron Technology, Inc. | Methods of forming semiconductor constructions |
US20080277738A1 (en) * | 2007-05-08 | 2008-11-13 | Venkat Ananthan | Memory cells, memory banks, memory arrays, and electronic systems |
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US8624312B2 (en) * | 2011-04-28 | 2014-01-07 | Freescale Semiconductor, Inc. | Semiconductor device structure as a capacitor |
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JP5815813B2 (en) * | 2014-08-04 | 2015-11-17 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | Semiconductor device |
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-
1994
- 1994-06-17 US US08/261,511 patent/US5432739A/en not_active Expired - Fee Related
-
1995
- 1995-04-21 US US08/426,512 patent/US5563083A/en not_active Expired - Lifetime
- 1995-05-16 JP JP8501865A patent/JPH09504655A/en active Pending
- 1995-05-16 EP EP95916816A patent/EP0714554A1/en not_active Withdrawn
- 1995-05-16 KR KR1019960700804A patent/KR960704358A/en not_active Application Discontinuation
- 1995-05-16 WO PCT/IB1995/000359 patent/WO1995035581A2/en not_active Application Discontinuation
- 1995-06-29 TW TW084106701A patent/TW275715B/en active
Non-Patent Citations (4)
Title |
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IEEE TRANSACTIONS ON ELECTRON DEVICES, Volume 38, No. 3, March 1991, HIROSHI TAKATO et al., "Impact of Surrounding Gate Transistor (SGT) for Ultra-High-Density LSI's". * |
IEEE TRANSACTIONS ON ELECTRON DEVICES, Volume 40, No. 11, November 1993, HOWARD PEIN et al., "A 3-D Sidewall Flash EPROM Cell and Memory Array". * |
PATENT ABSTRACTS OF JAPAN, Vol. 16, No. 444, E-1265; & JP,A,4 155 870 (NEC CORP), 28 May 1992 (28.05.92). * |
PATENT ABSTRACTS OF JAPAN. Vol. 16, No. 297, E-1226; & JP,A,4 079 369 (TOSHIBA CORP), 12 March 1992 (12.03.92). * |
Also Published As
Publication number | Publication date |
---|---|
JPH09504655A (en) | 1997-05-06 |
EP0714554A1 (en) | 1996-06-05 |
KR960704358A (en) | 1996-08-31 |
TW275715B (en) | 1996-05-11 |
WO1995035581A2 (en) | 1995-12-28 |
US5432739A (en) | 1995-07-11 |
US5563083A (en) | 1996-10-08 |
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