WO1996016433A3 - Process for the anisotropic and selective dry etching of nitride over thin oxides - Google Patents

Process for the anisotropic and selective dry etching of nitride over thin oxides Download PDF

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Publication number
WO1996016433A3
WO1996016433A3 PCT/US1995/015474 US9515474W WO9616433A3 WO 1996016433 A3 WO1996016433 A3 WO 1996016433A3 US 9515474 W US9515474 W US 9515474W WO 9616433 A3 WO9616433 A3 WO 9616433A3
Authority
WO
WIPO (PCT)
Prior art keywords
layer
anisotropic
nitride
dry etching
nitride over
Prior art date
Application number
PCT/US1995/015474
Other languages
French (fr)
Other versions
WO1996016433A2 (en
Inventor
Francois Hebert
Rashid Bashir
Original Assignee
Nat Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nat Semiconductor Corp filed Critical Nat Semiconductor Corp
Priority to EP95943617A priority Critical patent/EP0739537A1/en
Publication of WO1996016433A2 publication Critical patent/WO1996016433A2/en
Priority to KR1019960703737A priority patent/KR970703042A/en
Publication of WO1996016433A3 publication Critical patent/WO1996016433A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/005—Control means for lapping machines or devices
    • B24B37/013—Devices or means for detecting lapping completion
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement

Abstract

In a method for anisotropically and selectively etching a nitride layer in a semiconductor device having a layer of nitride overlying a layer of oxide on a silicon substrate, first, the substrate is placed between the upper electrode and the lower electrode of a reactive ion etching device. Then, the etching process is commenced. The endpoint of the etch is determined by measuring the change in voltage between the upper and lower electrodes. The etching process is terminated some time after determining that the chaange in the measured voltage is approximately equal to zero. The change in the measured voltage is approximately equal to zero when the layer of nitride is completely etched from the layer of oxide.
PCT/US1995/015474 1994-11-10 1995-11-13 Process for the anisotropic and selective dry etching of nitride over thin oxides WO1996016433A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP95943617A EP0739537A1 (en) 1994-11-10 1995-11-13 Process for the anisotropic and selective dry etching of nitride over thin oxides
KR1019960703737A KR970703042A (en) 1994-11-10 1996-07-10 PROCESS FOR THE ANISOTROPIC AND SELECTIVE DRY ETCHING OF NITRIDE OVER THIN OXIDES

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US33730394A 1994-11-10 1994-11-10
US08/337,303 1994-11-10

Publications (2)

Publication Number Publication Date
WO1996016433A2 WO1996016433A2 (en) 1996-05-30
WO1996016433A3 true WO1996016433A3 (en) 1996-08-29

Family

ID=23319980

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1995/015474 WO1996016433A2 (en) 1994-11-10 1995-11-13 Process for the anisotropic and selective dry etching of nitride over thin oxides

Country Status (3)

Country Link
EP (1) EP0739537A1 (en)
KR (1) KR970703042A (en)
WO (1) WO1996016433A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE59914708D1 (en) * 1998-12-24 2008-05-08 Atmel Germany Gmbh Process for the anisotropic plasma chemical dry etching of silicon nitride layers by means of a fluorine-containing gas mixture
KR100457742B1 (en) * 2002-05-16 2004-11-18 주식회사 하이닉스반도체 Method for forming a gate of semiconductor device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4602981A (en) * 1985-05-06 1986-07-29 International Business Machines Corporation Monitoring technique for plasma etching
US4832787A (en) * 1988-02-19 1989-05-23 International Business Machines Corporation Gas mixture and method for anisotropic selective etch of nitride
US5015331A (en) * 1988-08-30 1991-05-14 Matrix Integrated Systems Method of plasma etching with parallel plate reactor having a grid
US5198072A (en) * 1990-07-06 1993-03-30 Vlsi Technology, Inc. Method and apparatus for detecting imminent end-point when etching dielectric layers in a plasma etch system
US5242532A (en) * 1992-03-20 1993-09-07 Vlsi Technology, Inc. Dual mode plasma etching system and method of plasma endpoint detection
US5322809A (en) * 1993-05-11 1994-06-21 Texas Instruments Incorporated Self-aligned silicide process

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4602981A (en) * 1985-05-06 1986-07-29 International Business Machines Corporation Monitoring technique for plasma etching
US4832787A (en) * 1988-02-19 1989-05-23 International Business Machines Corporation Gas mixture and method for anisotropic selective etch of nitride
US5015331A (en) * 1988-08-30 1991-05-14 Matrix Integrated Systems Method of plasma etching with parallel plate reactor having a grid
US5198072A (en) * 1990-07-06 1993-03-30 Vlsi Technology, Inc. Method and apparatus for detecting imminent end-point when etching dielectric layers in a plasma etch system
US5242532A (en) * 1992-03-20 1993-09-07 Vlsi Technology, Inc. Dual mode plasma etching system and method of plasma endpoint detection
US5322809A (en) * 1993-05-11 1994-06-21 Texas Instruments Incorporated Self-aligned silicide process

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
MCNEVIN ET AL: "Bias voltage diagnostics during oxide etch in Drytek 384T", JOURNAL OF VACUUM SCIENCE AND TECHNOLOGY: PART A, vol. 11, no. 4, August 1993 (1993-08-01), NEW YORK US, pages 1142 - 1144, XP000575221 *
STOCKER: "Selective reactive ion etching of silicon nitride on oxide in a multifacet ("HEX") plasma etching machine", JOURNAL OF VACUUM SCIENCE AND TECHNOLOGY: PART A, vol. 7, no. 3, June 1989 (1989-06-01), NEW YORK US, pages 1145 - 1149, XP000126089 *

Also Published As

Publication number Publication date
WO1996016433A2 (en) 1996-05-30
EP0739537A1 (en) 1996-10-30
KR970703042A (en) 1997-06-10

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