WO1996024098A3 - Circuit arrangement comprising a permutation unit and method of processing a batch of items - Google Patents

Circuit arrangement comprising a permutation unit and method of processing a batch of items Download PDF

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Publication number
WO1996024098A3
WO1996024098A3 PCT/IB1996/000077 IB9600077W WO9624098A3 WO 1996024098 A3 WO1996024098 A3 WO 1996024098A3 IB 9600077 W IB9600077 W IB 9600077W WO 9624098 A3 WO9624098 A3 WO 9624098A3
Authority
WO
WIPO (PCT)
Prior art keywords
permutations
batch
items
permutation
calculated
Prior art date
Application number
PCT/IB1996/000077
Other languages
French (fr)
Other versions
WO1996024098A2 (en
Inventor
Hendrik Drik Lodewijk Hollmann
Constant Paul Marie Joz Baggen
Original Assignee
Philips Electronics Nv
Philips Norden Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronics Nv, Philips Norden Ab filed Critical Philips Electronics Nv
Priority to EP96900676A priority Critical patent/EP0754320B1/en
Priority to JP52338396A priority patent/JP3773263B2/en
Priority to AT96900676T priority patent/ATE206217T1/en
Priority to DE69615475T priority patent/DE69615475T2/en
Publication of WO1996024098A2 publication Critical patent/WO1996024098A2/en
Publication of WO1996024098A3 publication Critical patent/WO1996024098A3/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0059—Convolutional codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/275—Interleaver wherein the permutation pattern is obtained using a congruential operation of the type y=ax+b modulo c
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2782—Interleaver implementations, which reduce the amount of required interleaving memory
    • H03M13/2785—Interleaver using in-place interleaving, i.e. writing to and reading from the memory is performed at the same memory location
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/713—Spread spectrum techniques using frequency hopping
    • H04B1/7143—Arrangements for generation of hop patterns
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/713—Spread spectrum techniques using frequency hopping
    • H04B1/7136—Arrangements for generation of hop frequencies, e.g. using a bank of frequency sources, using continuous tuning or using a transform
    • H04B2001/71367—Arrangements for generation of hop frequencies, e.g. using a bank of frequency sources, using continuous tuning or using a transform using a transform
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2602—Signal structure

Abstract

The circuit arrangement calculates pseudo-random permutations of a set of numbers. It is required that the permutations that can be calculated by the circuit arrangement include compositions of some basic pseudo-random permutations and the inverse permutations of permutations that are calculated (a composition corresponds to cumulatively repeated reordering of the numbers, an inverse of a permutation is a permutation that undoes the permutation). The basic pseudo-random permutations, their compositions and inverses are all calculated by the same generator whose operation is commanded to calculate the appropriate permutation by specifying a set of integer coefficients fi. The generator calculates the permutations σ(n) of the numbers n=O..m-1 corresponding to I, whereα is an integer number which is divisible by all prime factors of m and by four if m is divisible by four, with a potency s(α) of two or higher. When the same α is used for all permutations it is assured that all compositions and inverses of the generated permutations can be calculated in the same way, by the same generator. By storing a batch of items in a storage medium in a first order and retrieving the items from the storage medium in a second order, the first and second order corresponding to different permutations which are both of this type, it is made possible to permute the batch pseudo-randomly and start storing the batch of items in the storage medium before a previous batch has been fully retrieved from it.
PCT/IB1996/000077 1995-02-01 1996-01-29 Circuit arrangement comprising a permutation unit and method of processing a batch of items WO1996024098A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP96900676A EP0754320B1 (en) 1995-02-01 1996-01-29 Circuit arrangement comprising a permutation unit and method of processing a batch of items
JP52338396A JP3773263B2 (en) 1995-02-01 1996-01-29 Circuit device including permutation unit and method for processing a set of items
AT96900676T ATE206217T1 (en) 1995-02-01 1996-01-29 CIRCUIT DEVICE HAVING A PERMUTATION UNIT AND PROCESSING METHOD FOR A STACK OF ELEMENTS
DE69615475T DE69615475T2 (en) 1995-02-01 1996-01-29 CIRCUIT DEVICE WITH A PERMUTATION UNIT AND PROCESSING METHOD FOR A STACK OF ELEMENTS

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
EP95200242.6 1995-02-01
EP95200242 1995-02-01
EP95200520 1995-03-03
EP95200520.5 1995-03-03
EP95200580.9 1995-03-09
EP95200580 1995-03-09
EP95200642.7 1995-03-16
EP95200642 1995-03-16

Publications (2)

Publication Number Publication Date
WO1996024098A2 WO1996024098A2 (en) 1996-08-08
WO1996024098A3 true WO1996024098A3 (en) 1996-09-26

Family

ID=27443064

Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/IB1996/000064 WO1996024196A1 (en) 1995-02-01 1996-01-26 Method of error protected transmission, method of error protected reception of data and transmission system for transmission of data
PCT/IB1996/000077 WO1996024098A2 (en) 1995-02-01 1996-01-29 Circuit arrangement comprising a permutation unit and method of processing a batch of items

Family Applications Before (1)

Application Number Title Priority Date Filing Date
PCT/IB1996/000064 WO1996024196A1 (en) 1995-02-01 1996-01-26 Method of error protected transmission, method of error protected reception of data and transmission system for transmission of data

Country Status (13)

Country Link
US (2) US5737252A (en)
EP (10) EP2302809B1 (en)
JP (2) JP3623966B2 (en)
KR (2) KR100411165B1 (en)
CN (1) CN1199359C (en)
AT (1) ATE206217T1 (en)
AU (1) AU706801B2 (en)
BR (1) BR9603962A (en)
DE (2) DE69621887T2 (en)
DK (9) DK2302805T3 (en)
HK (1) HK1013373A1 (en)
MY (1) MY118323A (en)
WO (2) WO1996024196A1 (en)

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