WO1996024161A1

WO1996024161A1 - Electronic device and process for making same

Info

Publication number: WO1996024161A1
Application number: PCT/US1996/001049
Authority: WO
Inventors: Timothy Edward Boles; Paulette Rita Noonan
Original assignee: The Whitaker Corporation
Priority date: 1995-01-30
Filing date: 1996-01-30
Publication date: 1996-08-08
Also published as: KR19980701728A; JP2002515177A

Abstract

The present invention provides a transistor-based electronic device and process for making same that overcome the disadvantages and drawbacks of the prior art. One embodiment of the process of the present invention begins by forming a number of transistors on a substrate. This is accomplished by forming a common collector region for the transistors on the substrate by depositing a layer of a first conductivity type on the substrate. Base regions of the transistors are then formed in the common collector region. Emitter regions for the transistors are then formed in the base regions. Next, the common collector layer is etched to form cavities therein separating or partitioning the common collector layer into individual collector regions for each of the respective transistors. According to the subject invention, the cavities are made at least about 50 microns in depth. A layer of glass in then formed, which layer fills in the cavities.

Description

ELECTRONIC DEVICE AND PROCESS FOR MAKING SAME

The present invention relates generally to electronic devices and processes for making same, and more specifically, to semiconductor device having a number of circuit elements separated by deep trenches (50-300 microns or more) of insulating material, and a process for making same. Particular utility for the present invention is found in the area of fabrication of transistor-based high-frequency microwave and monolithic circuits, although other utilities are contemplated, for example, in fields related to fabrication of other types of electronic and integrated circuit devices.

Transistor-based semiconductor devices are well known in the electronics arts. One such device is the multi-stage, monolithic microwave amplifier. Commonly, such amplifiers include a plurality of transistors and biasing elements (e.g., resistors) disposed upon a substrate and configured to form at least one input stage for providing a high input impedance to the amplifier, and output stage for providing high current gain and low output impedance. It is also common for one or more intermediate gain stages to be included in the amplifier in between the input and output stages to increase the overall gain of the amplifier. Various passive elements such as capacitors and resistors are included to match the input and output impedances of the amplifier to those of external networks to which the amplifier is connected and/or to provide additional functionality to the amplifier.

As is known to those skilled m the art, one cf tne key factors that determines the overall performance of such amplifiers is the degree to which electrical isolation (at both DC and RF) can be maintained between the active areas of the individual transistors of the amplifier, when such isolation is desirable. In general, when a high degree of electrical isolation cannot be adequately maintained between such elements cf the amplifier, the amplifier's performance suffers.

One prior art method for forming and isolating sucn circuit elements begins by forming a number of transistors on a substrate. Initially, all of the transistors are connected together by a "common" collector layer. Relatively shallow (i.e., 5 to 10 microns in depth) trenches are then formed in the collector layer to partition the collector layer into separate collector regions for each of the transistors. The trenches are then filled, and the surface of the device covered with one or more layers of dielectric materials, such as polycrystalline silicon, glass, and/or organic films. Typically, the depth of the dielectric material external to the trenches is relatively shallow (i.e , about 1 micron) . Sometimes the trenches are left unfilled altogether, and air is used as the dielectric. The device is then completed DV forming desired transistor biasing and feedback resistors, and/or impedance matching networks on the surface of the dielectric material adjacent the transistors, but external to the trench areas.

Since the impedance matching, and biasing and feedback networks are formed on top of relatively thin dielectric layers (about 1 micron in depth) , a great deal of RF coupling may be exhibited by these elements through the dielectric layer to the remainder of the device . A further disadvantage is that the thin dielectric material layer usually exhibits a high loss tangent, and thus may cause a great deal of parasitic capacitance to be generated. Finally, the relatively shallow trenches may be inadequate to sufficiently electrically isolate the collector regions of the transistors from each other. These problems serve to greatly reduce the performance of the resulting electronic device.

Prior art of general relevance to the subject invention is disclosed in U.S. Pat. No. 5,024,965 to Chang et al . , U.S. Pat. No 3,874,918 to Nechtow et al . , U.S. Pat. No. 5,231,046 to Tasaka, U.S. Pat. No.

5,091,321 to Huie et al, U.S. Pat. No. 4,093,771 to Goldstein et al . , U.S. Pat. No. 4,369,220 to Prabhu et al., and U.S. Pat. No. 4,133,690 to Muller. All of this prior art suffers from the aforesaid and/or other disadvantages.

It is therefore an object of the present invention to provide an electronic or semi-conductor device and process for making same that overcome the aforesaid and other disadvantages of the prior art, and more specifically, to provide a transistor-based device and process for making same that permits the individual collectors of the transistors (and/or other circuit elements of the device) to be adequately electrically isolated from each other so as to optimize overall device performance.

The present invention provides a transistor-based electronic device and process for making same that overcome the disadvantages and drawbacks of the prior art . One preferred embodiment of the process of the present invention begins by forming a number of transistors on a substrate. This is accomplished by forming a common collector region for the transistors on the substrate by depositing a layer of a first conductivity type on the substrate. Base regions of the transistors are then formed in the common collector region. Emitter regions for the transistors are then formed in the base regions. Next, the common collector layer is etched to form cavities therein separating or partitioning the common collector layer into individual collector regions for each of the respective transistors. According to the subject invention, the cavities should be made between about 50 and 300 microns in depth. A layer of glass is then formed, which layer substantially or at least partially fills in the cavities. One or more electronic components (e.g., inductors, capacitors, etc.) then may be formed on the glass and connected to selected active areas of the device. Advantageously, it has been found that the process of the present invention permits parasitic RF 'coupling capacitance among the elements of the device to be reduced by at least a factor of 50 over the prior art. Additionally, the glass dielectric layer of the present invention exhibits a much lower loss tangent, and provides a far greater electrical isolation between the collector regions of the transistors than in the prior art. Further advantageously, if the electronic component formed on the glass is an inductor, the present invention permits the inductor to exhibit an actual Q factor of about 50, whereas in the prior art the maximum attainable Q factor typically is only about 8-9. Thus, the present invention permits fabrication of a transistor-based electronic device whose performance is greatly improved over that of the prior art.

These and other advantages and objects of the present invention will become apparent as the following Detailed Description proceeds, and upon reference to the Drawings, wherein like numerals depict like parts and in which:

Figure 1 is a top-plan, physical layout schematic of one preferred embodiment of the transistor-based electronic device of the present invention, which embodiment is a multi-stage, monolithic amplifier.

Figures 2 - 22 are various side, cross-sectional views taken along lines A-A of Figure 24 for illustrating a preferred process for fabricating the device of Figure 1. Figure 23 is an equivalent circuit diagram of the embodiment of Figure 1.

Figure 24 is a perspective view of the physical schematic layout of the embodiment of Figure 1, shown without its outer encapsulating layers, inductor, glass layer, and interconnections between the components of the device (i.e., transistors, resistors, etc.) .

Although the present invention will be described in connection with preferred embodiments and methods of use, it will be appreciated that it is not intended to be limited to these preferred embodiments and methods of use. On the contrary, the present invention is intended to be viewed has being of broad scope, as only defined by the hereinafter appended claims.

Figures 1 and 24 are two physical layout schematic views of one preferred embodiment 10 of the device of the present invention. The electrically equivalent circuit for embodiment 10 is shown in Figure 23. As can be seen from Figure 23, embodiment 10 is a multi-stage transistor-based amplifier. Amplifier 10 comprises three transistors 100, 102, 105 corresponding, respectively, to transistors Ql, Q2, Q3 of Figure 23, which transistors are interconnected with biasing and feedback resistors R2 . . . R6 and shunt capacitor C7 (216) and inductor LI (214) to form emitter-follower input stage 250 and Darlingon-pair output stage 252. Resistors R2 . . . R6 are shown in Figures 1 and 24 as physical resistive patterns 202, 206, 208, 207, and 224 and 226, respectively. Metallizations (collectively referred to by reference numeral 244) interconnect the various elements of the circuit 10. Input and output vias are illustrated in Figure 1 as 242, 234 and correspond to elements RF in and RF out, respectively, Figure 23. Ground vias are shown in Figure 1 as 234, 232, 220, 222, 236, 238, respectively.

Advantageously, as will be explained more fully below in connection with the process of the present invention, in device 10, various elements and/or electronic components of the device 10 are separated and electrically insulated from each other by a layer of msulative glass material.

With reference now being made specifically to Figures 2 - 22, a preferred method for forming the device 10 of Figure 1 will now be described. It will be appreciated that the numbers assigned to Figures 2 - 22 coincide with the sequence of steps of this embodiment of the process of the instant invention. It will also be appreciated that although the cross-sectional views of Figures 2-22 only show formation of certain of the components (i.e., transistors, resistors, etc.) of the device 10, the same principles and steps used to construct these elements are used to form the other elements of the device not shown in Figures 2-22. As shown in Figure 2, the preferred process for forming the device of Figure 1 begins by depositing a first epitaxial layer 12 of (preferably) n-doped material on the entire surface of a substrate 14. Preferably, substrate 14 is n+ doped silicon having a crystal orientation of <l-0-0> and a thickness of about 35 mil. Preferably, either antimony or arsenic is used as the dopant for substrate 14 , which has a dopant concentration of about 10¹⁹ atoms/cc. Epitaxial layer 12 has a thickness of about 3 microns and a dopant concentration of about 4 x 10¹⁵ to 2 x 10¹⁶ atoms/cc. As shown in Fig. 3, once epitaxial layer 12 is formed on substrate 14, a layer 16 of masking silicon dioxide is formed on the epitaxial layer 12. Preferably, layer 16 is formed using a conventional low temperature chemical vapor deposition (CVD) process, and has a thickness of about 6000 to 8000 angstroms or more. As illustrated in Figure 4, conventional dry-etch photoresist techniques are then used to etch openings 18, 19, 20, 21 in oxide layer 16 to regions 22, 23, 24, 25, respectively, in layer 12 and substrate 14 wherein low resistance collector contacts 26, 27, 28, 29 are to be formed. As shown in Figure 5, the oxide layer 16 as a mask, n-type ions are then implanted into regions 22, 23, 24, 25 to form contacts 26, 27, 28, 29 having n-type dopant concentrations higher than that of the substrate 14 and epitaxial layer 12, and preferably, of about 10²⁰ atoms/cc.

The masking layer 16 is then removed using conventional techniques and conventional LOCOS techniques are used to form a silicon dioxide layer 30 of about 200 angstrom thickness on layer 12. A layer 32 of about 1200 angstrom thickness of silicon nitride is then formed on oxide layer 30 using conventional low pressure CVD techniques. As shown in Figure 6, using conventional photoresist and etching techniques, nitride layer 32, oxide layer 30, and epitaxial layer 12 are then etched to form a trough 34 of about 5700 angstrom depth completely through nitride layer 32 and oxide layer 30, and partially through epitaxial layer 12. As shown in Figure 7, a field oxide layer 36 of abut 8000 to 12,000 angstrom thickness is then grown in trough 34 using conventional techniques. The nitride layer 32 is then removed from the entire surface of the device, and (as shown in Figure 8) a layer of pattern oxide 38 of about 1000 angstrom thickness is grown thereon using conventional techniques.

A layer of polysilicon is then deposited on the pattern oxide 38 using low pressure CVD techniques. The polysilicon layer is then n-doped using conventional dopant ion implantation techniques to a sufficient degree to make the resistivity of the layer about 80-150 ohm/square cm. As shown in Figure 9, using a conventional photolithography techniques, the polycrystalline layer is patterned into resistors 43 of desired shapes and resistive values for interconnecting and biasing various elements of the device 10.

Turning to Figure 10, using standard etching techniques, a roughly annular ring 42 is then etched between the contact regions through pattern oxide 38, and oxide layer 30 (shown merged with pattern oxide layer 38) . Boron ions (or some other type of p-type dopant) are then implanted or diffused through ring 42 into layer 12 to provide an edge breakdown regions 46A, 46B at the outer edge of intended base regions 44A, 44B. Preferably, region 46 has a p-type dopant concentration of about 10¹ to 10 atoms/cc. The p-type dopant in the breakdown regions 46A, 46B are then activated using conventional thermal activation techniques.

As shown in Figure 11, the pattern oxide layer 38 and oxide layer located adjacent base region 44A, 44B are then removed. A screen oxide layer 48 of about 400 angstroms in thickness for helping to prevent implantation ion channeling is then formed in the intended base regions 44A, 44B using conventional techniques. P-type ions (such as, boron) are then implanted into the base regions 44A, 44B through the screen oxide layer 48 to form base regions 44A, 44B. Preferably, the p-type ions are implanted to a depth of about 2800 angstroms in the n-layer 12 and provide a p- dopant concentration therein of about 10¹⁷ to 10¹⁸ atoms/cc.

Turning to Figure 12, another oxide layer 50 is formed on the pattern oxide 38, resistors 43, and base regions 44A, 44B using low temperature CVD techniques. Preferably, oxide layer 50 is made of silicon dioxide and has a thickness of about 2000 to 4000 angstroms. The p-ions implanted into base regions 44A, 44B are then activated using thermal activation techniques, which also serve to densify the oxide layer 50.

Layers 50, 38 and 48 are then etched to form a number of openings 52 . . . 64 to the base regions 44A, 44B, resistor contact region openings 66 and 68 and openings 70, 71, 72, 73 above the collector contact regions. As seen in Figure 13, openings 54, 60, 66, 68, 70, 71, 72, and 73 are then masked with a conventional photoresist 74, and additional p-type ions are implanted to the portions of the base regions 44A, 44B not covered with photoresist 74.

As shown in Figure 14, the photoresist 74 is removed and replaced with a mirror-image pattern of photoresist 76, thereby exposing openings 54, 60, 66, 68, 70, 71, 72 and 73. N-type ions (e.g., arsenic or phosphorus) are implanted into the unmasked collector contact regions 26, 27, 28, 29 to form emitter regions 78 and 80 in base regions 44A, 44B, and into the resistor contact regions 79, 81, such that these regions exhibit dopant concentration of about 5 x 10²⁰ - 1 x 10²¹ atoms/cc. As will be appreciated by those skilled in the art, the number of emitter regions formed is variable depending upon the desired operating power of the transistor to be formed.

Figure 15-19 are so-called "geometry" type cross- sectional views of greater scale than views 2-14 of device 10, for illustrating particularly advantageous features of the present invention. As shown in Figure 16, after implantation of the n-type ions, the photoresist 76 is removed and the device undergoes a final thermal activation. Oxide layers 38, 50 external to the transistor 100, 102 and resistor 103 active regions are then removed. A layer 84 of silicon nitride is then formed on the device using low pressure CVD techniques to shield the active regions 100, 102, 103 from damage during subsequent processing of the device. The nitride layer 84 is then etched so that it only covers the active regions. Cavities 85, 86, 88, 90 are then formed in the n-layer 12 and substrate 14 to partition the common collector layer 12 into separate collector regions 91, 92, 93, 94, 95, for the input via 101, transistors 100, 102, resistor 103, and output via 105, respectively. Preferably, formation of the cavities 85, 86, 88, 90 is accomplished by carrying out an orientation dependent isotropic etching of substrate 14 and n-layer 12. According to the present invention, the cavities are made at least 50 microns deep, and preferably are between about 50 and 300 microns deep. Nitride layer 84 is then removed.

After forming the cavities, layer 110 of silicon nitride and layer 111 of polysilicon or other "polish stop" material optionally and preferably is formed. However, formation of layer 110 may be omitted without departing from the present invention. Thereafter, a layer 112 of glass is formed on the device to fill in the cavities and cover the transistors. Preferably, formation of glass layer 112 is accomplished by using the process described in U.S. Patent No. 5,268,310 (which patent is incorporated herein by reference in its entirety) issued to Goodrich and Souchuns and assigned to the Assignee of the present application. Preferably, glass layer 112 is made of Corning 7070 borosilicate glass which glass material has been found to exhibit particularly desirable electrical and thermal expansion characteristics. However, other types of glass may be used so long as they have thermal expansion characteristics that closely match those of silicon, and exhibit a minimum dielectric constant of about 4.1 and a maximum loss tangent of about 0.06 percent at 20 degrees C and 1 MHz. Indeed, in certain embodiments, the glass layer may be omitted altogether, and air may be relied upon as the insulating material; other non-glass materials may also be used.

After being formed, glass layer 112 is mechanically ground and chemically polished to remove the glass from all areas external to the cavities, and to provide a substantially planar surface across the device. Advantageously, polish stop layer 110 protects the transistors from being damaged during this process.

Returning now the smaller scale drawings of Figures 20-21, the polysilicon and nitride layers external to the glass are then removed. Ohmic contacts 120 . . . 140 and metallizations 142 . . . 162 are formed in the active areas and resistor contact regions. Preferably, the ohmic contacts comprise titanium, platinum, palladium, and/or cobalt suicides, while the metallizations are of a titanium-platinum-gold composition. Additional electronic components (e.g., conventional air bridge connection 166 and bond pad 168) are formed and connected to various of the metallizations 158, in order to interconnect active areas 27 of the device to construct the overall functionality of the device 10. The entire device 10 is then encapsulated with plasma nitride 164 and polyimide cap 172 layers. Polyimide cap 172 serves to prevent damage to the device and to help support structures such as air bridge connection 166.

Finally, as shown in the geometry scale drawing of Figure 22, back-side 174 of the substrate 14 is mechanically ground and chemically polished to remove enough of substrate 14 to bare the back-side portion 190 of the glass layer filling he cavities, so as to totally electrically isolate the collector regions of the transistors, resistors, and input and output vias. Thereafter, back-side metal and/or electronic structures, components, and/or interconnections 175, 176, 177, 178, 179 (which may e.g. be capacitors, or bond pads) are formed on the back-side 174 of the device. The backside contacts 175, 176, 177, 178, 179 complete the interconnection of the various components of the device 10 to transform the circuit into a surface mount-type configura ion to further the functionality of the device 10. Advantageously, this arrangement permits elimination of the need to form wire-bond connections in device 10, and the backside metallizations may be directly coupled via a conventional circuit board (not shown) to external circuits (not shown) to provide interconnections without wirebond connections being included in device 10. Of course, some or all of the metallizations may be formed on top of the front-side

182 of the device 10 on top of the vias. Metallizations and interconnections to active areas 100, 101, 102, 103, and 105 are referenced collectively by numeral 200.

Advantageously, the thick glass layer separates and substantially completely electrically isolates the transistors of the electronic device. Indeed, it has been found that the present invention permits parasitic RF coupling capacitance among the elements of the device to be reduced by at least a factor of fifty over what is possible according to the prior art.

Thus, it is evident that there has been provided a process and article that fully satisfy both the aims and objects hereinbefore set forth. Various modifications may be made to the preferred embodiments and methods of use hereinbefore set forth without departing from the scope of the invention. For example, other processes for forming the glass layer may also be used without departing from the present invention. Likewise, although preferred techniques have been described above for forming device 10, other techniques may be used to form the device 10 without departing from the present invention, so long as the various design constraints specified above are satisfied. Additionally, the types of materials, dopants, thicknesses, and dopant concentrations are exemplary and many variations thereof are possible. Furthermore, although the transistor structures have been described herein as being n-p-n bipolar junction transistors, if the device and method of the present invention are appropriately modified in ways apparent to those skilled in the art, the transistors may be other types of transistor, including p-n-p, metal oxide semiconductor, or junction field effect transistors. Indeed, other active and/or passive elements may be electrically isolated without limitation according to the present invention. Other modifications are also possible. Therefore, it is intended that the subject invention be viewed broadly to encompass all such modifications, and that it defined only by the hereinafter appended claims.

Claims

Claims:

1. An electronic device having a plurality of transistors having a common collector layer an emitter region, a base region and at least one cavity between said transistors said at least one cavity having a dielectric disposed therein characterized i that: said dielectric is insulating glass.

2. An electronic device as recited in claim 1 wherein said at least one cavity has a depth that is greater than the thickness of said collector layer.

3. An electronic device as recited in any of the preceding claims wherein said collector layer has a thickness on the order of three microns.

4. An electronic device as recited in any of the preceding claims wherein said at least one cavity has a depth on the order of at least 50 microns.

5. An electronic device as recited in any of the preceding claims wherein said insulating glass has a dielectric constant of at least 4.10.

6. An electronic device as recited in any of the previous claims wherein said insulating glass has a loss tangent at 20°C and 1MHz not greater than about 0.06%.

7. An electronic device as recited in any of the preceding claims wherein said insulating glass is borosilicate.

8. An electronic device having a plurality of transistors having a common collector layer an emitter region, a base region and at least one cavity between said transistors said at least one cavity having a dielectric disposed therein characterized in that: said at least one cavity has a depth that is greater than the thickness of said collector layer.

9. An electronic device as recited any of the preceding claims wherein said collector layer has a thickness on the order of 3 microns.

10. An electronic device of any of the preceding claims wherein said at least one cavity has a depth on the order of at least 50 microns.

11. An electronic device as recited in any of the preceding claims wherein said dielectric material is insulating glass.

12. An electronic device as recited in any of the preceding claims wherein said dielectric material has a dielectric constant of at least 4.10.

13. An electronic device as recited in any of the preceding claims wherein said insulating glass has a loss tangent at 20°C and 1MHz not greater than about 0.06%.

14. An electronic device as recited in any of the preceding claims wherein said insulating glass is borosillicate.