WO1996024953A1 - TRENCH FIELD EFFECT TRANSISTOR WITH REDUCED PUNCH-THROUGH SUSCEPTIBILITY AND LOW R¿DSon? - Google Patents
TRENCH FIELD EFFECT TRANSISTOR WITH REDUCED PUNCH-THROUGH SUSCEPTIBILITY AND LOW R¿DSon? Download PDFInfo
- Publication number
- WO1996024953A1 WO1996024953A1 PCT/US1996/000941 US9600941W WO9624953A1 WO 1996024953 A1 WO1996024953 A1 WO 1996024953A1 US 9600941 W US9600941 W US 9600941W WO 9624953 A1 WO9624953 A1 WO 9624953A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- region
- layer
- trench
- transistor
- body region
- Prior art date
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 25
- 210000000746 body region Anatomy 0.000 claims abstract description 45
- 239000002019 doping agent Substances 0.000 claims abstract description 25
- 238000009825 accumulation Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 12
- 229910052710 silicon Inorganic materials 0.000 abstract description 12
- 239000010703 silicon Substances 0.000 abstract description 12
- 238000009877 rendering Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 13
- 230000005684 electric field Effects 0.000 description 2
- 239000008186 active pharmaceutical agent Substances 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
Definitions
- This invention relates to trench field effect transistors.
- Figure 1 is a simplified cross- sectional diagram of a conventional planar double diffused field effect transistor.
- a layer of N type epitaxial silicon 1 is formed on an N+ type substrate 2.
- a P body region 3A and a P+ body region are formed into the epitaxial layer from upper surface 4, and an
- N+ type source region 5 is formed into the body regions 3A and 3B from upper surface .
- a positive potential is placed on gate 6.
- the positive potential on gate 6 causes what is called a channel region to form in the surface portion of P body region 3A underneath the gate and also causes what is called an accumulation region to form in the surface portion of the N type epitaxial silicon region 1A immediately underneath the gate. Electrons can then flow as generally indicated by the arrow from the N+ type source region 5, through the channel region in P body region 3A, through the accumulation region of N type epitaxial layer 1A, downward through the N type epitaxial region 1A, downward through the N+ type substrate 2, and to a drain electrode 7.
- Figure 2 is a simplified cross- sectional diagram of another type of double diffused field effect transistor, a trench field effect transistor.
- An N type epitaxial layer 1 is formed on a N+ type substrate 2.
- Body regions 3A and 3B and N+ type source region 5 are then formed in similar double diffused fashion to the body and source regions in the planar transistor.
- a trench is etched down into epitaxial layer 1 from upper surface 4.
- a gate oxide layer 8 is then grown in this trench on the side walls and the trench bottom.
- a positive potential is placed on gate 9.
- the positive potential causes a channel region to form in the portion of the P body region 3A which forms part of the sidewall of the trench and causes an accumulation region to form in the portion of the N type epitaxial layer region 1A which forms a part of the sidewall of the trench. Electrons can then flow as indicated by the arrow from the N+ type source region 5, downward through the channel region of P body region 3A, downward through the accumulation region, downward through the remainder of the N type epitaxial region 1A, downward through the N+ type substrate 2, and to a drain electrode 7. If gate 9 does not have a positive potential, then no channel is formed and no electron flow from source to drain takes place. The transistor is therefore turned off.
- the resistance R DSon in the planar structure is made up of the resistance Rc H through the channel, the resistance R ACC laterally through the accumulation region, the resistance R JFET vertically through the pinched portion of the N type epitaxial region 1A between the two adjacent P body regions, the resistance R DRIFr vertically through the remainder of the N type epitaxial region 1A to the substrate, and the resistance R s ⁇ B vertically through the substrate to the drain electrode.
- the resistance R, ⁇ in the trench structure is made up of the resistance Rc H vertically through the channel, the resistance R ACC vertically through the accumulation region, the resistance R DWFT vertically through the remainder of the N type epitaxial region 1A, and the resistance R SUB vertically through the substrate to the drain electrode.
- R JFET is eliminated in the trench device. Because the conductivity of silicon increases with dopant concentration, epitaxial silicon layer 1 is relatively heavily doped to reduce the R DRIFT and thereby reduce R DSO ...
- the channel region of the P body region of a trench field effect transistor is formed in a layer of lightly doped epitaxial silicon.
- the channel region has less counterdoping from the background N type epitaxial silicon dopants and has a greater net P type dopant concentration. Due to the higher net P type dopant concentration of the P body region, the depletion regions on either side of the P body region expand less far inward through the P body region at a given voltage, thereby rendering the transistor less susceptible to source-to-drain punchthrough.
- the relatively high conductivity of an accumulation region formed along a sidewall of the trench of the transistor when the transistor is on is used to form a conductive path from the channel region to an underlying relatively highly conductive layer upon which the lightly doped epitaxial layer is formed.
- This underlying relatively highly conductive layer may, for example, be either substrate or a more heavily doped epitaxial silicon layer.
- Some embodiments have low threshold voltages (such as 0.6 to 1.0 volts) and are usable in low voltage battery applications (2.5 to 3.3 volts). Other details of structures and associated methods are also disclosed.
- Figure 1 is a cross-sectional diagram of a planar double diffused field effect transistor.
- Figure 2 (Prior Art) is a cross-sectional diagram of a trench double diffused field effect transistor.
- Figure 3 is a simplified cross-sectional diagram of a planar double diffused field effect transistor.
- Figure 4 is a simplified cross-sectional diagram of a trench double diffused field effect transistor formed in a double epitaxial layer structure in accordance with another embodiment of the present invention.
- Figure 5 is an approximate dopant profile taken along line A-A of Figure 4.
- Figure 6 is a simplified cross-sectional diagram of a trench double diffused field effect transistor formed in a single epitaxial layer structure in accordance with yet another embodiment of the present invention.
- Figure 7 is an approximate dopant profile taken along line B-B of Figure 6.
- Figure 3 is a simplified cross-sectional diagram of a planar double diffused field effect transistor.
- a lightly doped N- type epitaxial layer 101 is disposed on a more heavily doped N type epitaxial layer 102 which is in turn disposed on a more heavily doped N+ type substrate layer 103.
- a P body region 104 is formed into the epitaxial layers 101 and 102 from upper surface 105 to form a relatively heavily doped epitaxial region 102A and a relatively lightly doped epitaxial region 101A.
- P body region is understood to entail a relatively lightly doped doubly diffused portion and a more highly doped body portion which correspond with regions 3A and 3B of Figure 2, respectively.
- the dashed lines in Figures 4 and 6 similarly indicate that each of those P body regions actually comprises a relatively lightly doped portion and more highly doped portion.
- N+ type source region 106 is then formed into P body region 104 from upper surface 105.
- the drain 107 is located on the underside of the substrate 103.
- the conventional gate (as in Figure 1) and contacts and other possible layers are not illustrated to improve the clarity of the diagram.
- Relatively lightly doped N- type epitaxial layer 101 can be either an ion implanted counterdoped portion of layer 102 or it can be grown having its relatively light dopant concentration. A depletion region expands less far for a given voltage in a relatively heavily doped silicon than it would for that given voltage in a relatively lightly doped silicon. Accordingly, the upper portion 104A (in which the channel region is disposed) has a higher net doping.
- the relatively lightly doped epitaxial silicon layer 101 is provided so that there will be less background counterdoping of the P body dopants in upper portion 104A. Accordingly, the region 104A of the P body region has a higher net doping concentration and the depletion regions do not punchthrough as easily from source region 106 to region 101A. Furthermore, to maintain a low R D ⁇ the resistance R DRIFr is maintained at a low value due to the use of the relatively heavily doped epitaxial layer 102. Both improved punchthrough resistance as well as low R DSon is therefore achieved.
- U.S. Patent Appl. Ser. No. 08/131,114 entitled "Low Threshold Voltage Epitaxial DMOS Technology" the subject matter of which is incorporated herein by reference.
- FIG. 3 The structure of Figure 3, however, involves the higher resistances through the relatively lightly doped N- epitaxial layer region 101A.
- the structure of Figure 3 is disclosed in the copending application serial number 08/131,114, the subject matter of which is incorporated herein by reference. To eliminate these high resistances of region 101A in the path the drain-to-source current, the structure of Figure 4 is provided.
- Figure 4 is a simplified cross-sectional diagram of a trench double diffused field effect transistor which does not incur the resistance penalty that the transistor of Figure 3 does.
- a lightly doped N- type epitaxial layer 201 is disposed on a more heavily doped N type epitaxial layer 202 which is in turn disposed on a more heavily doped N+ type substrate layer 203.
- a P body region 204 is formed into the epitaxial layers 201 and 202 from upper surface 205 to form a relatively heavily doped epitaxial region 202A and a relatively light doped epitaxial region 201A.
- N+ type source region 206 is formed into P body region 204 from upper surface 205.
- the drain 207 is located on the underside of the substrate 203.
- Relatively lightly doped N- type epitaxial layer 201 can be either an ion implanted counterdoped portion of epitaxial layer 202 or it can be grown having its final relatively light dopant concentration.
- a trench is etched into surface 205 and a gate oxide 208 and gate 209 are formed as in the trench transistor structure of Figure 2. See U.S. Patent No. 5,072,266, the contents of which are incorporated herein by reference, for details on fabricating a trench field effect transistor.
- the structure of Figure 4 does not incur the resistance penalty associated with the planar structure of Figure 3 because electron flow proceeds through the N- type epitaxial region 201A in an accumulation region along the sidewall of the trench.
- the resistance in an accumulation region is substantially independent of dopant concentration.
- the gate/trench structure therefore forms a means for controllably forming the accumulation region. After the electrons have passed through the N- type epitaxial region 201A, the electrons pass through the relatively heavily doped N type epitaxial region 202A where the resistance is also low.
- Figure 5 is a diagram showing an approximate dopant profile along the line labeled A-A in Figure 4.
- the 3-9E15 dopant concentration is the approximate dopant concentration of the relatively lightly doped N- type epitaxial region 201A of Figure 4.
- the net peak doping concentration in the channel region of P body region 204 is 3-9E16. Dopant concentrations are in atoms/cm 3 .
- FIG. 6 is a simplified cross-sectional diagram of a trench double diffused field effect transistor in accordance with another embodiment of the present invention.
- the gate region 209A extends into the N+ type substrate 203. Only one epitaxial layer, a relatively lightly doped N- type epitaxial layer 201, is used. Electrons flow vertically in the low resistance accumulation region at the sidewall of the trench from the low resistance channel region in P body region 204 downward to the N+ substrate 203.
- a specific R DS ⁇ , in the range of 0.1 to 0.5 ohms-cm 2 is achievable in a device having a breakdown voltage in the range of 15 to 30 volts and a threshold voltage in the range of 0.6 to 1.0 volts.
- Figure 7 is a diagram showing an approximate dopant profile along the line labeled B-B in Figure 6.
- the 3-9E15 dopant concentration is the dopant concentration of the relatively lightly doped N- type epitaxial region 201A of Figure 6. Due to the heavily doped N+ type substrate 203 being in close proximity to gate 209A, a relatively high electric field develops between gate 209A and N+ substrate 203 as compared to the electric field developed between gate 209 and N type epitaxial region 202A of Figure 4.
- the net P type peak doping concentration in the channel region of P type body region 204 is 3-9E16.
- F.igure 6 has the advantage of not requiring the double epitaxial layer structure in relatively low source-to-drain voltage applications (such as 12-30 volts).
- the structure of Figure 4 is usable in relatively high source-to- drain voltage applications (up to approximately 60 volts) .
- Approximate thickness ranges for the embodiment of Figure 4 are 0.5 microns for source region 206, 1.0-2.0 microns for P body region 204 at the trench sidewall, 1.0-3.0 microns from the bottom of the P body region at the sidewall to the top of N+ substrate layer 203.
- the gate oxide may, for example, be 150-1000 angstroms thick.
- the trench may be, for example, 1.2-2.0 microns deep.
- Epitaxial layers 201 and 202 may be a combined 4.0-12.0 microns thick. The short channel renders the transistor usable in low threshold voltage applications such as battery applications.
- Approximate thickness ranges for the embodiment of Figure 6 are 0.5 microns for source region 206, 1.0-2.0 microns for P body region 204 at the trench sidewall, 1.0-2.0 microns from the bottom of the P body region at the sidewall to the top of N+ substrate layer 203.
- the gate oxide may, for example, be 150-1000 angstroms thick.
- the trench may be approximately 1.2-6.0 microns deep.
- the bottom of the trench may be approximately 0.5-1.0 microns from the top of N+ type substrate layer 203.
- Epitaxial layer 201 may be approximately 2.0-5.0 microns thick. The short channel renders the transistor usable in low threshold voltage applications such as battery applications.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP96906189A EP0808513A4 (en) | 1995-02-10 | 1996-02-07 | TRENCH FIELD EFFECT TRANSISTOR WITH REDUCED PUNCH-THROUGH SUSCEPTIBILITY AND LOW R DSon? |
JP08524276A JP3108439B2 (en) | 1995-02-10 | 1996-02-07 | Trench field-effect transistor with reduced punch-through and low RDSon |
AU49650/96A AU4965096A (en) | 1995-02-10 | 1996-02-07 | Trench field effect transistor with reduced punch-through susceptibility and low rdson |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/386,895 | 1995-02-10 | ||
US08/386,895 US5558313A (en) | 1992-07-24 | 1995-02-10 | Trench field effect transistor with reduced punch-through susceptibility and low RDSon |
Publications (2)
Publication Number | Publication Date |
---|---|
WO1996024953A1 true WO1996024953A1 (en) | 1996-08-15 |
WO1996024953B1 WO1996024953B1 (en) | 1996-10-03 |
Family
ID=23527518
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1996/000941 WO1996024953A1 (en) | 1995-02-10 | 1996-02-07 | TRENCH FIELD EFFECT TRANSISTOR WITH REDUCED PUNCH-THROUGH SUSCEPTIBILITY AND LOW R¿DSon? |
Country Status (6)
Country | Link |
---|---|
US (2) | US5558313A (en) |
EP (1) | EP0808513A4 (en) |
JP (1) | JP3108439B2 (en) |
AU (1) | AU4965096A (en) |
CA (1) | CA2212765A1 (en) |
WO (1) | WO1996024953A1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7649222B2 (en) | 2006-12-25 | 2010-01-19 | Sanyo Electric Co., Ltd. | Semiconductor device |
CN106409675A (en) * | 2016-09-08 | 2017-02-15 | 深圳深爱半导体股份有限公司 | Production method for depletion mode power transistor |
Families Citing this family (65)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5844273A (en) * | 1994-12-09 | 1998-12-01 | Fuji Electric Co. | Vertical semiconductor device and method of manufacturing the same |
US5688725A (en) * | 1994-12-30 | 1997-11-18 | Siliconix Incorporated | Method of making a trench mosfet with heavily doped delta layer to provide low on-resistance |
DE69631995T2 (en) * | 1995-06-02 | 2005-02-10 | Siliconix Inc., Santa Clara | Bidirectionally blocking trench power MOSFET |
US5679966A (en) * | 1995-10-05 | 1997-10-21 | North Carolina State University | Depleted base transistor with high forward voltage blocking capability |
US5637898A (en) * | 1995-12-22 | 1997-06-10 | North Carolina State University | Vertical field effect transistors having improved breakdown voltage capability and low on-state resistance |
US5821583A (en) * | 1996-03-06 | 1998-10-13 | Siliconix Incorporated | Trenched DMOS transistor with lightly doped tub |
US5904525A (en) * | 1996-05-08 | 1999-05-18 | Siliconix Incorporated | Fabrication of high-density trench DMOS using sidewall spacers |
US5742076A (en) * | 1996-06-05 | 1998-04-21 | North Carolina State University | Silicon carbide switching devices having near ideal breakdown voltage capability and ultralow on-state resistance |
JP2000515684A (en) * | 1996-07-19 | 2000-11-21 | シリコニックス・インコーポレイテッド | High density trench DMOS transistor with trench bottom implant region |
KR19980014820A (en) * | 1996-08-16 | 1998-05-25 | 김광호 | Tungsten-type MOS field effect transistor and manufacturing method thereof |
KR100243741B1 (en) * | 1996-12-27 | 2000-02-01 | 김영환 | Manufacturing method of a semiconductor device |
US6570185B1 (en) * | 1997-02-07 | 2003-05-27 | Purdue Research Foundation | Structure to reduce the on-resistance of power transistors |
US6096608A (en) * | 1997-06-30 | 2000-08-01 | Siliconix Incorporated | Bidirectional trench gated power mosfet with submerged body bus extending underneath gate trench |
JP3502531B2 (en) | 1997-08-28 | 2004-03-02 | 株式会社ルネサステクノロジ | Method for manufacturing semiconductor device |
KR100304716B1 (en) * | 1997-09-10 | 2001-11-02 | 김덕중 | Diode by controlled metal oxide semiconductor & method of fabrication the same |
US6031265A (en) * | 1997-10-16 | 2000-02-29 | Magepower Semiconductor Corp. | Enhancing DMOS device ruggedness by reducing transistor parasitic resistance and by inducing breakdown near gate runners and termination area |
US6103635A (en) * | 1997-10-28 | 2000-08-15 | Fairchild Semiconductor Corp. | Trench forming process and integrated circuit device including a trench |
US6429481B1 (en) * | 1997-11-14 | 2002-08-06 | Fairchild Semiconductor Corporation | Field effect transistor and method of its manufacture |
US6376293B1 (en) * | 1999-03-30 | 2002-04-23 | Texas Instruments Incorporated | Shallow drain extenders for CMOS transistors using replacement gate design |
US7084456B2 (en) * | 1999-05-25 | 2006-08-01 | Advanced Analogic Technologies, Inc. | Trench MOSFET with recessed clamping diode using graded doping |
US6191447B1 (en) | 1999-05-28 | 2001-02-20 | Micro-Ohm Corporation | Power semiconductor devices that utilize tapered trench-based insulating regions to improve electric field profiles in highly doped drift region mesas and methods of forming same |
US6376315B1 (en) * | 2000-03-31 | 2002-04-23 | General Semiconductor, Inc. | Method of forming a trench DMOS having reduced threshold voltage |
US7745289B2 (en) | 2000-08-16 | 2010-06-29 | Fairchild Semiconductor Corporation | Method of forming a FET having ultra-low on-resistance and low gate charge |
US6437386B1 (en) * | 2000-08-16 | 2002-08-20 | Fairchild Semiconductor Corporation | Method for creating thick oxide on the bottom surface of a trench structure in silicon |
US6818513B2 (en) | 2001-01-30 | 2004-11-16 | Fairchild Semiconductor Corporation | Method of forming a field effect transistor having a lateral depletion structure |
US6803626B2 (en) | 2002-07-18 | 2004-10-12 | Fairchild Semiconductor Corporation | Vertical charge control semiconductor device |
US6916745B2 (en) | 2003-05-20 | 2005-07-12 | Fairchild Semiconductor Corporation | Structure and method for forming a trench MOSFET having self-aligned features |
US6713351B2 (en) * | 2001-03-28 | 2004-03-30 | General Semiconductor, Inc. | Double diffused field effect transistor having reduced on-resistance |
US20030151092A1 (en) * | 2002-02-11 | 2003-08-14 | Feng-Tso Chien | Power mosfet device with reduced snap-back and being capable of increasing avalanche-breakdown current endurance, and method of manafacturing the same |
DE10239862B4 (en) * | 2002-08-29 | 2007-03-15 | Infineon Technologies Ag | Trench transistor cell, transistor arrangement and method for producing a transistor arrangement |
US7576388B1 (en) | 2002-10-03 | 2009-08-18 | Fairchild Semiconductor Corporation | Trench-gate LDMOS structures |
US6710418B1 (en) | 2002-10-11 | 2004-03-23 | Fairchild Semiconductor Corporation | Schottky rectifier with insulation-filled trenches and method of forming the same |
US7652326B2 (en) | 2003-05-20 | 2010-01-26 | Fairchild Semiconductor Corporation | Power semiconductor devices and methods of manufacture |
KR100994719B1 (en) | 2003-11-28 | 2010-11-16 | 페어차일드코리아반도체 주식회사 | Superjunction semiconductor device |
US7368777B2 (en) | 2003-12-30 | 2008-05-06 | Fairchild Semiconductor Corporation | Accumulation device with charge balance structure and method of forming the same |
US7041561B2 (en) * | 2004-03-31 | 2006-05-09 | Agere Systems Inc. | Enhanced substrate contact for a semiconductor device |
JP2005302925A (en) * | 2004-04-09 | 2005-10-27 | Toshiba Corp | Semiconductor device |
US7352036B2 (en) | 2004-08-03 | 2008-04-01 | Fairchild Semiconductor Corporation | Semiconductor power device having a top-side drain using a sinker trench |
DE102005009000B4 (en) * | 2005-02-28 | 2009-04-02 | Infineon Technologies Austria Ag | Trench structural type vertical semiconductor device and manufacturing method |
JP2008536316A (en) | 2005-04-06 | 2008-09-04 | フェアチャイルド・セミコンダクター・コーポレーション | Trench gate field effect transistor and method of forming the same |
KR101296922B1 (en) | 2005-06-10 | 2013-08-14 | 페어차일드 세미컨덕터 코포레이션 | Charge balance field effect transistor |
JP5008046B2 (en) * | 2005-06-14 | 2012-08-22 | ローム株式会社 | Semiconductor device |
KR101142104B1 (en) * | 2006-02-23 | 2012-05-03 | 비쉐이-실리코닉스 | Process for forming a short channel trench mosfet and device |
US7446374B2 (en) | 2006-03-24 | 2008-11-04 | Fairchild Semiconductor Corporation | High density trench FET with integrated Schottky diode and method of manufacture |
US7319256B1 (en) | 2006-06-19 | 2008-01-15 | Fairchild Semiconductor Corporation | Shielded gate trench FET with the shield and gate electrodes being connected together |
KR100881015B1 (en) * | 2006-11-30 | 2009-01-30 | 동부일렉트로닉스 주식회사 | Semiconductor device and method for fabricating the same |
JP2008218711A (en) * | 2007-03-05 | 2008-09-18 | Renesas Technology Corp | Semiconductor device, its manufacturing method, and power supply device |
EP2208229A4 (en) | 2007-09-21 | 2011-03-16 | Fairchild Semiconductor | Superjunction structures for power devices and methods of manufacture |
US7772668B2 (en) * | 2007-12-26 | 2010-08-10 | Fairchild Semiconductor Corporation | Shielded gate trench FET with multiple channels |
US20120273916A1 (en) | 2011-04-27 | 2012-11-01 | Yedinak Joseph A | Superjunction Structures for Power Devices and Methods of Manufacture |
US8174067B2 (en) | 2008-12-08 | 2012-05-08 | Fairchild Semiconductor Corporation | Trench-based power semiconductor devices with increased breakdown voltage characteristics |
US10026835B2 (en) | 2009-10-28 | 2018-07-17 | Vishay-Siliconix | Field boosted metal-oxide-semiconductor field effect transistor |
JP4791572B2 (en) * | 2009-12-21 | 2011-10-12 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
US8432000B2 (en) | 2010-06-18 | 2013-04-30 | Fairchild Semiconductor Corporation | Trench MOS barrier schottky rectifier with a planar surface using CMP techniques |
JP2010283368A (en) * | 2010-07-26 | 2010-12-16 | Renesas Electronics Corp | Method of manufacturing semiconductor device |
US8487371B2 (en) | 2011-03-29 | 2013-07-16 | Fairchild Semiconductor Corporation | Vertical MOSFET transistor having source/drain contacts disposed on the same side and method for manufacturing the same |
US8673700B2 (en) | 2011-04-27 | 2014-03-18 | Fairchild Semiconductor Corporation | Superjunction structures for power devices and methods of manufacture |
US8836028B2 (en) | 2011-04-27 | 2014-09-16 | Fairchild Semiconductor Corporation | Superjunction structures for power devices and methods of manufacture |
US8786010B2 (en) | 2011-04-27 | 2014-07-22 | Fairchild Semiconductor Corporation | Superjunction structures for power devices and methods of manufacture |
US8772868B2 (en) | 2011-04-27 | 2014-07-08 | Fairchild Semiconductor Corporation | Superjunction structures for power devices and methods of manufacture |
US8816431B2 (en) | 2012-03-09 | 2014-08-26 | Fairchild Semiconductor Corporation | Shielded gate MOSFET device with a funnel-shaped trench |
JP2014075483A (en) * | 2012-10-04 | 2014-04-24 | Sanken Electric Co Ltd | Semiconductor device and semiconductor device manufacturing method |
US9847233B2 (en) * | 2014-07-29 | 2017-12-19 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor device and formation thereof |
JP6674395B2 (en) * | 2017-02-03 | 2020-04-01 | 株式会社東芝 | Semiconductor device |
CN112186035B (en) * | 2019-07-04 | 2022-03-29 | 长鑫存储技术有限公司 | Storage device, recessed channel array transistor and preparation method thereof |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4593302A (en) * | 1980-08-18 | 1986-06-03 | International Rectifier Corporation | Process for manufacture of high power MOSFET with laterally distributed high carrier density beneath the gate oxide |
US4680853A (en) * | 1980-08-18 | 1987-07-21 | International Rectifier Corporation | Process for manufacture of high power MOSFET with laterally distributed high carrier density beneath the gate oxide |
US4803532A (en) * | 1982-11-27 | 1989-02-07 | Nissan Motor Co., Ltd. | Vertical MOSFET having a proof structure against puncture due to breakdown |
US5072266A (en) * | 1988-12-27 | 1991-12-10 | Siliconix Incorporated | Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry |
US5138422A (en) * | 1987-10-27 | 1992-08-11 | Nippondenso Co., Ltd. | Semiconductor device which includes multiple isolated semiconductor segments on one chip |
US5168331A (en) * | 1991-01-31 | 1992-12-01 | Siliconix Incorporated | Power metal-oxide-semiconductor field effect transistor |
Family Cites Families (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4078947A (en) * | 1976-08-05 | 1978-03-14 | International Business Machines Corporation | Method for forming a narrow channel length MOS field effect transistor |
JPS5553462A (en) * | 1978-10-13 | 1980-04-18 | Int Rectifier Corp | Mosfet element |
US4705759B1 (en) * | 1978-10-13 | 1995-02-14 | Int Rectifier Corp | High power mosfet with low on-resistance and high breakdown voltage |
US5191396B1 (en) * | 1978-10-13 | 1995-12-26 | Int Rectifier Corp | High power mosfet with low on-resistance and high breakdown voltage |
JPS5567161A (en) * | 1978-11-14 | 1980-05-21 | Seiko Epson Corp | Semiconductor memory storage |
JPS55146976A (en) * | 1979-05-02 | 1980-11-15 | Nec Corp | Insulating gate field effect transistor |
US5008725C2 (en) * | 1979-05-14 | 2001-05-01 | Internat Rectifer Corp | Plural polygon source pattern for mosfet |
JPS5658267A (en) * | 1979-10-17 | 1981-05-21 | Nippon Telegr & Teleph Corp <Ntt> | Insulated gate type field-effect transistor |
JPS57153469A (en) * | 1981-03-18 | 1982-09-22 | Toshiba Corp | Insulated gate type field effect transistor |
JPS57188877A (en) * | 1981-05-18 | 1982-11-19 | Nec Corp | Semiconductor device and manufacture thereof |
JPS5984474A (en) * | 1982-11-05 | 1984-05-16 | Nec Corp | Vertical type field effect transistor for power |
JPS62176168A (en) * | 1986-01-30 | 1987-08-01 | Nippon Denso Co Ltd | Vertical mos transistor |
US4767722A (en) * | 1986-03-24 | 1988-08-30 | Siliconix Incorporated | Method for making planar vertical channel DMOS structures |
US5017504A (en) * | 1986-12-01 | 1991-05-21 | Mitsubishi Denki Kabushiki Kaisha | Vertical type MOS transistor and method of formation thereof |
US4941026A (en) * | 1986-12-05 | 1990-07-10 | General Electric Company | Semiconductor devices exhibiting minimum on-resistance |
JPS6442177A (en) * | 1987-08-10 | 1989-02-14 | Hitachi Ltd | Insulated gate transistor |
US4893160A (en) * | 1987-11-13 | 1990-01-09 | Siliconix Incorporated | Method for increasing the performance of trenched devices and the resulting structure |
JP2771172B2 (en) * | 1988-04-01 | 1998-07-02 | 日本電気株式会社 | Vertical field-effect transistor |
JPH0783118B2 (en) * | 1988-06-08 | 1995-09-06 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
US5386136A (en) * | 1991-05-06 | 1995-01-31 | Siliconix Incorporated | Lightly-doped drain MOSFET with improved breakdown characteristics |
GB9215653D0 (en) * | 1992-07-23 | 1992-09-09 | Philips Electronics Uk Ltd | A method of manufacturing a semiconductor device comprising an insulated gate field effect device |
US5910669A (en) * | 1992-07-24 | 1999-06-08 | Siliconix Incorporated | Field effect Trench transistor having lightly doped epitaxial region on the surface portion thereof |
KR940004847A (en) * | 1992-08-04 | 1994-03-16 | 리차드 제이. 컬 | A method of forming an epitaxial double diffusion metal oxide (DMOS) transistor structure having a low threshold hold voltage |
US5341011A (en) * | 1993-03-15 | 1994-08-23 | Siliconix Incorporated | Short channel trenched DMOS transistor |
JPH07122749A (en) * | 1993-09-01 | 1995-05-12 | Toshiba Corp | Semiconductor device and its manufacture |
US5405794A (en) * | 1994-06-14 | 1995-04-11 | Philips Electronics North America Corporation | Method of producing VDMOS device of increased power density |
US5674766A (en) * | 1994-12-30 | 1997-10-07 | Siliconix Incorporated | Method of making a trench MOSFET with multi-resistivity drain to provide low on-resistance by varying dopant concentration in epitaxial layer |
JPH08213607A (en) * | 1995-02-08 | 1996-08-20 | Ngk Insulators Ltd | Semiconductor device and its manufacturing method |
-
1995
- 1995-02-10 US US08/386,895 patent/US5558313A/en not_active Expired - Lifetime
-
1996
- 1996-02-07 WO PCT/US1996/000941 patent/WO1996024953A1/en not_active Application Discontinuation
- 1996-02-07 EP EP96906189A patent/EP0808513A4/en not_active Withdrawn
- 1996-02-07 JP JP08524276A patent/JP3108439B2/en not_active Expired - Lifetime
- 1996-02-07 AU AU49650/96A patent/AU4965096A/en not_active Abandoned
- 1996-02-07 CA CA002212765A patent/CA2212765A1/en not_active Abandoned
- 1996-06-04 US US08/658,115 patent/US5981344A/en not_active Expired - Lifetime
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4593302A (en) * | 1980-08-18 | 1986-06-03 | International Rectifier Corporation | Process for manufacture of high power MOSFET with laterally distributed high carrier density beneath the gate oxide |
US4680853A (en) * | 1980-08-18 | 1987-07-21 | International Rectifier Corporation | Process for manufacture of high power MOSFET with laterally distributed high carrier density beneath the gate oxide |
US4593302B1 (en) * | 1980-08-18 | 1998-02-03 | Int Rectifier Corp | Process for manufacture of high power mosfet laterally distributed high carrier density beneath the gate oxide |
US4803532A (en) * | 1982-11-27 | 1989-02-07 | Nissan Motor Co., Ltd. | Vertical MOSFET having a proof structure against puncture due to breakdown |
US5138422A (en) * | 1987-10-27 | 1992-08-11 | Nippondenso Co., Ltd. | Semiconductor device which includes multiple isolated semiconductor segments on one chip |
US5072266A (en) * | 1988-12-27 | 1991-12-10 | Siliconix Incorporated | Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry |
US5168331A (en) * | 1991-01-31 | 1992-12-01 | Siliconix Incorporated | Power metal-oxide-semiconductor field effect transistor |
Non-Patent Citations (1)
Title |
---|
See also references of EP0808513A4 * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7649222B2 (en) | 2006-12-25 | 2010-01-19 | Sanyo Electric Co., Ltd. | Semiconductor device |
CN106409675A (en) * | 2016-09-08 | 2017-02-15 | 深圳深爱半导体股份有限公司 | Production method for depletion mode power transistor |
Also Published As
Publication number | Publication date |
---|---|
EP0808513A1 (en) | 1997-11-26 |
CA2212765A1 (en) | 1996-08-15 |
AU4965096A (en) | 1996-08-27 |
JPH10507880A (en) | 1998-07-28 |
EP0808513A4 (en) | 1998-10-07 |
US5558313A (en) | 1996-09-24 |
US5981344A (en) | 1999-11-09 |
JP3108439B2 (en) | 2000-11-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5981344A (en) | Trench field effect transistor with reduced punch-through susceptibility and low RDSon | |
US5688725A (en) | Method of making a trench mosfet with heavily doped delta layer to provide low on-resistance | |
US7365402B2 (en) | LDMOS transistor | |
US8076719B2 (en) | Semiconductor device structures and related processes | |
US6008520A (en) | Trench MOSFET with heavily doped delta layer to provide low on- resistance | |
EP0885460B1 (en) | Trenched dmos transistor with lightly doped tub | |
US20040036138A1 (en) | High voltage power MOSFET having low on-resistance | |
US20090206913A1 (en) | Edge Termination with Improved Breakdown Voltage | |
US20040070044A1 (en) | High voltage power MOSFET having low on-resistance | |
US20030057478A1 (en) | Mos-gated power semiconductor device | |
US20030122189A1 (en) | High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching using an etchant gas that is also a doping source | |
KR930009101A (en) | Improved horizontally lateral double-diffusion MOS transistor and its manufacturing method | |
KR100194661B1 (en) | Power transistor | |
WO1996024953B1 (en) | TRENCH FIELD EFFECT TRANSISTOR WITH REDUCED PUNCH-THROUGH SUSCEPTIBILITY AND LOW R¿DSon? | |
US5583365A (en) | Fully depleted lateral transistor | |
US20040097019A1 (en) | Semiconductor component and method of manufacturing | |
US6989567B2 (en) | LDMOS transistor | |
KR100701712B1 (en) | Lateral thin-film silicon-on-insulator soi device having lateral depletion | |
US6559502B2 (en) | Semiconductor device | |
US5008719A (en) | Dual layer surface gate JFET having enhanced gate-channel breakdown voltage | |
US9871135B2 (en) | Semiconductor device and method of making | |
JP2003518749A (en) | Silicon carbide LMOSFET with gate breakdown protection | |
US5750416A (en) | Method of forming a lateral field effect transistor having reduced drain-to-source on-resistance | |
US7579649B2 (en) | Trench field effect transistor and method of making it | |
US5118632A (en) | Dual layer surface gate JFET having enhanced gate-channel breakdown voltage |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): AL AM AT AU AZ BB BG BR BY CA CH CN CZ DE DK EE ES FI GB GE HU IS JP KE KG KP KR KZ LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK TJ TM TT UA UG UZ VN AZ BY KG KZ RU TJ TM |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): KE LS MW SD SZ UG AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN ML MR NE SN TD |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
ENP | Entry into the national phase |
Ref document number: 2212765 Country of ref document: CA Ref country code: CA Ref document number: 2212765 Kind code of ref document: A Format of ref document f/p: F |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1996906189 Country of ref document: EP |
|
WWP | Wipo information: published in national office |
Ref document number: 1996906189 Country of ref document: EP |
|
REG | Reference to national code |
Ref country code: DE Ref legal event code: 8642 |
|
WWW | Wipo information: withdrawn in national office |
Ref document number: 1996906189 Country of ref document: EP |