WO1996031883A1 - A method for programming an amg eprom or flash memory when cells of the array are formed to store multiple bits of data - Google Patents
A method for programming an amg eprom or flash memory when cells of the array are formed to store multiple bits of data Download PDFInfo
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- WO1996031883A1 WO1996031883A1 PCT/US1996/004843 US9604843W WO9631883A1 WO 1996031883 A1 WO1996031883 A1 WO 1996031883A1 US 9604843 W US9604843 W US 9604843W WO 9631883 A1 WO9631883 A1 WO 9631883A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0491—Virtual ground arrays
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
- G11C11/5635—Erasing circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/562—Multilevel memory programming aspects
- G11C2211/5622—Concurrent multilevel programming of more than one cell
Definitions
- the present invention relates to programming an altemate-metal virtual-ground (AMG) EPROM or flash memory and, more particularly, to a method for programming these memories when cells of the array are formed to store multiple bits of data, i.e., more than a logic "1 " and a logic "0".
- AMG an altemate-metal virtual-ground
- An altemate-metal virtual-ground (AMG) array architecture is a type of non-volatile memory architecture that is characterized by metal which only contacts every other bit line of the array.
- the AMG array architecture can be utilized with both U-V erasable EPROMs as well as flash memories.
- FIG. 1 shows a portion of a conventional AMG array 10.
- array 10 includes a plurality of contacted bit lines BLC, a plurality of non-contacted bit lines BLU formed so that one non- contacted bit line BLU is positioned between each pair of contacted bit lines BLC, a plurality of memory cells 12, and a plurality of access transistors 14.
- the contacted bit lines BLC directly contact a metal line ML
- the non-contacted bit lines BLU contact a metal line ML via one of the access transistors 14.
- Memory cells 12 are arranged in columns and rows so that a predetermined number of cells 12 are formed between each pair of contacted and non-contacted bit lines BLC and BLU.
- Access transistors 14, on the other hand are arranged in columns and rows so that in each row only one transistor 14 is formed between every other pair of contacted and non-contacted bit lines BLC and BLU.
- Array 10 further includes a series of word lines WLl-WLn which are formed so that one word line WL is formed over each of the memory cells 12 in a row of memory cells.
- the portion of the word line 18 which is formed over each memory cell 12 functions as the control gate of that memory cell.
- the access transistors 14 in a row of access transistors 14 share one of four access lines AC 1-AC4.
- a cell in array 10 is conventionally programmed to store one bit of data by selecting the cell to be programmed, and then applying a programming voltage to the word line that corresponds to the cell to be programmed.
- the contacted bit line BLC that adjoins cell A is held at an intermediate voltage Vd (approximately 5-7V), while the contacted bit line BLC positioned on the opposite side of cell A is held at ground Vss.
- the remaining contacted bit lines BLC are allowed to float.
- access lines AC2 and AC3 are biased to the supply voltage Vcc (approximately 5V), while access lines AC1 and AC4 are held at ground Vss. This, in turn, pulls the non-contacted bit line
- the programming voltage Vpp (approximately 12V) is then applied to word line WL1, while the remaining word lines WL2-WLn are grounded. These bias conditions result in current flow as shown by the arrow in FIG. 1, which results in electron injection from the drain of cell A to the floating gate of cell A, thus programming cell A.
- One drawback to programming memory cells 12 as described above is that only one bit of data can be programmed into a cell, and only one cell in a column of cells can be programmed at any one time. Although it would appear that multiple cells in a column could be simultaneously programmed by applying the programming voltage Vpp to the word lines WL2-WLn that correspond to each cell in the column to be programmed, the high current requirements of each cell during programming (approximately 400mA) preclude this. Thus, there is a need for a method of programming multiple cells in a column of an AMG array at the same time.
- the present invention provides a method for simultaneously programming any combination of memory cells in a column of cells in an alternate-metal virtual-ground (AMG) EPROM or flash memory to each store one of three or more threshold voltages, i.e., logic levels.
- AMG alternate-metal virtual-ground
- any combination of memory cells in a column can be simultaneously programmed to store, for example, a logic "0-0", a "0-1 ", a "1-0", or a "1-1”.
- the array which is formed in a well, includes a plurality of metal contacted bit lines, and a plurality of non-contacted bit lines which are formed so that one non-contacted bit line is formed between each adjacent pair of metal contacted bit lines.
- the array also includes a plurality of memory cells which are formed in columns and rows so that each column of memory cells is formed between and contacts adjacent pairs of metal contacted and non-contacted bit lines.
- a plurality of access transistors are also formed in columns and rows so that one access transistor is formed at each end of each column of memory cells.
- each row of access transistors is formed so that one access transistor is formed between and contacts every other pair of metal contacted and non-contacted bit lines.
- the array further includes a plurality of access lines and a plurality of word line. The access lines are formed so that each row of access transistors is contacted by a corresponding access line, while the of word lines are formed so that each row of memory cells is contacted by a corresponding word line.
- each cell is formed to produce a punchthrough current during programming.
- a method for simultaneously programming any combination of memory cells in a column to each store one of three or more threshold voltages includes the step of selecting a programming voltage from three or more programming voltages for each of a plurality of cells in a column that are to be programmed.
- the three or more programming voltages correspond to the three or more threshold voltages.
- each cell in the column that is to be programmed has a corresponding word line.
- the method continues with the step of applying a first voltage to a first metal contacted bit line.
- the first metal contacted bit line contacts each memory cell and each access transistor in a first column of a pair of adjacent columns where the first column includes the cells to be programmed.
- a second voltage which is less than the first voltage, is applied to a second metal contacted bit line.
- the second metal contacted bit line contacts each memory cell and access transistor in a second column of the pair of adjacent columns.
- the second voltage is also applied to the well.
- the method further continues with the step of applying a third voltage to a pair of access lines where each access line of the pair of access lines contacts an access transistor located in the second column of the pair of adjacent columns.
- Each cell is programmed to store one of the multiple logic levels by applying the programming voltages selected for the cells to be programmed to the word lines that correspond to the cells to be programmed.
- FIG. 1 is a plan view illustrating a portion of a conventional AMG array 10.
- FIG. 2 is a plan view illustrating a portion of an altemate-metal virtual-ground (AMG) array 100 in accordance with the present invention.
- AMG an altemate-metal virtual-ground
- FIG. 3 is a cross-sectional view illustrating the structure of one of the memory cells 1 12 from airay 100.
- FIG. 4 is a graphical representation illustrating a cell programming characterization curve.
- FIG. 5 is a graphical representation illustrating the amount of negative charge injected onto the floating gate for initial and final voltages V j and V2.
- FIG. 6 is a graphical representation illustrating the amount of negative charge injected onto the floating gate for initial voltages VQQ-VJ J and final voltage V ⁇ .
- FIG. 7 is a graphical representation illustrating a series of experimental results.
- FIG. 8 is a plan view illustrating segment select transistors in a portion of an altemate-metal virtual-ground (AMG) array 100 in accordance with the present invention.
- FIG. 2 shows a portion of an altemate-metal virtual-ground (AMG) array 100 in accordance with the present invention. As shown in FIG. 2, array 100, which can be utilized with both U-V erasable
- EPROMs as well as flash memories is divided into a series of segments SG l-SGm which each include a plurality of metal contacted bit lines BLC. and a plurality of non-contacted bit lines BLU which are formed so that one non-contacted bit line BLU is formed between each adjacent pair of metal contacted bit lines BLC.
- Each segment SG also includes a plurality of memory cells 1 12 and a plurality of access transistors
- the memory cells 1 12 are formed in columns and rows so that each column of memory cells 1 12 is formed between and contacts adjacent pairs of metal contacted and non-contacted bit lines BLC and BLU.
- the access transistors 1 14 are formed in columns and rows so that one access transistor 1 14 is formed at each end of each column of memory cells 1 12 in each segment SG.
- each row of access transistors 1 14 is formed so that one access transistor 1 14 is formed between and contacts every other pair of metal contacted and non-contacted bit lines BLC and BLU.
- each of the memory cells 1 12 in a row of cells 1 12 in a segment SG share one of a series of word lines WLl-WLn while each of the access transistors 1 14 in a row of transistors 1 14 share one of a series of access lines AC 1-AC4.
- the portion of the word line WL formed over each memory cell 1 12 functions as the control gate of that memory cell while the portion of the access line
- FIG. 3 shows the structure of one of the memory cells 1 12 from array 100.
- cell 1 12 is formed in a p-type well 120 which, in turn, is formed in an n-type substrate 1 18.
- Memory cell 1 12 includes an n-type source region 122, an n-type drain region 124, and a channel region 126 formed between the source and drain regions 122 and 124.
- cell 1 12 is formed to produce a punchthrough current during programming.
- the channel lengths and doping levels, as well as the bias conditions, which are required to produce a punchthrough current through channel region 126 are well known in the art.
- cell 1 12 preferably utilizes a channel length of 0.5-0.7 microns and a doping concentration of 1-2x10 p-type atoms.
- the channel length and the doping concentration can be reduced accordingly.
- cell 1 12 preferably utilizes a channel length of 0.2-0.4 microns and a doping
- memory cell 1 12 also includes a first insulation layer 130 formed over channel region 126, a floating gate 132 formed over insulation layer 130, a second insulation layer 134 formed over floating gate 132, and a control gate 136 (a portion of word line WL) formed over insulation layer 134.
- memory cell 112 is programmed to store one of three or more logic levels by maintaining an equilibrium across the source-to-well junction, reverse-biasing the drain-to-well junction, and applying one of a corresponding three or more programming voltages to control gate 136 during programming.
- memory cell 112 preferably utilizes a drain voltage that is 4-7 volts greater than the well voltage.
- well 120 and source 122 are preferably grounded.
- cell 112 preferably utilizes a drain voltage which is 2-4 volts greater than the well voltage.
- control gate 136 when one of the programming voltages is applied to control gate 136, a positive potential is induced on floating gate 132 which, in turn, attracts electrons from the doped p-type atoms in channel region 126 to the surface of well 120 to form a channel 140. This potential also repels holes from the doped impurity atoms and forms a depletion region 142.
- the present invention utilizes the punchthrough current to form substrate hot electrons which also collect on floating gate 132.
- the electric field reduces the potential energy barrier at the source-to-weil junction.
- the reduced potential energy barrier allows more majority carriers in source 122 to overcome the barrier which, in turn, produces the punchthrough current across the source-to-well junction.
- the electric field accelerates the electrons which, in turn, also have ionizing collisions that form substrate hot electrons.
- the positive potential on floating gate 132 also attracts these substrate hot electrons which penetrate insulation layer 130 and begin accumulating on floating gate 132.
- the flow of electrons generated by the punchthrough current does not depend on the existence of a channel or the relative positive charge on floating gate 132. As a result, the electrons associated with the punchthrough current continue to accumulate on floating gate 132 after channel 130 has been turned off.
- cell 112 is programmed by utilizing both channel hot electrons and substrate hot electrons to change the potential on floating gate 132.
- a significantly lower control gate voltage can be used during programming than is conventionally used to program a cell because fewer channel hot electrons need to be attracted to floating gate 132.
- FIG. 4 shows a graphical representation that illustrates a cell programming characterization curve.
- the voltage (V) on the floating gate influences the number of hot electrons (I) that are injected onto the floating gate.
- the primary consideration in programming memory cells is the time required to place a defined amount of negative charge on the floating gate of the cell.
- the typical memory cell is designed to utilize an initial floating gate voltage V, and a final floating gate voltage V ⁇ that are positioned on opposite sides of the peak of the curve shown in FIG. 4, thereby taking advantage of the maximum injection of hot electrons onto the floating gate.
- the initial floating gate voltage V ] represents the voltage capacitively coupled to the floating gate from the control gate
- the final floating gate voltage V 7 represents the initial voltage V j reduced by the accumulated negative charge.
- FIG. 5 shows a graphical representation that illustrates the amount of negative charge injected onto the floating gate for initial and final voltages V j and V 2 -
- the amount of charge injected on the floating gate can be determined by integrating under the curve from the initial voltage V j at time t Q to the final voltage V 2 at time t_ .
- FIG. 5 illustrates that any variation in the timing will cause a greater or lesser amount of negative charge to be injected onto the floating gate.
- a greater amount of charge will be injected.
- this additional (or lesser) amount of negative charge does not present any problems because the cell is only being programmed to one of two logic levels.
- any additional charge is acceptable.
- the present invention achieves multiple levels of injected charge by utilizing one of a plurality of initial voltages. Since the initial voltages are defined by the voltage capacitively coupled to the floating gate from the control gate, the initial voltages are selected by selecting one of a plurality of control voltages.
- FIG. 6 shows a graphical representation that illustrates the amount of negative charge injected onto the floating gate for initial voltages VQ -V , j and final voltage V 4 .
- the amount of negative charge injected on the floating gate can be determined by integrating under the curve from each of the initial voltages VQ -V , , at time t to the final voltage V 4 at time t 4 .
- the floating gate can still have one of a plurality of discrete levels of injected charge if programming is terminated anytime between time t 4 and because the amount of additional charge during this time is so small.
- line LI of FIG.4 can be altered, as shown by line L2, by increasing the formation of substrate hot electrons as described above.
- the time required to program a memory cell in accordance with the present invention remains longer than conventional programming, the formation of substrate hot electrons substantially narrows the time difference.
- FIG. 7 shows a graphical representation that illustrates a series of experimental results.
- the charge on the floating gate converged to a threshold voltage of approximately three volts from an initial threshold voltage of 1.5 volts within 50 milliseconds or less.
- the charge on the floating gate converged to threshold voltages of approximately four, five, and six volts, respectively, within 50 milliseconds or less.
- an initial threshold voltage of 1.5 volts was utilized in the above experiment, any initial threshold voltage after erase may be utilized.
- a single floating gate memory cell can be programmed to have one of a plurality of threshold voltages by applying the corresponding voltage to the control gate during programming. As a result, a single floating gate memory cell can be utilized to store two or more bits of data.
- a 0-0 could be represented by a threshold voltage of 3 volts, while a 0- 1 could be represented by a threshold voltage of 4 volts.
- a 1-0 could be represented by a threshold voltage of 5 volts, while a 1-1 could be represented by a threshold voltage of 6 volts.
- memory cell 112 is not limited to representing two bits, but can represent any number of bits depending on the sensitivity of the current sense detectors utilized to discriminate one threshold voltage from another.
- a continuous analog level can be stored in a cell as a threshold voltage. For example, a 0-0-0 could be represented by a threshold voltage of 3 volts, while a 0-0- 1 could be represented by a threshold voltage of 3.5 volts.
- a 0-0-0-0 could be represented by a threshold voltage of 3 volts, while a 0-0-0-1 could be represented by a threshold voltage of 3.25 volts.
- cell 1 12 can be programmed to store three or more logic levels by applying one of a corresponding three or more programming voltages to the control gate (word line).
- the equilibrium and reverse-bias conditions for the cells to be programmed are established in array 100 by identifying the column of cells to be programmed, and applying a voltage VD to the metal contacted bit line BLC that contacts the memory cells 1 12 and access transistors 114 in that column. For example, referring again to FIG. 2. if any combination of cells in column A are to be programmed, voltage VD is applied to metal contacted bit line BLC 1. The application of voltage VD to metal contacted bit line BLC1 is equivalent to applying a voltage to the drain of an individual cell as described above.
- a voltage VS. which is less than voltage VD, is applied to the metal contacted bit line BLC that contacts the memory cells 1 12 and access transistors 1 14 in a column adjacent to the column containing the cells to be programmed.
- the remaining metal contacted bit lines BLC are allowed to float.
- voltage VD is preferably 4-7 volts greater than voltage VS.
- voltage VS is preferably ground.
- voltage VD is preferably 2-4 volts greater than voltage VS.
- the column of cells to be programmed is selected by applying a voltage VA to the access lines AC that contact the access transistors 114 that are in the adjacent column, i.e., column B.
- the remaining access lines AC are held at ground.
- the cells 1 12 in column A are selected by applying voltage VA to access lines AC 1 and AC4, while access lines AC2 and AC3 are held at ground. Since voltage VA is used to turn on the appropriate access transistors 114, any voltage which turns on the transistors can be used.
- Programming is accomplished by selecting a programming voltage VG from three or more programming voltages VGl-VGs for each cell to be programmed where the three or more programming voltages correspond to three or more threshold voltages, and by applying the programming voltages VGl- VGs to the word lines WL that correspond to the cells 1 12 to be programmed for a predetermined time. For example, if cells Al, A2, and At are to be programmed with voltages VG1, VG2, and VGs, respectively, voltages VG1, VG2, and VGs are simultaneously applied to word lines WL1 , WL2, and WLn, respectively.
- the preferred voltages for programming voltages VG l-VGs depend on the number of logic levels to be programmed and generally fall within 0-5 volts. Although negative voltages can also be used, these voltages are not as desirable because of the additional circuitry needed to generate negative voltages.
- cells A l-At, or any combination thereof in column A of segment SG I can be programmed at the same time to each have any one of the three or more logic levels by applying the corresponding programming voltages VG 1 -VGs to corresponding word lines WLl-WLn.
- each cell in an entire segment can be programmed to store multiple bits of data in less time than is required for each cell to be conventionally programmed to store one bit of data. For example, in a segment that is eight bits wide by 32 bytes long, it takes one programming cycle to conventionally program each cell in a segment for a total of 256 (8x32) programming cycles.
- each segment SG of array 100 can be formed in a separate well. Further, as shown in FIG. 2, the entire array is formed in a single well.
- each segment can be individually accessed via segment select transistors.
- each segment SG can be operated on independently.
- one column in segment SG 1 can be programmed at the same time that a separate column in segment SG2 is being programmed which both can occur at the same time that a row of data is being read from segment SG3.
- cell Cl can not be conventionally programmed at the same time that cell A l is being programmed due to the high programming currents that are required, i.e., 400mA.
- cells Al and Cl can be programmed at the same time, if both cells are being programmed to the same logic level, by also grounding bit line BLC3.
- one advantage of the present invention is that the memory cells 1 12 of array 100 can be programmed to store multiple levels by utilizing a programming voltage that is considerably less than the programming voltage typically used, i.e., less than five volts in the present invention compared to the approximately 12 volts that are typically used.
- the present invention eliminates the need to form charge pumps on memory chips to produce the programming voltage, i.e., the 12 volts.
- charge pumps can consume a significant area, i.e., up to 30% of the total die area of a memory chip.
- the present invention significantly reduces the area required for a memory cell, and therefore the cost of a memory.
- the elimination of high programming voltages also leads to an increase in the density of array 100 because less isolation is required between both memory cells and the peripheral circuitry. As a result, the present invention substantially reduces the size of array 100.
- array 100 can be configured to support both conventional as well as multilevel programming by utilizing a high programming voltage.
- the high programming voltage can be provided either externally or on-chip, i.e., via the charge pumps.
- a single memory chip can utilize a first portion of the array to store one bit per cell when the data must be stored quickly, and a second portion of the array to store multiple bits per cell when more time can be taken to store the data.
Abstract
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Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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EP96912630A EP0764329B1 (en) | 1995-04-06 | 1996-04-08 | A method for programming an amg eprom or flash memory when cells of the array are formed to store multiple bits of data |
DE69613186T DE69613186T2 (en) | 1995-04-06 | 1996-04-08 | PROGRAMMING PROCEDURE FOR AN AMG EPROM STORAGE OR A FLASH STORAGE IF EVERY STORAGE CELL IS SUCCESSFUL TO SAVE MULTIPLE DATA BITS |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US08/417,938 | 1995-04-06 | ||
US08/417,938 US5557567A (en) | 1995-04-06 | 1995-04-06 | Method for programming an AMG EPROM or flash memory when cells of the array are formed to store multiple bits of data |
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WO1996031883A1 true WO1996031883A1 (en) | 1996-10-10 |
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PCT/US1996/004843 WO1996031883A1 (en) | 1995-04-06 | 1996-04-08 | A method for programming an amg eprom or flash memory when cells of the array are formed to store multiple bits of data |
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US (1) | US5557567A (en) |
EP (1) | EP0764329B1 (en) |
KR (1) | KR100365167B1 (en) |
DE (1) | DE69613186T2 (en) |
WO (1) | WO1996031883A1 (en) |
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- 1996-04-08 KR KR1019960706933A patent/KR100365167B1/en not_active IP Right Cessation
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Also Published As
Publication number | Publication date |
---|---|
DE69613186D1 (en) | 2001-07-12 |
US5557567A (en) | 1996-09-17 |
DE69613186T2 (en) | 2002-01-31 |
KR970703598A (en) | 1997-07-03 |
KR100365167B1 (en) | 2003-03-06 |
EP0764329A1 (en) | 1997-03-26 |
EP0764329B1 (en) | 2001-06-06 |
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