WO1996037822A1 - Area and time efficient field extraction circuit - Google Patents
Area and time efficient field extraction circuit Download PDFInfo
- Publication number
- WO1996037822A1 WO1996037822A1 PCT/US1996/007583 US9607583W WO9637822A1 WO 1996037822 A1 WO1996037822 A1 WO 1996037822A1 US 9607583 W US9607583 W US 9607583W WO 9637822 A1 WO9637822 A1 WO 9637822A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- data
- bit
- output
- group
- extraction
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
Definitions
- the present invention relates to field extraction circuits and in particular, to a high-speed field extraction circuit which has a minimum wiring complexity.
- processor machine code instructions are typically have pre-defined instruction "fields" which may be predictably located within each instruction.
- the decoder extracts particular fields of an inst ⁇ iction to be decoded from an instruction stream.
- What is desired is a circuit for extracting instruction fields which has relatively low wiring complexity and area, and which operates at relatively high speed.
- the circuit provides at least one of the data words DW ⁇ to an extraction circuit output responsive to an extraction indicator signal.
- a group of data selector elements DSE each corresponding to a separate one of the bit positions BP ⁇ in the received data words.
- Each data selector element includes a data output DO and a plurality of data inputs DI ⁇ .
- Each data input DI ⁇ is connected to receive a bit from the bit position BP V to which the data selector element DSE V corresponds, of a data word DW to y y x which the data input Dl ⁇ corresponds.
- a select input is responsive to the extraction indicator signal such that the data selector element DSE provides, at the data output, the bit received at one of the data inputs Dl ⁇ that corresponds to the extraction indicator signal.
- the bits provided at the data outputs of the group of data selector elements are collectively provided to the extraction circuit output.
- a second group of data selector elements DSE2 is also provided. Each of the data selector elements corresponds to a separate one of the bit positions BP in the received data words DW ⁇ .
- each of the second group of data selector elements includes a data output D02 .
- Each of the second group of data selector elements further includes a plurality of data inputs DI2 ⁇ .
- Each data input DI2 ⁇ is connected to receive a bit from the bit position BP to which the data selector element DSE2 y corresponds, of a data word DW ( x _nR£Mn t0 nicn tne data in P ut DI X corresponds.
- each of the second group of data selectors includes a select input that is responsive to the extraction indicator signal.
- the data selector element DSE y provides, at the data output, the bit received at one of the data inputs DI ⁇ that corresponds to the extraction indicator signal.
- the bits provided at the data outputs of the second group of data selector elements are also collectively provided to the extraction circuit output.
- FIG. 1 schematically illustrates a field extraction circuit in accordance with the present invention.
- a first row 1 10 of four-to-one data selectors 1 12a through 1 12d are each configured to receive four bits of an instruction.
- four- to-one data selector 112a receives, at its four inputs, the least significant bit (i.e., bit 0) of each of four words —words 0 through 3— of an input data stream.
- the input data stream may be, for example, instructions to be decoded by a processor decoder.
- the least significant input, DO, of four-to-one data selector 1 12a receives bit 0 of word 0; the next significant input, Dl, receives bit 0 of word 1; the next significant input, D2, receives bit 0 of word 2; and the most significant input, D3, receives bit 0 of word 3.
- Four-to-one data selector 1 12b receives, at its four inputs, the next to least significant bit (i.e., bit
- each of four-to-one data selectors 122a through 122d of row 120 are rotated by one bit from the four bits received by each of the four-to-one data selectors 112a through 122d, of row 110.
- the least significant input of four-to-one data selector 122a, DO receives bit 0 of word 1, as compared to the least significant input of four-to-one data selector 112a receiving bit 0 of word 0.
- a third row 130 of four-to-o ⁇ e data selectors 132a through 132d are each configured to receive the same four bits received by the data selectors 112a through 112d, respectively, of the first row 1 10 and the data selectors 122a through 122d, respectively, of the second row 120.
- the four bits received by each of four-to-one data selectors 132a through 132d of the third row 130 are rotated by one bit from the four bits received by the four-to-one data selectors 122a through 122d, respectively, of the second row 120; and by two bits from the four bits received by the four-to-one data selectors 1 12a through 112d, respectively, of the first row 110.
- a fourth row 140 of four-to-one data selectors 142a through 142d are each configured to receive the same four bits received by the data selectors 112a through 1 12d, respectively, of the first row 110, but rotated by three bits; by the data selectors 122a through 122d, respectively, of the second row 120, but rotated by two bits; and by the data selectors 132a through 132d, respectively, of the third row 130, but rotated by one bit.
- a two-to-one decoder 160 receives a two bit address, ADR [0..1].
- ADR [0..1 ] the two-bit address
- DO and Dl the decoder 160 operates in a conventional manner to assert one, and only one, of the four decoder outputs, Q0 through Q3.
- the decoder outputs, Q0 through Q3, are connected to a four bit bus 162.
- the four bit bus 162 is connected to the select input, S, of every one of the four-to- one data selectors I 12a-1 12d, 122a-122d, 132a-132d, and 142a-142d.
- each of the four-to-one data selectors 112a- 1 12d, 122a-122d, 132a-132d, and 142a- 142d behave conventionally, and in an identical manner. That is, if decoder output Q0 is asserted, each four-to-one data selector outputs, to its Q data output, the value provided at its DO data input. If decoder output Ql is asserted, each four-to-one data selector outputs, to its Q data output, the value provided at its Dl data input. If decoder output Q2 is asserted, each four-to-one data selector outputs, to its Q data output, the value provided at its D2 data input. Finally, if decoder output Q3 is asserted, each four-to- one data selector outputs, to its Q data output, the value provided at its D3 data input.
- decoder output Q0 is asserted
- four-to-one selector 1 12a selects bit 0 of input data stream word 0 to be provided to its output, Q. Otherwise, if decoder output Ql is asserted, then four-to-one selector 112a selects bit 0 of word 1 to be provided to its output, Q. If decoder output Q2 is asserted, then four-to-one selector 112a selects bit 0 of word 2 to be provided to its output, Q. Finally, if decoder output Q3 is asserted, then four-to-one selector 112a selects bit 0 of word 3 to be provided to its output, Q.
- the Q data outputs of the four-to-one data selectors of a particular one of the four rows 110, 120, 130, and 140 collectively provide one of four extracted output values EXTR[0], EXTRfl], EXTR[2], and EXTR[3], respectively.
- the value of the address, ADR [0..1] determines which word of the input data stream will be provided to the extracted outputs, EXTR [0] through EXTR [3]. That is, first, if ADR[0..1] is 0, then word 0 is provided to EXTR [0], word 1 is provided to EXTR [1], word 2 is provided to EXTR [2], and word 3 is provided to EXTR [3]. Second, if ADR [0..1] is 1, then word 1 is provided to EXTR [0], word 2 is provided to EXTR [1], word 3 is provided to EXTR [2], and word 0 is provided to EXTR [3].
- ADR[0..1] 2 is provided to EXTR [0]
- word 3 is provided to EXTR [1]
- word 0 is provided to EXTR [2]
- word 1 is provided to EXTR [3].
- ADR [0..1] 3 is provided to EXTR [0]
- word 0 is provided to EXTR [1]
- word 1 is provided to EXTR [2]
- word 2 is provided to EXTR [3].
- the size of the input data stream words may vary from four, as may the number of input data stream words.
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP96917826A EP0776501A1 (en) | 1995-05-26 | 1996-05-23 | Area and time efficient field extraction circuit |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/451,434 | 1995-05-26 | ||
US08/451,434 US5815736A (en) | 1995-05-26 | 1995-05-26 | Area and time efficient extraction circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1996037822A1 true WO1996037822A1 (en) | 1996-11-28 |
Family
ID=23792196
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1996/007583 WO1996037822A1 (en) | 1995-05-26 | 1996-05-23 | Area and time efficient field extraction circuit |
Country Status (4)
Country | Link |
---|---|
US (1) | US5815736A (en) |
EP (1) | EP0776501A1 (en) |
KR (1) | KR970705067A (en) |
WO (1) | WO1996037822A1 (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56162145A (en) * | 1980-05-17 | 1981-12-12 | Nec Corp | Data arranging circuit |
EP0368826A2 (en) * | 1988-11-09 | 1990-05-16 | International Business Machines Corporation | Data processing circuit |
EP0522186A1 (en) * | 1991-07-06 | 1993-01-13 | International Business Machines Corporation | Multiplexer |
WO1994027211A1 (en) * | 1993-05-07 | 1994-11-24 | Apple Computer, Inc. | Method and system for reordering bytes in a data stream |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3812467A (en) * | 1972-09-25 | 1974-05-21 | Goodyear Aerospace Corp | Permutation network |
US4162534A (en) * | 1977-07-29 | 1979-07-24 | Burroughs Corporation | Parallel alignment network for d-ordered vector elements |
KR880001399B1 (en) * | 1983-03-03 | 1988-07-30 | 후지쓰 가부시끼가이샤 | Data processor |
US4999808A (en) * | 1986-09-26 | 1991-03-12 | At&T Bell Laboratories | Dual byte order data processor |
US5204953A (en) * | 1989-08-04 | 1993-04-20 | Intel Corporation | One clock address pipelining in segmentation unit |
US5259006A (en) * | 1990-04-18 | 1993-11-02 | Quickturn Systems, Incorporated | Method for substantially eliminating hold time violations in implementing high speed logic circuits or the like |
US5189319A (en) * | 1991-10-10 | 1993-02-23 | Intel Corporation | Power reducing buffer/latch circuit |
US5254888A (en) * | 1992-03-27 | 1993-10-19 | Picopower Technology Inc. | Switchable clock circuit for microprocessors to thereby save power |
US5438668A (en) * | 1992-03-31 | 1995-08-01 | Seiko Epson Corporation | System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer |
US5404473A (en) * | 1994-03-01 | 1995-04-04 | Intel Corporation | Apparatus and method for handling string operations in a pipelined processor |
-
1995
- 1995-05-26 US US08/451,434 patent/US5815736A/en not_active Expired - Lifetime
-
1996
- 1996-05-23 KR KR1019970700501A patent/KR970705067A/en not_active Application Discontinuation
- 1996-05-23 EP EP96917826A patent/EP0776501A1/en not_active Withdrawn
- 1996-05-23 WO PCT/US1996/007583 patent/WO1996037822A1/en not_active Application Discontinuation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56162145A (en) * | 1980-05-17 | 1981-12-12 | Nec Corp | Data arranging circuit |
EP0368826A2 (en) * | 1988-11-09 | 1990-05-16 | International Business Machines Corporation | Data processing circuit |
EP0522186A1 (en) * | 1991-07-06 | 1993-01-13 | International Business Machines Corporation | Multiplexer |
WO1994027211A1 (en) * | 1993-05-07 | 1994-11-24 | Apple Computer, Inc. | Method and system for reordering bytes in a data stream |
Non-Patent Citations (1)
Title |
---|
PATENT ABSTRACTS OF JAPAN vol. 6, no. 46 (P - 107) 24 March 1982 (1982-03-24) * |
Also Published As
Publication number | Publication date |
---|---|
KR970705067A (en) | 1997-09-06 |
EP0776501A1 (en) | 1997-06-04 |
US5815736A (en) | 1998-09-29 |
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