WO1996037960A3 - Configurable power management scheme - Google Patents

Configurable power management scheme Download PDF

Info

Publication number
WO1996037960A3
WO1996037960A3 PCT/US1996/007571 US9607571W WO9637960A3 WO 1996037960 A3 WO1996037960 A3 WO 1996037960A3 US 9607571 W US9607571 W US 9607571W WO 9637960 A3 WO9637960 A3 WO 9637960A3
Authority
WO
WIPO (PCT)
Prior art keywords
power management
management system
circuit
clock
oscillations
Prior art date
Application number
PCT/US1996/007571
Other languages
French (fr)
Other versions
WO1996037960A2 (en
Inventor
Michael J Shay
Original Assignee
Nat Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nat Semiconductor Corp filed Critical Nat Semiconductor Corp
Priority to EP96916586A priority Critical patent/EP0772911B1/en
Priority to DE69629780T priority patent/DE69629780T2/en
Publication of WO1996037960A2 publication Critical patent/WO1996037960A2/en
Publication of WO1996037960A3 publication Critical patent/WO1996037960A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L3/00—Starting of generators
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A power management system is disclosed. The system includes an oscillator interface for use in a power management system, a power recycle circuit for use in a power management system, a pad clock and self test for use in a power management system, a clock enable circuit for use in a power management system, a power level detect circuit for use in a power management system, an internal source clock generation circuit for use in a power management system, and a power-save mode change detection circuit for use in a power management system. The oscillator interface includes an interface circuit for interfacing with an external oscillator used as a source of oscillations. A clock stabilization filter masks out spurious crystal frequencies in the oscillations during start-up of the power management system following an enabling of a feedback loop. The clock stabilization filter has circuitry which provides that the oscillations will start with a rising transition after filtering. A bypassing circuit enables the clock stabilization filter when the external oscillator is a crystal oscillator and for bypassing the clock stabilization filter when the external oscillator is a can oscillator. A masking circuit masks the oscillations from the rest of the power management system. The masking circuit has circuitry which disables the clock masking after a falling edge of the oscillations and starts back up with a rising transition of the oscillations.
PCT/US1996/007571 1995-05-26 1996-05-23 Configurable power management scheme WO1996037960A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP96916586A EP0772911B1 (en) 1995-05-26 1996-05-23 Oscillator interface for use in a power management system
DE69629780T DE69629780T2 (en) 1995-05-26 1996-05-23 OSCILLATOR FOR USE IN A POWER CONTROL SYSTEM

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/451,206 US5805923A (en) 1995-05-26 1995-05-26 Configurable power management system having a clock stabilization filter that can be enabled or bypassed depending upon whether a crystal or can oscillator is used
US08/451,206 1995-05-26

Publications (2)

Publication Number Publication Date
WO1996037960A2 WO1996037960A2 (en) 1996-11-28
WO1996037960A3 true WO1996037960A3 (en) 1997-02-06

Family

ID=23791238

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1996/007571 WO1996037960A2 (en) 1995-05-26 1996-05-23 Configurable power management scheme

Country Status (5)

Country Link
US (7) US5805923A (en)
EP (1) EP0772911B1 (en)
KR (5) KR100399662B1 (en)
DE (1) DE69629780T2 (en)
WO (1) WO1996037960A2 (en)

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Also Published As

Publication number Publication date
KR100430769B1 (en) 2004-05-10
US6367021B1 (en) 2002-04-02
DE69629780T2 (en) 2004-07-15
KR100430768B1 (en) 2004-05-10
US6397338B2 (en) 2002-05-28
US20010007113A1 (en) 2001-07-05
WO1996037960A2 (en) 1996-11-28
KR20030097635A (en) 2003-12-31
US5805923A (en) 1998-09-08
KR20030097634A (en) 2003-12-31
DE69629780D1 (en) 2003-10-09
EP0772911B1 (en) 2003-09-03
KR970705238A (en) 1997-09-06
EP0772911A1 (en) 1997-05-14
US5926641A (en) 1999-07-20
KR100399662B1 (en) 2004-03-24
US6016071A (en) 2000-01-18
US6021501A (en) 2000-02-01
KR20030097636A (en) 2003-12-31
KR20030097637A (en) 2003-12-31
US5983014A (en) 1999-11-09

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