WO1997001172A1 - Method for page writing to flash memory using channel hot-carrier injection - Google Patents
Method for page writing to flash memory using channel hot-carrier injection Download PDFInfo
- Publication number
- WO1997001172A1 WO1997001172A1 PCT/US1996/010562 US9610562W WO9701172A1 WO 1997001172 A1 WO1997001172 A1 WO 1997001172A1 US 9610562 W US9610562 W US 9610562W WO 9701172 A1 WO9701172 A1 WO 9701172A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- drain
- programming
- flash eeprom
- set forth
- low
- Prior art date
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
Definitions
- This invention relates to hot carrier injection programmable flash EEPROM's, and more particularly to a floating gate memory cell operated in a low-energy programming mode permitting charge pump programming of at least 1024 memory cells.
- Flash EEPROM's are solid state memories and they store information in arrays of memory cells formed on substrates in rows and columns.
- the cells are programmed by injection of hot carriers into a floating gate structure within each cell.
- the internal operating voltages needed to program the cells are derived from a basic chip supply voltage, such as
- the Kazerounian et al. reference teaches a split gate architecture requiring a separate doping area within the channel near the source region.
- the operation ofthe cells requires the application of specialized biasing schemes such as ramping the gate, high drain voltages, or pulsing the gate.
- Kazerounian et al limits the practical usefulness ofthe cell despite the benefits ofthe low programming current.
- the low-energy write mode flash EEPROM in accordance with this invention comprises: an array of floating gate flash EEPROM memory cells fo ⁇ ned on a substrate in rows and columns, each cell having a source, a drain, a-channel between the source and the drain, a floating gate extending between the source and the drain above the channel, and a control gate extending between the source and the drain above the floating gate, the control gates of respective rows being connected to respective word select lines, the memory cell source for at least one row of memory cells being coupled to a common source line, and the memory cell drain ofthe respective columns being connected to respective bit select lines; the memory cells having a high core doping to optimize cell programming by hot carrier injection into the floating gate of selected memory cells; a circuit for limiting a programming drain current to less than lO ⁇ A per memory cell, the limited cell drain current resulting in a high programming efficiency; and a selected row of memory cells being programmable within a shortened row programming interval having
- the selected row of memory cells includes 1024 cells and defines a page of memory cells.
- the preferred embodiment also includes a cache buffer and address and control logic for receiving a page of data from a computer bus, temporarily storing the data in the cache buffer, and simultaneously writing the temporarily stored data from the cache buffer as one page of 1024 cells into the selected row of memory cells.
- the preferred embodiment uses charge pumps to derive intemal programming voltages from a +V CC device input line.
- Another preferred embodiment includes selective doping enhancements in the channel and the drain regions of each memory cell. The doping allows operation at a programming drain voltage below the +V CC level.
- Fig. 1 is partial schematic diagram illustrating a low-energy write mode flash EEPROM in accordance with one aspect ofthe present invention.
- Fig. 2 is a graph illustrating a relationship between programming efficiency and drain-to- source voltage for a class of low-energy write mode memory cells.
- Fig. 3 is a partial schematic diagram illustrating a circuit for precharging a source line parasitic capacitance according to another aspect ofthe invention.
- Fig. 4 is a partial schematic diagram illustrating a charge pump for providing a programming drain voltage to a memory cell according to one aspect ofthe invention.
- Figs. 5 and 5a show a graph displaying a relationship between a memory cell threshold voltage and the duration of a programming interval at selected cell currents.
- Fig. 6 is a graph illustrating the effect of core doping upon programming drain voltage and programming interval for low-energy write mode flash EEPROMs according to one aspect ofthe present invention.
- Fig. 7 is a graph showing the effect of drain region doping upon programming drain voltage and cell programming interval.
- Fig. 8 is a pictorial diagram illustrating a stacked gate flash EEPROM memory cell according to one aspect ofthe invention.
- Fig. 9 is a partial schematic diagram of a low-energy write flash EEPROM memory system according to the present invention. Description of the Preferred Embodiment
- Fig. 1 a partial schematic diagram illustrating one aspect of a low-energy write mode flash EEPROM, designated generally by the numeral 10.
- the EEPROM 10 includes an array 12 of stacked gate flash EEPROM memory cells 14 formed in rows 16 and columns 18.
- Each memory cell 14 includes a source 20, a drain 22. a channel region 24 between the source 20 and the drain 22. a floating gate 26 extending between the source 20 and the drain 22 above the channel region 24 and a control gate 28 extending above the floating gate 26.
- the control gate 28 of each memory cell in the respective rows 16 are connected to respective row select lines 30.
- the source 20 ofthe memory cells 14 of at least one row 16 are connected to a common source 32.
- the drain 22 of each cell 14 within a respective column 18 is connected to a respective bit select line 34.
- the common source 32 is connected to a circuit 36 which limits the cell current in each memory cell 14 to less than lO ⁇ A during programming.
- the memory cells 14 are programmed by hot carrier injection of electrons from the drain- channel junction into the floating gate 26 (US patent no. 5,077,691 to Haddad et al. which is incorporated here by referenced).
- the doping in the channel and the drain is increased to reduce the programming drain voltage and to improve the charging time, also referred to as the programming interval.
- the operation at drain voltages near a typical chip supply voltage level (i.e.. ⁇ 5VDC) and limited programming cell current permit the use of on-chip charge pumps to provide programming current.
- the low-energy write mode also permits an entire page of at least 1024 cells to be programmed within one programming interval.
- the cell programming current limiting circuit 36 can be implemented in a number of ways which will be obvious to a person having an ordinary level of skill in this art. For example, a series resistor having a very high resistance can be used. Alternatively, a constant current supply can be used to limit the cell programming current.
- FIG. 2 graphically illustrates a relationship between programming efficiency and drain-to-source voltage at two levels of cell current.
- the graph is depicted generally by the numeral 40 and has a vertical axis 42 representing programming efficiency, defined as a ratio of programming drain current, I D (essentially the cell current), to the current flowing into the floating gate 26 during programming, I G (the injection current).
- I D essentially the cell current
- I G the injection current
- the drain-to- source voltage is depicted along the horizontal axis 44. Two curves are shown.
- the lower curve 46 corresponds to a cell current of approximately lOO ⁇ A.
- the invention limits cell prograrriming current to less than lO ⁇ A, and experiment has shown that programming efficiencies in a range from 10 " * to 10 are available using the features ofthe present invention.
- the altemative method of charging the parasitic capacitance 58 ofthe common source 56 does not use the precharge circuit 60. Instead, the selected row of memory cells 53 is programmed in groups of cells by sequentially activating respective groups of bit select Iines 34 (Fig. 1). In this way, the capacitance 58 is gradually charged during the programming ofthe first groups of cells and the remaining cells can then be programmed simultaneously. For example, assume there are 1024 cells 54, 55 in the selected row 53, and assume several groups of 8 cells each are programmed as the capacitance 58 is gradually charged. Then the remaining cells, e.g., 1000 cells, are programmed as a single group.
- FIG. 4 is a partial schematic diagram which illustrates a low-energy write mode flash EEPROM according to another aspect ofthe present invention and depicted generally by the numeral 70.
- the EEPROM 70 includes an array 72 of stacked gate memory cells 74 formed in rows
- the array 72 includes respective row select lines 80, a common source 82, respective bit select lines 84 and an on-chip charge pump 86 connected for supplying programming cu ⁇ ent to selected cells 74.
- the charge pump 86 derives operating power from the chip +V CC supply.
- the charge pump 86 is connected to supply cell programming cu ⁇ ent through the bit select lines 84 of cells 74 which are to be programmed.
- the charge pump 86 is designed to maintain a relatively constant voltage at line 84 and will provide programming cu ⁇ ent for up to an entire page of cells. Excessive cell programming current defeats the usefulness of a charge pump to supply a well regulated drain programming voltage, hence the importance of maintaining a low cell programming cu ⁇ ent.
- a floating gate memory cell 14 (Fig. 1) is programmed by charging the floating gate 26 to cause an increase in a threshold voltage ofthe cell, in other words, the voltage applied to the control 28 to cause the cell to conduct cu ⁇ ent between the drain 22 and the source 20.
- the threshold voltage In an unprogrammed cell, the threshold voltage is low, while in a programmed cell, the threshold voltage is high. The change in the threshold voltage is later detectable during a cell read operation.
- the time required to produce the desired increase in the cell voltage threshold must be kept to a minimum. Also, keeping the duration ofthe programming interval (the charging time to accomplish the desired increase in the threshold voltage) short means that the data transfer rate during writing can be higher, making a more useful product.
- FIG. 5 illustrates a graph generally indicated by the numeral 90, showing a relationship between cell threshold voltage and charging time, as shown.
- the graph 90 has a vertical axis 92 defining a threshold voltage V a , and a horizontal axis 94 defining the charging time in seconds on a logarithmic scale.
- Three curves 96, 98 and 100 illustrate an experimentally determined relationship between cell threshold voltage and programming time at cell programming cu ⁇ ents of 16 ⁇ A, 4 ⁇ A and l ⁇ A, respectively.
- the creation of hot carriers for programming is not entirely independent of cell cu ⁇ ent despite the high programming efficiency. In general, the higher the cell cu ⁇ ent, the faster the cell is programmed.
- all 42 cells are programmed in an interval in a range from 20 ⁇ S to 100 ⁇ S (less than lOO ⁇ S at cell cu ⁇ ents of less than 4- 16 ⁇ A.
- Fig. 5a there is shown an example of page write programming.
- the entire page of 1024 cells is programmed in about lOO ⁇ S with a channel current of less than or equal to 3 ⁇ A.
- Fig. 6 shows a graph illustrating the effect of channel doping on programming drain voltage
- Fig. 7 is a graph which shows the effect of drain doping on the duration ofthe programming interval.
- Fig. 6 illustrates a graph generally indicated by the numeral 110.
- the graph 110 has a vertical axis 112 defining a memory cell source pull-up voltage and a horizontal axis 114 indicating the programming time in seconds.
- the graph 1 10 has three curves 116, 1 18 and 120 which illustrate that the necessary increase in memory cell threshold voltage, indicated by a co ⁇ esponding decrease in the cell source pull-up voltage, is improved by increasing the channel doping. Also there is a decrease in the drain voltage as the channel doping is increased.
- the curve 116 co ⁇ esponds to a channel doping having a dosage equal to 2.2 x 10 Ij # cm "2 .
- the drain voltage is 6.8V.
- the curve 118 co ⁇ esponds to a channel doping having a dosage equal to 4.6 x 10 # cm ' .
- the drain voltage is 5.3 V.
- the curve 120 co ⁇ esponds to a channel doping having a dosage equal to 5.4 x 10 # cm " .
- the drain voltage is 5.16V.
- Fig. 7 illustrates a graph generally indicated by the numeral 130.
- the graph 130 has a vertical axis 132 defining the cell programming drain voltage, and a horizontal axis 134 defining the same cell programming time as that used in Fig. 6.
- Three curves 136, 138 and 140 co ⁇ espond to the decrease on the drain voltage during a cell programming interval of approximately lOO ⁇ S at drain region enhanced dosages of 8 x 10 15 # cm " , 6 x IO 15 # cm *2 and 4 x 10 # cm " , respectively.
- the decrease in the drain voltage co ⁇ esponds to the increase in the cell threshold voltage necessary for programming.
- Fig. 7 illustrates that increasing the doping of the drain region translates directly into increases in cell programming time.
- the EEPROM 200 includes a substrate 202 upon which is formed in the usual rows and columns an array of memory cells. Each cell includes an N+ source region 204, an N+ drain region 206, the source and drain regions being separated by a channel region 208 of an opposite doping.
- a floating gate structure 210 extends above the channel region 208 between the source region 204 and the drain region 206.
- a control 212 extends above the floating gate 210 from the source region 204 to the drain region 206.
- the drain 206 of each cell within respective columns is connected to a respective bit select line 214.
- the control 212 of each cell within respective rows is connected to a respective page select line 216.
- the source region 204 of each cell forms a common source or a line 218.
- a circuit 220 is connected to the common source for biasin ⁇ the source re ⁇ ion of each cell to define a low-energy operating mode having a high programming efficiency and a shortened programming cycle.
- Fig. 9 is a partial schematic diagram of an EEPROM memory system according to another aspect ofthe present invention.
- the memory system is depicted generally by the numeral 250 and includes an array 252 of memory cells arranged in rows and columns and including at least 1024 cells per row.
- the respective columns of cells are selected by bit select lines of which lines 254, 256 are examples.
- the respective rows of cells are selected by page select lines of which line 258 is an example.
- a common source line 260 is connected to the cell source ofthe cells of at least one page.
- the memory system 250 includes a cache buffer 262 which receives data on data input lines 264 and address and control signals from buffer address and control logic circuits 266.
- An array address decoder 268 receives memory system addresses on address input lines 270 and decodes these to control the page select lines 258.
- An on-chip charge pump is connected to a memory system +V CC input line and provides programming cu ⁇ ent for all bit select lines 254, 256.
- data is received on lines 264 in groups smaller than one page. Typically the data will be received in 8, 16, 32 or 64-bit words. These received words are stored in the cache buffer 262 under the control of address and control circuits 266.
- the cache buffer 262 stores up to one page of data, the page being at least 1024 bits (128 bytes) in length.
- the contents ofthe cache buffer 262 is read one page at a time and controls the individual bit select lines 254, 256.
- a page address received on input lines 270 is decoded to select a page of cells ofthe anay 252, and the page of data controlling the bit select lines 254, 256 is written into the selected page of the anay 252.
- a page of 128 bytes of data is written in under lOO ⁇ S, a transfer rate of 1.28MB per second, and the EEPROM memory system 250 derives programming cu ⁇ ent from an on-chip charge pump 272.
- the entire memory system 250 is operated from a single +V CC input.
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Abstract
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Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP50391297A JP3903142B2 (en) | 1995-06-21 | 1996-06-18 | Method for page writing to flash memory using channel hot carrier injection |
EP96922505A EP0835509B1 (en) | 1995-06-21 | 1996-06-18 | Method for page writing to flash memory using channel hot-carrier injection |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/493,138 | 1995-06-21 | ||
US08/493,138 US5590076A (en) | 1995-06-21 | 1995-06-21 | Channel hot-carrier page write |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1997001172A1 true WO1997001172A1 (en) | 1997-01-09 |
Family
ID=23959067
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1996/010562 WO1997001172A1 (en) | 1995-06-21 | 1996-06-18 | Method for page writing to flash memory using channel hot-carrier injection |
Country Status (5)
Country | Link |
---|---|
US (1) | US5590076A (en) |
EP (1) | EP0835509B1 (en) |
JP (1) | JP3903142B2 (en) |
KR (1) | KR100391117B1 (en) |
WO (1) | WO1997001172A1 (en) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
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US5687114A (en) | 1995-10-06 | 1997-11-11 | Agate Semiconductor, Inc. | Integrated circuit for storage and retrieval of multiple digital bits per nonvolatile memory cell |
US5712815A (en) * | 1996-04-22 | 1998-01-27 | Advanced Micro Devices, Inc. | Multiple bits per-cell flash EEPROM capable of concurrently programming and verifying memory cells and reference cells |
US5870335A (en) * | 1997-03-06 | 1999-02-09 | Agate Semiconductor, Inc. | Precision programming of nonvolatile memory cells |
US6487116B2 (en) | 1997-03-06 | 2002-11-26 | Silicon Storage Technology, Inc. | Precision programming of nonvolatile memory cells |
US5856946A (en) * | 1997-04-09 | 1999-01-05 | Advanced Micro Devices, Inc. | Memory cell programming with controlled current injection |
US6046934A (en) * | 1999-01-12 | 2000-04-04 | Macronix International Co., Ltd. | Method and device for multi-level programming of a memory cell |
US6178118B1 (en) | 1997-08-26 | 2001-01-23 | Macronix International Co., Ltd. | Electrically programmable semiconductor device with multi-level wordline voltages for programming multi-level threshold voltages |
US6282145B1 (en) | 1999-01-14 | 2001-08-28 | Silicon Storage Technology, Inc. | Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system |
US6175519B1 (en) | 1999-07-22 | 2001-01-16 | Macronix International Co., Ltd. | Virtual ground EPROM structure |
US6181604B1 (en) | 1999-07-22 | 2001-01-30 | Macronix International Co., Ltd. | Method for fast programming of EPROMS and multi-level flash EPROMS |
US6396742B1 (en) | 2000-07-28 | 2002-05-28 | Silicon Storage Technology, Inc. | Testing of multilevel semiconductor memory |
US6750157B1 (en) | 2000-10-12 | 2004-06-15 | Advanced Micro Devices, Inc. | Nonvolatile memory cell with a nitridated oxide layer |
WO2002056316A1 (en) * | 2001-01-12 | 2002-07-18 | Hitachi, Ltd. | Nonvolatile semiconductor storage device |
US7154141B2 (en) | 2001-02-02 | 2006-12-26 | Hyundai Electronics America | Source side programming |
US6574158B1 (en) | 2001-09-27 | 2003-06-03 | Cypress Semiconductor Corp. | Method and system for measuring threshold of EPROM cells |
US6794923B2 (en) * | 2002-03-20 | 2004-09-21 | Texas Instruments Incorporated | Low ripple charge pump for charging parasitic capacitances |
US6950348B2 (en) * | 2003-06-20 | 2005-09-27 | Sandisk Corporation | Source controlled operation of non-volatile memories |
WO2006001058A1 (en) * | 2004-06-25 | 2006-01-05 | Spansion Llc | Semiconductor device and source voltage control method |
WO2008047416A1 (en) * | 2006-10-18 | 2008-04-24 | Spansion Llc | Voltage detecting circuit |
US8180981B2 (en) | 2009-05-15 | 2012-05-15 | Oracle America, Inc. | Cache coherent support for flash in a memory hierarchy |
KR102167600B1 (en) * | 2014-04-29 | 2020-10-19 | 에스케이하이닉스 주식회사 | EPROM cell array, method of operating the same, and memory device having the same |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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FR2688333A1 (en) * | 1992-03-06 | 1993-09-10 | Sgc Thomson Microelectronics S | Device and process for erasing an EPROM flash memory in sectors |
US5367484A (en) * | 1993-04-01 | 1994-11-22 | Microchip Technology Incorporated | Programmable high endurance block for EEPROM device |
WO1995007535A1 (en) * | 1993-09-10 | 1995-03-16 | Intel Corporation | Flash eeprom using charge pumping |
EP0698888A1 (en) * | 1994-08-26 | 1996-02-28 | STMicroelectronics Limited | Controlling capacitive load |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
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US5042009A (en) * | 1988-12-09 | 1991-08-20 | Waferscale Integration, Inc. | Method for programming a floating gate memory device |
US5077691A (en) * | 1989-10-23 | 1991-12-31 | Advanced Micro Devices, Inc. | Flash EEPROM array with negative gate voltage erase operation |
US5511020A (en) * | 1993-11-23 | 1996-04-23 | Monolithic System Technology, Inc. | Pseudo-nonvolatile memory incorporating data refresh operation |
-
1995
- 1995-06-21 US US08/493,138 patent/US5590076A/en not_active Expired - Lifetime
-
1996
- 1996-06-18 KR KR1019970709500A patent/KR100391117B1/en not_active IP Right Cessation
- 1996-06-18 JP JP50391297A patent/JP3903142B2/en not_active Expired - Fee Related
- 1996-06-18 EP EP96922505A patent/EP0835509B1/en not_active Expired - Lifetime
- 1996-06-18 WO PCT/US1996/010562 patent/WO1997001172A1/en active IP Right Grant
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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FR2688333A1 (en) * | 1992-03-06 | 1993-09-10 | Sgc Thomson Microelectronics S | Device and process for erasing an EPROM flash memory in sectors |
US5367484A (en) * | 1993-04-01 | 1994-11-22 | Microchip Technology Incorporated | Programmable high endurance block for EEPROM device |
WO1995007535A1 (en) * | 1993-09-10 | 1995-03-16 | Intel Corporation | Flash eeprom using charge pumping |
EP0698888A1 (en) * | 1994-08-26 | 1996-02-28 | STMicroelectronics Limited | Controlling capacitive load |
Also Published As
Publication number | Publication date |
---|---|
JPH11508388A (en) | 1999-07-21 |
EP0835509A1 (en) | 1998-04-15 |
KR100391117B1 (en) | 2003-08-19 |
US5590076A (en) | 1996-12-31 |
JP3903142B2 (en) | 2007-04-11 |
KR19990023030A (en) | 1999-03-25 |
EP0835509B1 (en) | 1999-08-11 |
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