WO1997003465A1 - Semiconductor pellet, method of its packaging, and bump electrode - Google Patents

Semiconductor pellet, method of its packaging, and bump electrode Download PDF

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Publication number
WO1997003465A1
WO1997003465A1 PCT/JP1996/000432 JP9600432W WO9703465A1 WO 1997003465 A1 WO1997003465 A1 WO 1997003465A1 JP 9600432 W JP9600432 W JP 9600432W WO 9703465 A1 WO9703465 A1 WO 9703465A1
Authority
WO
WIPO (PCT)
Prior art keywords
film
bump electrode
semiconductor pellet
mounting
external terminal
Prior art date
Application number
PCT/JP1996/000432
Other languages
French (fr)
Japanese (ja)
Inventor
Takayuki Uda
Hiroshi Kikuchi
Toshihiko Sato
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to JP50565997A priority Critical patent/JP3582014B2/en
Priority to TW085103809A priority patent/TW380361B/en
Publication of WO1997003465A1 publication Critical patent/WO1997003465A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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Definitions

  • the present invention relates to a mounting technique for mounting a semiconductor pellet on a mounting surface of a mounting substrate with a bump electrode interposed.
  • a semiconductor pellet is mounted on a mounting surface of a mounting board made of a resin substrate having a low heat resistance with a bump electrode interposed between the mounting board and the CCB (_Controlled C_olla P). se B_onding)
  • An implementation technology is disclosed in IEEE [Controlled Collapse Chip Connection (C4) 'Ann Enabling Technology, 1993, PP. 378-394].
  • C4 Controlled Collapse Chip Connection
  • a semiconductor pellet is mounted using bump electrodes made of a high-melting point composition and solders made of a low-melting point composition. The mounting method using the CCB mounting technology is described below.
  • the mounting substrate is formed of, for example, a resin substrate in which glass fiber is impregnated with an epoxy resin.
  • the heat resistant temperature of the mounting board is about 260 [° C] ⁇ 60 seconds to about 120 seconds.
  • the semiconductor pellet has a bump electrode on an external terminal on its main surface.
  • the bump electrode is made of, for example, an alloy material having a composition of 99 to 95 [wt%] Pb—1 to 5 [wt%] Sn. In this case, the melting point of the bump electrode is about 318 to 325 [° C].
  • the external terminals on the surface are made of a base metal film (BLM: B_all L_initing_etalizaton) to ensure high wettability with the bump electrodes.
  • This external terminal is connected to the lower internal terminal through an opening formed in the final protective film of the semiconductor pellet.
  • the underlying metal film is not limited to this structure, but may be used for the metal film (for example, Cr film) that has adhesiveness to the final protective film of the semiconductor pellet and the bump electrode from the surface side of the lower internal terminal. It has a laminated structure in which a wettable metal film (for example, a Cu film) and a non-oxidizable metal film (for example, an Au film) are sequentially laminated.
  • a paste solder is formed (printed) on the surface of the external terminal on the mounting surface of the mounting substrate by a screen printing method.
  • the welcome solder is formed of, for example, a eutectic composition of 37 [wt%] Pb-6 3 [wt%] Sn. In this case, the melting point of the solder is about 18 3 (Pb—Sn eutectic temperature) C].
  • the screen printing method is a method in which paste paste solder placed on a screen mask is transferred by a squeegee from the opening of the risk-lean mask onto the external terminals on the mounting surface of the mounting board.
  • the semiconductor bellet is arranged on the mounting surface of the mounting board, and a bump electrode is arranged between an external terminal of the mounting board and an external terminal of the semiconductor pellet.
  • a paste-like solder is interposed between the external terminal of the mounting board and one end of the bump electrode.
  • the semiconductor pellet can be mounted on the mounting surface of the mounting substrate made of a resin substrate having a low heat-resistant temperature with the bump electrode interposed therebetween.
  • the bump electrode has a high melting point composition with a small Sn content [wt%].
  • the reason for the formation of the Pb-Sn alloy material is to prevent the bump electrodes from being damaged due to the difference in thermal expansion coefficient between the mounting substrate and the semiconductor pellet.
  • the bump electrode becomes harder as the Sn content [% by weight] increases. Disclosure of the invention
  • the CCB mounting technology for mounting a semiconductor pellet using the bump electrode made of the high melting point composition and the receiving solder made of the low melting point composition is based on a paste-shaped solder solder that is screen-printed on the surface of the external terminal of the mounting board. After formation, the semiconductor pellet is placed on the mounting surface of the mounting board, and then heat treated to mount the semiconductor pellet. For this reason, the number of steps for mounting is increased by an amount corresponding to the step of forming the paste-like solder.
  • ⁇ Screen printing method uses a paste-like solder placed on a screen mask. This is a method in which a squeegee is used to transfer the image from the opening of the rescreen mask onto the surface of the external terminals on the mounting surface of the mounting board.
  • the arrangement pitch of the opening of the screen mask is limited to about 300 0 ⁇ ]. is there.
  • the arrangement pitch of the external terminals on the mounting substrate can be reduced to about 100 [ ⁇ m] by forming the external terminals on the thin film wiring layer.
  • the arrangement pitch of the external terminals of the semiconductor pellet can be reduced to about 100 [ ⁇ m] by forming the external terminals by photolithography.
  • the arrangement pitch of the bump electrodes can be reduced to about 100 [ ⁇ ] by forming the bump electrodes by a lift-off method using photolithography technology.
  • the arrangement pitch of the openings of the screen mask is limited to about 300 [/ im]
  • the arrangement pitch of the external terminals of the mounting board, the external terminals of the semiconductor pellet, and the bump electrodes is met by the solder pitch. It is restricted by the arrangement pitch.
  • the bump Since the arrangement pitch of the poles is not set to be less than 300 [y «m], the semiconductor in which the semiconductor pellet is mounted on the mounting surface of the mounting board made of a resin substrate having a low heat-resistant temperature with bump electrodes interposed therebetween. The number of pins in the device cannot be increased.
  • the film thickness accuracy of the contact solder formed by the screen printing method is low.
  • a connection failure occurs between the external terminal of the mounting board and one end of the bump electrode, and the semiconductor battery is mounted on the mounting surface of the mounting board made of a resin substrate having a low heat-resistant temperature via the bump electrode.
  • the yield of the semiconductor device mounting the semiconductor device is reduced.
  • Another object of the present invention is to increase the number of pins in a semiconductor device in which a semiconductor pellet is mounted via a bump electrode on a mounting surface of a mounting substrate made of a resin substrate having a low heat resistance temperature. To provide technology.
  • Another object of the present invention is to provide a technology capable of increasing the yield of a semiconductor device in which a semiconductor battery is mounted via a bump electrode on a mounting surface of a mounting substrate made of a resin substrate having a low heat resistance temperature. Is to provide.
  • a semiconductor pellet having a bump electrode on an external terminal wherein the bump electrode is formed from a surface side of the external terminal by a Pb film and a film thickness of the Pb film.
  • the bump electrode is formed from a surface side of the external terminal by a Pb film and a film thickness of the Pb film.
  • each of the thin Sn films is sequentially stacked.
  • Each of the Pb film and the Sn film is formed by a vapor deposition method.
  • the bump electrode at one end of the bump electrode, there is a Pb-Sn interface where Pb atoms and Sn atoms react to form a eutectic composition, so that one end of the bump electrode ( (Sn film) can be melted at the Pb-Sn eutectic temperature (183 [° C]).
  • the external terminals of the mounting board and one end of the bump electrode are connected to the Pb-Sn eutectic temperature (183 [° C] ), And can be electrically and mechanically connected, without using low-melting-point solder formed by screen printing, and on the mounting surface of a mounting substrate made of a resin substrate with a low heat-resistant temperature.
  • the semiconductor pellet can be mounted with a bump electrode interposed therebetween.
  • the semiconductor pellet can be mounted on the mounting surface of a mounting substrate made of a resin substrate having a low heat-resistant temperature without using a low-melting-point contact solder formed by the screen printing method
  • the screen printing method can be used.
  • the arrangement pitch of the external terminals of the mounting board, the external terminals of the semiconductor pellet, and the bump electrodes can be set without being restricted by the solder formed by the method described above. m].
  • the thickness accuracy of each of the Pb film and the Sn film formed by the vapor deposition method is higher than the film thickness accuracy of the contact solder formed by the screen printing method. Poor connection with the tip of the bump electrode can be prevented.
  • the mounting board made of a resin The yield of the semiconductor device in which the semiconductor pellet is mounted on the mounting surface with the bump electrode interposed therebetween can be improved.
  • FIG. 1 is a cross-sectional view of a semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 2 is a cross-sectional view of a main part of the mounting board showing a state before a mounting step is performed.
  • FIG. 3 is a plan view of the mounting board.
  • FIG. 4 is a cross-sectional view of a main part of the semiconductor pellet showing a state before a mounting process is performed.
  • FIG. 5 is a plan view of the semiconductor pellet.
  • FIG. 6 is a fragmentary cross-sectional view for explaining a method of forming the semiconductor pellet.
  • FIG. 7 is a fragmentary sectional view for explaining a method of forming the semiconductor pellet.
  • FIG. 8 is a fragmentary sectional view for explaining a method of forming the semiconductor pellet.
  • FIG. 9 is a fragmentary cross-sectional view for explaining a method of forming the semiconductor pellet.
  • FIG. 10 is a cross-sectional view for explaining a method for mounting the semiconductor pellet.
  • FIG. 11 is an enlarged sectional view of a main part for describing a method of mounting the semiconductor pellet.
  • FIG. 12 is a sectional view of a principal part showing a modification of the semiconductor pellet.
  • Fig. 13 explains the mounting method of the semiconductor pellet shown in Fig. 12 It is an important section enlarged sectional view for the.
  • FIG. 14 is a sectional view of a principal part showing another modified example of the semiconductor pellet.
  • FIG. 15 is a sectional view of a principal part showing another modification of the semiconductor pellet.
  • FIG. 16 is a cross-sectional view of a principal part of a semiconductor device that is Embodiment 2 of the present invention.
  • FIG. 17 is a plan view of a semiconductor pellet showing a state before a mounting process is performed.
  • FIG. 18 is a cross-sectional view of a base on which bump electrodes according to Embodiment 3 of the present invention are arranged.
  • FIG. 19 is an enlarged sectional view of a main part of the base.
  • FIG. 20 is a fragmentary cross-sectional view for explaining the method for forming the bump electrode.
  • FIG. 21 is a cross-sectional view for explaining a method of mounting a semiconductor battery using the bump electrode.
  • FIG. 22 is a cross-sectional view for explaining a method of mounting a semiconductor pellet using the bump electrodes.
  • FIG. 23 is a cross-sectional view for explaining a method of mounting a semiconductor pellet using the bump electrodes.
  • FIG. 24 is a sectional view showing a modification of the bump electrode.
  • FIG. 1 (cross-sectional view) shows a schematic configuration of a semiconductor device which is Embodiment 1 of the present invention.
  • the semiconductor device has a semiconductor pellet 8 mounted on a mounting surface of a mounting substrate 1 with a bump electrode 14 interposed therebetween.
  • the mounting board 1 includes, for example, a wiring board 2 and a thin film wiring layer 3.
  • the wiring board 2 is formed of, for example, a resin substrate in which glass fiber is impregnated with an epoxy resin or a polyimide resin.
  • the wiring board 2 has, for example, a multilayer wiring structure.
  • the thin film wiring layer 3 has a multilayer wiring structure in which, for example, polyimide resin is an insulated layer. That is, the mounting substrate 1 of the present embodiment has a structure in which a resin substrate in which glass fiber is impregnated with an epoxy resin or a polyimide resin is used as a base.
  • the heat-resistant temperature of the mounting board 1 in this case is about 260 [° C] ⁇ 60 seconds to about 120 seconds.
  • a plurality of external terminals 5 and a plurality of internal terminals 4 formed thereunder are arranged.
  • Each of the plurality of external terminals 5 is electrically and mechanically connected to each of the plurality of internal terminals 4 through an opening (reference numeral 3A shown in FIG. 2) formed in the final protective film 3B of the thin film wiring layer 3. It is connected to the.
  • a plurality of internal terminals 6 are arranged on the back surface of the wiring board 2 of the mounting board 1.
  • a spherical bump electrode 16 is electrically and mechanically connected to each of the plurality of internal terminals 6 via an external terminal 7.
  • the bump electrode 16 is made of, for example, a Pb-Sn alloy material.
  • the semiconductor pellet 8 includes a semiconductor substrate 9 made of, for example, single crystal silicon. It is mainly composed. On the element formation surface (the lower surface in FIG. 1) of the semiconductor substrate 9, a logic circuit system, a storage circuit system, or a mixed circuit system thereof is mounted. A plurality of external terminals 13 and a plurality of internal terminals 11 formed thereunder are arranged on the element formation surface of the semiconductor substrate 9. Each of the plurality of external terminals 13 is electrically and mechanically connected to each of the plurality of internal terminals 11 through openings (reference numeral 12 C shown in FIG. 4) formed in the final protective film 12. ing.
  • Each of the plurality of internal terminals 11 is formed on the uppermost wiring layer among wiring layers for electrically connecting the semiconductor elements formed on the element forming surface of the semiconductor substrate 9, for example, an A1 film or It is formed of an A1 alloy film.
  • Each of the plurality of internal terminals 11 is insulated and separated from the semiconductor substrate 9 by an interlayer insulating film 12.
  • the external terminals 5 of the mounting board 1 and the external terminals 13 of the semiconductor pellet 8 are electrically and mechanically connected by bump electrodes 14. In other words, the semiconductor pellet 8 is mounted on the mounting surface of the mounting board 1 using the CCB mounting technology.
  • a resin 15 is filled in a gap region between the mounting board 1 and the semiconductor pellet 8.
  • the resin 15 is formed of, for example, an insulating resin obtained by adding a silicone filler, a curing accelerator, a coupling agent, and the like to an epoxy-based thermosetting resin.
  • the external terminals 5 of the mounting substrate 1 are formed with a base metal film (BLM: Ball Limit) of the bump electrodes 14 in order to ensure high wettability with the bump electrodes 14. ing etalization).
  • BBM Ball Limit
  • the external terminals 5 are not limited to this structure, as shown in FIG. 2 (a cross-sectional view of a main part of the mounting board showing a state before the mounting process is performed), the final terminals are placed on the front side of the internal terminals 4. It has a laminated structure in which a metal film 20 having adhesiveness to the protective film 3B, a metal film 21 having wettability to the bump electrode 14 and a metal film 22 having non-oxidizing property are sequentially laminated. It is configured.
  • the metal film 20 is formed of a refractory metal film, for example, a Cr film, and its thickness is set to, for example, about 0.1 [m].
  • the metal film 21 is formed of, for example, a Cu film, and the thickness thereof is set to, for example, about 0.5 to 5 [ ⁇ ].
  • the metal film 22 is formed of, for example, an Au film, and its thickness is set to about 0.1 [ ⁇ ].
  • the external terminal 7 is configured as a base metal film for the bump electrode 16 in order to ensure high wettability with the bump electrode 16.
  • the external terminal 7 is not limited to this structure, but has the same configuration as the external terminal 5 described above.
  • the external terminal 5 and the external terminal 7 are electrically connected to each other via a wiring 3 C, a through-hole wiring 2 B, and an electrode 6.
  • the through-hole wiring 2B is formed on the inner wall surface of the through-hole 2A formed in the wiring board 2. Since the through holes 2A are formed by mechanical processing (for example, drilling), it is extremely difficult to set the arrangement pitch to 300 [/ im] or less. However, since the mounting board 1 of this embodiment is composed of the wiring board 2 and the thin film wiring layer 3, the arrangement pitch of the internal terminals 4 and the external terminals 5 must be set to 300 [m] or less. Can be.
  • Each of the internal terminal 4 and the external terminal 5 is formed by photolithography technology. Has been established. This photolithography technique can reduce the arrangement pitch of each of the internal terminals 4 and the external terminals 5 to about 100 [ ⁇ ].
  • the external terminals 5 of the mounting board 1 of this embodiment are arranged at an arrangement pitch of 100 [ ⁇ m], as shown in FIG. 3 (a plan view of the mounting board showing a state before the mounting process is performed). Have been. In FIG. 3, the dashed line indicates the mounting position of the semiconductor pellet 8.
  • the external terminal 13 of the semiconductor pellet 8 is formed as a base metal film (BLM: B ⁇ al 1 imiting ⁇ letalization) of the bump electrode 14 in order to ensure high wettability with the bump electrode 14. ing.
  • the external terminal 13 is not limited to this structure, but as shown in FIG. 4 (a cross-sectional view of a main part of the semiconductor pellet before the mounting process is performed), the surface of the internal terminal 11 is From the metal film 20 having an adhesive property to the final protective film 12, the metal film 21 having a wettability to the bump electrode 14, and the metal film 22 having a non-oxidizing property. It has a laminated structure.
  • the metal film 20 is formed of a refractory metal film, for example, a Cr film, and its thickness is set to, for example, about 0.1 [m].
  • the metal film 21 is formed of, for example, a Cu film, and its thickness is set to, for example, about 0.5 to 5 [m].
  • the metal film 22 is formed of, for example, an Au film, and its thickness is set to about 0.1 [m].
  • the final protective film 12 has a laminated structure in which, for example, a silicon nitride film 12A and a silicon oxide film 12B are sequentially laminated.
  • Each of the internal terminal 11 and the external terminal 13 is formed by photolithography. This photolithography technique can reduce the arrangement pitch of the internal terminals 11 and the external terminals 13 to about 100 [in].
  • the external terminals 13 of the semiconductor pellet 8 of this embodiment are As shown in the figure (a plan view of a semiconductor pellet showing a state before a mounting step is performed), the semiconductor pellets are arranged at an arrangement pitch of 100 [m].
  • the bump electrode 14 is formed by forming a Pb film 14B and a Sn film 14A thinner than the Pb film 14B from the surface side of the external terminal 13 respectively. It has a laminated structure in which layers are sequentially laminated.
  • the thickness of the Pb film 14B is set to, for example, about 50 to: L O O [m]
  • the thickness of the Sn film 14A is set to, for example, about 0.4 to 4 [ ⁇ m].
  • Each of the Pb film 14B and the Sn film 14A is formed by a vacuum evaporation method.
  • the bump electrode 14 is formed by sequentially laminating the Pb film 14 B and the Sn film 14 A thinner than the Pb film 14 B from the surface side of the external terminal 13.
  • the bump electrodes 14 are formed by a lift-off method using photolithography technology.
  • the lift-off method using the photolithography technique can reduce the arrangement pitch of the bump electrodes 14 to about 100 [m].
  • the bump electrodes 14 of this embodiment are arranged at an arrangement pitch of 100 [m].
  • the bump electrode 14 is not subjected to a step of forming the shape into a spherical shape by heat treatment, that is, not subjected to a wet back treatment. That is, as shown in FIGS. 4 and 5, the shape of the bump electrode 14 is formed in a truncated cone shape, and its vertical cross-sectional shape is formed in a trapezoidal shape.
  • a method of manufacturing the semiconductor pellet 8 will be described with reference to FIG. 6 to FIG. 9 (cross-sectional views showing main parts in respective manufacturing steps).
  • a semiconductor wafer composed of a semiconductor substrate 9 made of single crystal silicon is prepared.
  • semiconductor elements are formed on the surface of the semiconductor wafer (the element formation surface of the semiconductor substrate 9), and wiring, interlayer insulating films 10, internal terminals 11, final protective films 12, etc. are formed on the surface of the semiconductor elements.
  • a plurality of semiconductor pellet forming regions having substantially the same circuit system mounted on the surface of a semiconductor wafer are formed in a matrix.
  • the final protective film 12 has a laminated structure in which a silicon nitride film 12A and a silicon oxide film 12B are laminated.
  • the internal terminal 11 is formed by a photolithography technique, for example, an A1 film or an A1 alloy film.
  • an opening 12 C for exposing the surface of the internal terminal 11 is formed in the final protective film 12.
  • the final protective film 12 is adhered to the final protective film 12 on the surface of the final protective film 12 including the surface of the internal terminal 11 exposed from the opening 12C.
  • a metal film 20 having a wettability, a metal film 21 having a wettability to the bump electrode 14 and a metal film 22 having a non-oxidizing property are sequentially laminated.
  • Each of the metal film 20, metal film 21, and metal film 22 is deposited by, for example, a sputtering method.
  • the metal film 20 is formed of a refractory metal film, for example, a Cr film, and its thickness is set to, for example, about 0.1 [m].
  • the metal film 21 is formed of, for example, a Cu film, and its thickness is set to, for example, about 0.5 to 5 ⁇ .
  • the metal film 22 is formed of, for example, an Au film, and its thickness is set to about 0.1 [m].
  • a photoresist mask 23 is formed on the surface of the final protective film 12. This photoresist mask 23 is formed by a photolithography technique.
  • Pb and Sn were sequentially deposited on the entire surface of the semiconductor wafer (semiconductor substrate 9) by a vacuum deposition method, and a Pb film 14 was formed on the surface of the external terminal 13 as shown in FIG.
  • a laminate composed of B and the Sn film 14A is formed.
  • a similar laminated body is also formed on the surface of the photoresist mask 23.
  • the shape of the laminated body formed on the surface of the external terminal 13 is formed in a truncated cone shape, and its vertical cross-sectional shape is formed in a trapezoid shape. This laminate is separated from the laminate formed on the surface of the photoresist mask 23.
  • the thickness accuracy of each of the Pb film 14B and the Sn film 14A is higher than the thickness accuracy of the contact solder formed by the screen printing method.
  • the photoresist mask 23 is removed using a lift-off method, and the laminate (Pb film 14B, Sn film 14A) on the surface of the photoresist mask 23 is removed.
  • a bump electrode 14 having a laminated structure composed of the Pb film 14B and the Sn film 14A is formed. Since the thickness accuracy of each of the Pb film 14B and the Sn film 14A is high, the height of each bump electrode 14 is uniform.
  • the semiconductor wafer is divided for each semiconductor belt. And the semiconductor pellet shown in Fig. 5. Cut 8 is formed. Since the bump electrodes 14 are not subjected to the wet-back process, the height of each bump electrode 14 can be made uniform.
  • the mounting board 1 shown in FIGS. 2 and 3 is prepared, and the semiconductor pellet 8 shown in FIGS. 4 and 5 is prepared.
  • the arrangement pitch of the external terminals 5 of the mounting board 1 is set to 100 [ ⁇ ].
  • the arrangement pitch of the external terminals 13 and the bump electrodes 14 of the semiconductor pellet 8 is set to 100 [ ⁇ m].
  • the semiconductor pellet 8 is arranged on the mounting surface of the mounting board 1, and the external terminals 5 of the mounting board 1 and the external terminals 13 of the semiconductor pellet 8 are connected to each other.
  • a bump electrode 14 is arranged between them.
  • a heat treatment is performed to electrically and mechanically connect the external terminals 5 of the mounting substrate 1 to one end (511 film 14) of the bump electrode 14.
  • the heat treatment is performed in an atmosphere at a temperature slightly higher than the Pb-Sn eutectic temperature (183 [at]) at which Pb atoms and Sn atoms react to form a eutectic structure.
  • a reaction layer (intermetallic compound layer) 24 is formed between the external terminal 5 of the mounting board 1 and one end of the bump electrode 14, so that mounting is performed.
  • the external terminal 5 of the substrate 1 and one end of the bump electrode 14 can be firmly fixed.
  • the bump electrodes 14 are formed on the mounting surface of the mounting board 1 made of a resin substrate having a low heat resistance temperature without using a solder formed on the surface of the external terminal 5 of the mounting board 1 by a screen printing method.
  • the semiconductor pellet 8 can be mounted therebetween.
  • Each of the metal film 22 of the external terminal 5 and the metal film 22 of the external terminal 13 is a bump electrode. Absorbed in 14
  • a resin 15 is filled in a gap region between the mounting board 1 and the semiconductor pellet 8. Thereafter, by forming a spherical bump electrode 16 on the surface of the external terminal 7 of the mounting board 1, the semiconductor device shown in FIG. 1 is almost completed.
  • Each of the Sn films 14A, which is thinner than the thickness of the film 14B, is formed in a laminated structure in which they are sequentially laminated.
  • Pb—Sn interface where Pb atoms and Sn atoms react to form a eutectic composition.
  • Sn film can be melted at Pb-Sn eutectic temperature (183 [° C]).
  • the external terminals 5 of the mounting substrate 1 and the tips of the bump electrodes 14 are connected to the Pb-Sn eutectic temperature. (183 [° C]), making it possible to connect electrically and mechanically without using a low melting point solder formed by screen printing.
  • the semiconductor pellet 8 can be mounted on the mounting surface of the mounting substrate 1 made of a substrate via the bump electrodes 14.
  • the semiconductor pellet 8 is interposed on the mounting surface of the mounting substrate 1 made of a resin substrate having a low heat resistance with a bump electrode 14 interposed therebetween.
  • the external terminals 5 of the mounting substrate 1 and the external terminals of the semiconductor pellet 8 can be mounted without being restricted by the low-melting-point composition solder formed by the screen printing method.
  • the arrangement pitch of the electrodes 13 and the bump electrodes 14 can be set, and the arrangement pitch of the bump electrodes 14 can be set to 300 [ ⁇ or less. As a result, it is possible to increase the number of pins of the semiconductor device in which the semiconductor pellet 8 is mounted on the mounting surface of the mounting substrate 1 made of a resin substrate having a low heat-resistant temperature with the bump electrode 14 interposed therebetween.
  • Each of the Pb film 14 B and the S ⁇ film 14 ⁇ is formed by a vacuum evaporation method.
  • the film thickness accuracy of each of the Pb film 14B and Sn film 14A formed by the vapor deposition method is smaller than the film thickness accuracy of the low-melting-point solder formed by the screen printing method. Therefore, poor connection between the external terminal 5 of the mounting board 1 and one end of the bump electrode 14 can be prevented.
  • the yield of a semiconductor device in which the semiconductor pellet 8 is mounted on the mounting surface of the mounting substrate 1 made of a resin substrate having a low heat-resistant temperature with the bump electrode 14 interposed therebetween can be increased.
  • the metal film 20 having wettability with respect to the final protective film 12 may be formed of a refractory metal film, for example, a Ti film.
  • the metal film 21 having wettability to the bump electrode 14 may be formed of, for example, a Ni film.
  • each of the external terminal 5 and the external terminal 13 is a metal film having a non-oxidizing property, a metal film having an adhesive property to a final protective film, a metal film having a wettability to the bump electrode 14,
  • Each of the non-oxidizing metal films may be sequentially laminated to form a laminated structure.
  • the bump electrode 14 is formed of a Sn film 14 A and a film thickness of the Sn film 14 A from the surface side of the external terminal 13.
  • a Pb film 14B thicker than the Pb film 14B and an Sn film 14A thinner than the Pb film 14B may be formed in a laminated structure.
  • a reaction layer intermetallic compound layer
  • the external terminals 13 of the semiconductor pellet 8 and the other end of the bump electrode 14 can be firmly fixed.
  • the bump electrode 14 has a Pb film 14 B, which is thinner than the Pb film 14 B from the surface side of the external terminal 13.
  • Each of the multilayer films 14C including the Sn film 14C1 and the Pb film 14C2 may be sequentially laminated.
  • one end of the bump electrode 14 is determined by the Pb—Sn eutectic temperature (183 [° C]). (Multilayer film 14 C) can be reliably melted.
  • Multilayer film 1 4 C of S n film 14 C 1, P b film 14 C 2 are each of a thickness of 3 7 [wt 0/0] P b - 63 [ wt. /. ] It is set to the film thickness of the alloy layer of the composition before and after.
  • the bump electrode 14 is a multilayer film composed of a Sn film 14 C 1 and a Pb film 14 C 2 from the surface side of the external terminal 13.
  • 14 C, a Pb film 14 B thicker than the thickness of the multilayer film 14 C, and a thinner Sn film 14 C 1 and a Pb film 14 C 2 than the Pb film 14 B May be formed in a laminated structure in which the respective multilayer films 14C are sequentially laminated.
  • the bump electrode since there are a plurality of Pb-Sn interfaces at one end and the other end of the bump electrode, the bump electrode depends on the Pb-Sn eutectic temperature (183 [° C]). It is possible to surely melt one end (the multilayer film 14C) of 14 and the other end.
  • the bump electrodes 14 are formed from the surface side of the external terminals 13 by an Sn film 14A, a P film having a thickness larger than that of the Sn film 14A.
  • b film 14B, a multilayer film 14C comprising a Sn film 14C1 and a Pb film 14C2 thinner than the thickness of the Pb film 14B
  • a multilayer film 14 C composed of an Sn film 14 C 1 and a Pb film 14 C 2, compared with the film thickness of the multilayer film 14 C
  • the Pb film 14B may have a stacked structure in which a thick Pb film 14B and a Sn film 14A thinner than the thickness of the Pb film 14B are sequentially stacked.
  • FIG. 1 A schematic configuration of a semiconductor device according to the second embodiment of the present invention is shown in FIG.
  • the semiconductor belt 8 and the semiconductor component 26 are mounted on the mounting surface of the mounting board 1.
  • the semiconductor pellet 8 is mounted on the mounting surface of the mounting board 1 with the bump electrode 14 interposed therebetween. That is, the semiconductor pallet 8 is mounted in the CCB scheme (ontroled C_ollaps eB_onding).
  • the mounting substrate 1 is formed of, for example, a resin substrate in which glass fiber is impregnated with an epoxy resin or a polyimide resin.
  • the heat-resistant temperature of the mounting board 1 is about 260 [° C] ⁇ 60 seconds to about 120 seconds.
  • the external terminals 5 of the mounting board 1 and the external terminals 13 of the semiconductor bellet 8 are electrically and mechanically connected by bump electrodes 14.
  • Each of the external terminals 5 of the mounting substrate 1 and the external terminals 13 of the semiconductor pellet 8 is provided with a base metal film (BLM: B_all limiting M) of the bump electrode 14 in order to ensure high wettability with the bump electrode 14. .etalization).
  • BBM base metal film
  • Each of the external terminal 5 and the external terminal 13 is not limited to this structure. However, as in the first embodiment, the external terminal 5 and the external terminal 13 are wetted by the metal film having an adhesive property to the final protective film and the bump electrode 14. Metal film, non-oxidizing gold It has a laminated structure in which the metal films are sequentially laminated.
  • the bump electrode 14 is formed of a Pb film (14B) and an Sn film (14A) thinner than the Pb film from the surface side of the external terminal 13 in the same manner as in the first embodiment. ) Are sequentially laminated.
  • solder 27 is, for example, 3 7 [weight. /. ] Pb-63 [weight. /. ] It is formed of an alloy material having a composition of Sn. This alloy material has a melting point of about 18 3 [° C].
  • the external terminals 13 and the bump electrodes 14 of the semiconductor pellet 8 are 200 [m ] Are arranged at an arrangement pitch of.
  • the external terminals 5 of the mounting board 1 are similarly arranged at an arrangement pitch of 200 [m].
  • the mounting board 1 and the semiconductor pellet 8 are prepared.
  • the arrangement pitch of the external terminals 5 of the mounting board 1 is set to 200 m].
  • a solder paste material 37 [% by weight] Pb-63 [% by weight] Sn
  • the arrangement pitch of the external terminals 13 and the bump electrodes 14 of the semiconductor pellet 8 is set to 200 [m].
  • the semiconductor pellet 8 and the semiconductor component 26 are arranged on the mounting surface of the mounting substrate 1, and a bump electrode is provided between the external terminal 5 of the mounting substrate 1 and the external terminal 13 of the semiconductor pellet 8. 1 4 and solder paste material between the external terminals 2 ⁇ of the mounting board 1 and the leads 26 ⁇ of the semiconductor component 26. Place.
  • heat treatment is performed to electrically and mechanically connect the external terminals 5 of the mounting substrate 1 to one end of the bump electrodes 14, and to connect the external terminals 25 of the mounting substrate 1 to the leads of the semiconductor components 26.
  • 26 A is electrically and mechanically connected with solder 27.
  • the heat treatment is performed in an atmosphere at a temperature slightly higher than the Pb-Sn eutectic temperature (183 [° C]) at which Pb atoms and Sn atoms react to form a eutectic structure.
  • a reaction layer (intermetallic compound layer) is formed between the external terminal 5 of the mounting substrate 1 and one end of the bump electrode 14, so that the external terminal 5 of the mounting substrate 1 and the bump electrode 14 are formed.
  • One end can be firmly fixed.
  • the bump electrodes 14 are formed on the mounting surface of the mounting substrate 1 made of a resin substrate having a low heat resistance temperature without using a solder formed on the surface of the external terminal 5 of the mounting substrate 1 by a screen printing method.
  • the semiconductor bellet 8 can be mounted with the interposition.
  • a resin 15 is filled in a gap region between the mounting board 1 and the semiconductor pellet 8 to substantially complete the semiconductor device shown in FIG.
  • FIG. 18 (sectional view) shows a schematic configuration of the bump electrode according to the third embodiment of the present invention.
  • a plurality of bump electrodes 14 are arranged on a substrate 30.
  • the base 30 is composed of, for example, a support substrate 3 OA made of a single-crystal silicon substrate and a silicon oxide film 30 B formed on the support substrate 30 A and having poor wettability to the bump electrodes 14. It is configured. That is, Each of the plurality of bump electrodes 14 is disposed on the silicon oxide film 30B having poor wettability.
  • the bump electrode 14 is formed from the front side of the silicon oxide film 30B as compared with the Sn film 14A and the film thickness of the Sn film 14A. It has a stacked structure in which a thick Pb film 14B and an Sn film 14A thinner than the thickness of the Pb film 14B are sequentially stacked. That is, the bump electrode 14 has a configuration in which the Sn film 14A thinner than the film thickness is provided on one surface and the back surface of the Pb film 14B.
  • the base 30 itself may be formed of a material such as ceramics having poor wettability to the bump electrode (solder) 14. Further, the base 30 may be composed of a support substrate 3 OA and a metal film such as a r film having poor wettability to the bump electrodes (solder) 14.
  • the base 30 is prepared.
  • a mask 31 exposing a part of the surface is formed on the surface of the base 30.
  • the mask 31 is formed of, for example, a photo resist film formed by a photolithography technique.
  • an Sn film 14 A, a Pb film 14 B thicker than the Sn film 14 A, and a Pb film 14 B thicker than the Pb film 14 B is sequentially formed by a vacuum deposition method.
  • Electrodes 14 are formed.
  • the base 30 is disposed on the mounting surface of the mounting substrate 1 and the bump electrodes 14 are disposed on the external terminals 5 on the mounting surface of the mounting substrate 1.
  • the bump electrodes 14 firmly connected to the external terminals 5 of the mounting substrate 1 And transferred to the mounting board 1.
  • the semiconductor pellet 8 is arranged on the mounting surface of the mounting board 1, and the external terminals 5 of the mounting board 1 and the external terminals 13 of the semiconductor pellet 8 are connected to each other.
  • a bump electrode 14 is arranged between them.
  • the bump electrode 14 is formed. Since the Pb—Sn interface exists at one end of the electrode 14 and the other end, the external terminal 5 of the mounting board 1 and one end of the bump electrode 14 are shared by Pb—Sn. At the crystallographic temperature (183 [° C]), it can be electrically and mechanically connected, and the external end of the semiconductor pellet 8 The element 13 and the other end of the bump electrode 14 can be electrically and mechanically connected at the Pb—Sn eutectic temperature (183 [° C]).
  • the bump electrode 14 is composed of a multilayer film 14 C composed of an Sn film 14 C 1 and a Pb film 14 C 2 from the surface side of the substrate 30.
  • a multilayer film 14 composed of a Pb film 14 B thicker than the thickness of the multilayer film 14 C and a Sn film 14 C 1 and a Pb film 14 C 2 thinner than the thickness of the Pb film 14 B It is also possible to form a laminated structure in which each of C is sequentially laminated. In this case, since there are a plurality of Pb-Sn interfaces at one end and the other end of the bump electrode, the bump electrode depends on the Pb-Sn eutectic temperature (183 [° C]). It is possible to surely melt one end of the 14 (multilayer film 14 C) and the other end.
  • the bump electrodes 14 are formed from the surface side of the base 30 from the Sn film 14 A, the Pb film 14 B, and the Pb film 14 B, which are thicker than the Sn film 14 A.
  • Each of the Sn films 14A, which is thinner than the film thickness of B may be formed in a laminated structure in which each of them is sequentially laminated.

Abstract

A semiconductor pellet having bump electrodes on external terminals. The bump electrode comprises a laminate structure of a Pb layer and a thinner Sn layer on the surface of the external terminal. In this way, the semiconductor pellet can be connected to the surface of a resin substrate having a low heat resistance through the bump electrode without using a low-melting preparatory solder. A semiconductor device with an increased number of pins can be realized by connecting the semiconductor pellet through the bump electrodes to a resin substrate having a low heat resistance. The yield of the semiconductor device can be improved by using the semiconductor pellet with the bump electrodes, together with a resin substrate having a low heat resistance.

Description

明 棚 半導体ペレツ 卜及びその実装方法並びにバンプ電極 技術分野  Akira shelf semiconductor pellet, its mounting method, and bump electrode
本発明は、 実装基板の実装面上にバンプ電極を介在して半導体ペレ ッ 卜を実装する実装技術に関するものである。 背景技術  The present invention relates to a mounting technique for mounting a semiconductor pellet on a mounting surface of a mounting substrate with a bump electrode interposed. Background art
実装基板の実装面上に半導体ペレツ トを実装する実装技術において、 耐熱温度の低い樹脂基板からなる実装基板の実装面上にバンプ電極を 介在して半導体ぺレッ トを実装する C C B (_Controled C_ollaPse B_ onding) 実装技術が、 I E E E [Controlled Collapse Chip Con nection(C 4 )' Ann Enabling Technology, 1 9 94、 PP. 38 7 〜 3 94 ] に開示されている。 この C C B実装技術は、 高融点組成か らなるバンプ電極及び低融点組成からなる迎え半田を用いて半導体ぺ レッ トを実装している。 以下、 C CB実装技術による実装方法につい て説明する。 In a mounting technology for mounting a semiconductor pellet on a mounting surface of a mounting board, a semiconductor pellet is mounted on a mounting surface of a mounting board made of a resin substrate having a low heat resistance with a bump electrode interposed between the mounting board and the CCB (_Controlled C_olla P). se B_onding) An implementation technology is disclosed in IEEE [Controlled Collapse Chip Connection (C4) 'Ann Enabling Technology, 1993, PP. 378-394]. In this CCB mounting technology, a semiconductor pellet is mounted using bump electrodes made of a high-melting point composition and solders made of a low-melting point composition. The mounting method using the CCB mounting technology is described below.
まず、 実装基板及び半導体ペレッ トを準備する。 実装基板は例えば ガラス繊維にエポキシ樹脂を含浸させた樹脂基板で形成されている。 この場合の実装基板の耐熱温度は 2 6 0 [°C] X 6 0秒〜 1 2 0秒程 度である。 半導体ペレッ トは、 その主面の外部端子上にバンプ電極を 有している。 バンプ電極は例えば 9 9〜 9 5 [重量％ ] P b — 1〜 5 [重量％] S nの組成の合金材で形成されている。 この場合のバンプ 電極の融点は 3 1 8〜 3 2 5 [°C] 程度である。 半導体ペレッ トの主 面の外部端子は、 バンプ電極との高い濡れ性を確保するため、 下地金 属膜 ( B L M ： B_all L_initing _etalizat丄 on)で構成されて ゝる。 この外部端子は、 半導体ペレツ 卜の最終保護膜に形成された開口を通 して下層の内部端子に接続されている。 下地金属膜は、 この構造に限 定されないが、 下層の内部端子の表面側から、 半導体ペレッ トの最終 保護膜に対して接着性を有する金属膜（例えば C r膜）、 バンプ電極に 対して濡れ性を有する金属膜（例えば C u膜）、 非酸化性を有する金属 膜（例えば A u膜）の夫々を順次積層した積層構造で構成されている。 次に、 前記実装基板の実装面の外部端子の表面上にスクリーン印刷 法でペース卜状の迎え半田を形成（印刷）する。 迎え半田は例えば 3 7 [重量％] P b - 6 3 [重量％] S nの共晶組成で形成されている。 この場合の迎え半田の融点は 1 8 3 ( P b— S n共晶温度） C ] 程度 である。 スクリーン印刷法は、 スクリーンマスク上に置かれたペース ト状の迎え半田をスキージによリスク リーンマスクの開口部から実装 基板の実装面の外部端子の表面上に転写する方法である。 First, a mounting board and a semiconductor pellet are prepared. The mounting substrate is formed of, for example, a resin substrate in which glass fiber is impregnated with an epoxy resin. In this case, the heat resistant temperature of the mounting board is about 260 [° C] × 60 seconds to about 120 seconds. The semiconductor pellet has a bump electrode on an external terminal on its main surface. The bump electrode is made of, for example, an alloy material having a composition of 99 to 95 [wt%] Pb—1 to 5 [wt%] Sn. In this case, the melting point of the bump electrode is about 318 to 325 [° C]. Main of semiconductor pellets The external terminals on the surface are made of a base metal film (BLM: B_all L_initing_etalizaton) to ensure high wettability with the bump electrodes. This external terminal is connected to the lower internal terminal through an opening formed in the final protective film of the semiconductor pellet. The underlying metal film is not limited to this structure, but may be used for the metal film (for example, Cr film) that has adhesiveness to the final protective film of the semiconductor pellet and the bump electrode from the surface side of the lower internal terminal. It has a laminated structure in which a wettable metal film (for example, a Cu film) and a non-oxidizable metal film (for example, an Au film) are sequentially laminated. Next, a paste solder is formed (printed) on the surface of the external terminal on the mounting surface of the mounting substrate by a screen printing method. The welcome solder is formed of, for example, a eutectic composition of 37 [wt%] Pb-6 3 [wt%] Sn. In this case, the melting point of the solder is about 18 3 (Pb—Sn eutectic temperature) C]. The screen printing method is a method in which paste paste solder placed on a screen mask is transferred by a squeegee from the opening of the risk-lean mask onto the external terminals on the mounting surface of the mounting board.
次に、 前記実装基板の実装面上に前記半導体べレッ 卜を配置すると 共に、 実装基板の外部端子と半導体ペレツ 卜の外部端子との間にバン プ電極を配置する。 実装基板の外部端子とバンプ電極の一端部との間 には、 ペースト状の迎え半田が介在されている。  Next, the semiconductor bellet is arranged on the mounting surface of the mounting board, and a bump electrode is arranged between an external terminal of the mounting board and an external terminal of the semiconductor pellet. A paste-like solder is interposed between the external terminal of the mounting board and one end of the bump electrode.
次に、 1 8 3 ( P b— S n共晶温度） [ °C ] よりも若干高めの温度で 熱処理を施して、 前記ペースト状の迎え半田を溶融し、 次に凝固し、 実装基板の実装面の外部端子とバンプ電極の一端部とを固着する。 こ れにより、 耐熱温度の低い樹脂基板からなる実装基板の実装面上にバ ンプ電極を介在して半導体ぺレツ 卜を実装することができる。  Next, a heat treatment is performed at a temperature slightly higher than 18 3 (Pb—Sn eutectic temperature) [° C] to melt the paste-like solder, and then solidify it, The external terminals on the mounting surface and one end of the bump electrode are fixed. Thus, the semiconductor pellet can be mounted on the mounting surface of the mounting substrate made of a resin substrate having a low heat-resistant temperature with the bump electrode interposed therebetween.
なお、 バンプ電極を S nの含有量 [重量％] が少ない高融点組成の P b - S n合金材で形成する理由は、 実装基板と半導体べレツ 卜との 熱膨張係数の差に起因するバンプ電極の破損を防止するためである。 バンプ電極は、 S nの含有量 [重量％] の増加に伴って硬くなる。 発明の開示 In addition, the bump electrode has a high melting point composition with a small Sn content [wt%]. The reason for the formation of the Pb-Sn alloy material is to prevent the bump electrodes from being damaged due to the difference in thermal expansion coefficient between the mounting substrate and the semiconductor pellet. The bump electrode becomes harder as the Sn content [% by weight] increases. Disclosure of the invention
前記高融点組成からなるバンプ電極及び低融点組成からなる迎え半 田を用いて半導体ペレツ トを実装する C C B実装技術は、 実装基板の 外部端子の表面上にスクリーン印刷法でペースト状の迎え半田を形成 した後、 実装基板の実装面上に半導体ペレッ トを配置し、 その後、 熱 処理を施して半導体ペレッ トを実装している。 このため、 ペース卜状 の迎え半田を形成する工程に相当する分、 実装時の工程数が増加する < また、 スク リーン印刷法は、 スク リーンマスク上に置かれたペース ト状の迎え半田をスキージによリスクリーンマスクの開口部から実装 基板の実装面の外部端子の表面上に転写する方法であるが、 スク リー ンマスクの開口部の配列ピッチは 3 0 0 ί μ ττι ] 程度が限界である。 一方、 実装基板の外部端子の配列ピッチは、 薄膜配線層に外部端子を 形成すれば 1 0 0 [ ^ m] 程度まで微細化することができる。 また、 半導体ペレツ 卜の外部端子の配列ピッチは、 フォ トリソグラフィ技術 で外部端子を形成すれば 1 0 0 [ μ m] 程度まで微細化することがで きる。 また、 バンプ電極の配列ピッチは、 フォ トリソグラフィ技術を 用いたリ フ トオフ法でバンプ電極を形成すれば 1 0 0 [ μ ιη ] 程度ま で微細化することができる。 しかしながら、 スクリーンマスクの開口 部の配列ピッチは 3 0 0 [ /i m ] 程度が限界であるので、 実装基板の 外部端子、 半導体ペレッ トの外部端子、 バンプ電極の夫々の配列ピッ チが迎え半田の配列ピッチで制約されてしまう。 このため、 バンプ電 極の配列ピッチを 3 0 0 [ y« m ] 以下に設定することがでないので、 耐熱温度の低い樹脂基板からなる実装基板の実装面上にバンプ電極を 介在して半導体ペレツ 卜を実装する半導体装置の多ピン化を図ること ができない。 The CCB mounting technology for mounting a semiconductor pellet using the bump electrode made of the high melting point composition and the receiving solder made of the low melting point composition is based on a paste-shaped solder solder that is screen-printed on the surface of the external terminal of the mounting board. After formation, the semiconductor pellet is placed on the mounting surface of the mounting board, and then heat treated to mount the semiconductor pellet. For this reason, the number of steps for mounting is increased by an amount corresponding to the step of forming the paste-like solder. <Screen printing method uses a paste-like solder placed on a screen mask. This is a method in which a squeegee is used to transfer the image from the opening of the rescreen mask onto the surface of the external terminals on the mounting surface of the mounting board. However, the arrangement pitch of the opening of the screen mask is limited to about 300 0μττι]. is there. On the other hand, the arrangement pitch of the external terminals on the mounting substrate can be reduced to about 100 [^ m] by forming the external terminals on the thin film wiring layer. In addition, the arrangement pitch of the external terminals of the semiconductor pellet can be reduced to about 100 [μm] by forming the external terminals by photolithography. In addition, the arrangement pitch of the bump electrodes can be reduced to about 100 [μιη] by forming the bump electrodes by a lift-off method using photolithography technology. However, since the arrangement pitch of the openings of the screen mask is limited to about 300 [/ im], the arrangement pitch of the external terminals of the mounting board, the external terminals of the semiconductor pellet, and the bump electrodes is met by the solder pitch. It is restricted by the arrangement pitch. For this reason, the bump Since the arrangement pitch of the poles is not set to be less than 300 [y «m], the semiconductor in which the semiconductor pellet is mounted on the mounting surface of the mounting board made of a resin substrate having a low heat-resistant temperature with bump electrodes interposed therebetween. The number of pins in the device cannot be increased.
また、 スクリーン印刷法で形成される迎え半田の膜厚精度は低い。 このため、 実装基板の外部端子とバンプ電極の一端部とを接続する接 続不良が発生し、 耐熱温度の低い樹脂基板からなる実装基板の実装面 上にバンプ電極を介在して半導体べレッ トを実装する半導体装置の歩 留まりが低下する。  Also, the film thickness accuracy of the contact solder formed by the screen printing method is low. As a result, a connection failure occurs between the external terminal of the mounting board and one end of the bump electrode, and the semiconductor battery is mounted on the mounting surface of the mounting board made of a resin substrate having a low heat-resistant temperature via the bump electrode. The yield of the semiconductor device mounting the semiconductor device is reduced.
本発明の目的は、 低融点組成の迎え半田を使用することなく、 耐熱 温度の低い樹脂基板からなる実装基板の実装面上にバンプ電極を介在 して半導体べレッ 卜を実装することが可能な技術を提供することにあ る。  It is an object of the present invention to be able to mount a semiconductor bellet on a mounting surface of a mounting substrate made of a resin substrate having a low heat-resistant temperature via a bump electrode without using a solder having a low melting point composition. It is to provide technology.
また、 本発明の他の目的は、 耐熱温度の低い樹脂基板からなる実装 基板の実装面上にバンプ電極を介在して半導体ペレツ トを実装する半 導体装置の多ピン化を図ることが可能な技術を提供することにある。  Another object of the present invention is to increase the number of pins in a semiconductor device in which a semiconductor pellet is mounted via a bump electrode on a mounting surface of a mounting substrate made of a resin substrate having a low heat resistance temperature. To provide technology.
また、 本発明の他の目的は、 耐熱温度の低い樹脂基板からなる実装 基板の実装面上にバンプ電極を介在して半導体べレッ トを実装する半 導体装置の歩留まりを高めることが可能な技術を提供することにある。 本発明の前記ならびにその他の目的と新規な特徴は、 本明細書の記 述及び添付図面によって明らかになるであろう。  Another object of the present invention is to provide a technology capable of increasing the yield of a semiconductor device in which a semiconductor battery is mounted via a bump electrode on a mounting surface of a mounting substrate made of a resin substrate having a low heat resistance temperature. Is to provide. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
本願において開示される発明のうち、 代表的なものの概要を簡単に 説明すれば、 下記のとおりである。  The following is a brief description of the outline of typical inventions disclosed in the present application.
外部端子上にバンプ電極を有する半導体ペレツ 卜であって、 前記バ ンプ電極を、 前記外部端子の表面側から、 P b膜、 この P b膜の膜厚 に比べて薄い S n膜の夫々を順次積層した積層構造で構成する。 P b 膜、 S n膜の夫々は蒸着法で形成されている。 A semiconductor pellet having a bump electrode on an external terminal, wherein the bump electrode is formed from a surface side of the external terminal by a Pb film and a film thickness of the Pb film. In this case, each of the thin Sn films is sequentially stacked. Each of the Pb film and the Sn film is formed by a vapor deposition method.
前述の手段によれば、 バンプ電極の一端部には P b原子と S n原子 とが反応して共晶組成を形成する P b - S n界面が存在するので、 バ ンプ電極の一端部 （ S n膜） を P b— S n共晶温度（1 8 3 [ °C ] )で 溶融することができる。 この結果、 実装基板の実装面上に半導体ペレ ッ 卜を実装する実装時において、 実装基板の外部端子とバンプ電極の 一端部とを P b— S n共晶温度（1 8 3 [ °C ] )で電気的にかつ機械的 に接続することができるので、 スクリーン印刷法で形成される低融点 組成の迎え半田を使用することなく、 耐熱温度の低い樹脂基板からな る実装基板の実装面上にバンプ電極を介在して半導体ぺレッ トを実装 することができる。  According to the above-described means, at one end of the bump electrode, there is a Pb-Sn interface where Pb atoms and Sn atoms react to form a eutectic composition, so that one end of the bump electrode ( (Sn film) can be melted at the Pb-Sn eutectic temperature (183 [° C]). As a result, when mounting the semiconductor pellet on the mounting surface of the mounting board, the external terminals of the mounting board and one end of the bump electrode are connected to the Pb-Sn eutectic temperature (183 [° C] ), And can be electrically and mechanically connected, without using low-melting-point solder formed by screen printing, and on the mounting surface of a mounting substrate made of a resin substrate with a low heat-resistant temperature. The semiconductor pellet can be mounted with a bump electrode interposed therebetween.
また、 スクリーン印刷法で形成された低融点組成の迎え半田を使用 することなく、 耐熱温度の低い樹脂基板からなる実装基板の実装面上 に半導体ペレツ 卜を実装することができるので、 スクリーン印刷法で 形成される迎え半田の制約を受けずに、 実装基板の外部端子、 半導体 ペレツ 卜の外部端子、 バンプ電極の夫々の配列ピッチを設定すること ができ、 バンプ電極の配列ピッチを 3 0 0 [ m ] 以下にすることが できる。 この結果、 耐熱温度の低い樹脂基板からなる実装基板の実装 面上にバンプ電極を介在して半導体ペレツ 卜を実装する半導体装置の 多ピン化を図ることができる。  In addition, since the semiconductor pellet can be mounted on the mounting surface of a mounting substrate made of a resin substrate having a low heat-resistant temperature without using a low-melting-point contact solder formed by the screen printing method, the screen printing method can be used. The arrangement pitch of the external terminals of the mounting board, the external terminals of the semiconductor pellet, and the bump electrodes can be set without being restricted by the solder formed by the method described above. m]. As a result, it is possible to increase the number of pins of a semiconductor device in which a semiconductor pellet is mounted on a mounting surface of a mounting substrate made of a resin substrate having a low heat-resistant temperature with a bump electrode interposed therebetween.
また、 蒸着法で形成される P b膜、 S n膜の夫々の膜厚精度は、 ス ク リーン印刷法で形成される迎え半田の膜厚精度に比べて高いので、 実装基板の外部端子とバンプ電極の先端部との接続不良を防止するこ とができる。 この結果、 耐熱温度の低い樹脂基板からなる実装基板の 実装面上にバンプ電極を介在して半導体ペレツ 卜を実装する半導体装 置の歩留まりを高めることができる。 図面の簡単な説明 In addition, the thickness accuracy of each of the Pb film and the Sn film formed by the vapor deposition method is higher than the film thickness accuracy of the contact solder formed by the screen printing method. Poor connection with the tip of the bump electrode can be prevented. As a result, the mounting board made of a resin The yield of the semiconductor device in which the semiconductor pellet is mounted on the mounting surface with the bump electrode interposed therebetween can be improved. BRIEF DESCRIPTION OF THE FIGURES
第 1図は、 本発明の実施形態 1である半導体装置の断面図である。 第 2図は、 実装工程が施される前の状態を示す実装基板の要部断面 図である。  FIG. 1 is a cross-sectional view of a semiconductor device according to Embodiment 1 of the present invention. FIG. 2 is a cross-sectional view of a main part of the mounting board showing a state before a mounting step is performed.
第 3図は、 前記実装基板の平面図である。  FIG. 3 is a plan view of the mounting board.
第 4図は、 実装工程が施される前の状態を示す半導体ペレツ 卜の要 部断面図である。  FIG. 4 is a cross-sectional view of a main part of the semiconductor pellet showing a state before a mounting process is performed.
第 5図は、 前記半導体ペレツ 卜の平面図である。  FIG. 5 is a plan view of the semiconductor pellet.
第 6図は、 前記半導体ペレツ 卜の形成方法を説明するための要部断 面図である。  FIG. 6 is a fragmentary cross-sectional view for explaining a method of forming the semiconductor pellet.
第 7図は、 前記半導体ペレツ 卜の形成方法を説明するための要部断 面図である。  FIG. 7 is a fragmentary sectional view for explaining a method of forming the semiconductor pellet.
第 8図は、 前記半導体ペレツ 卜の形成方法を説明するための要部断 面図である。  FIG. 8 is a fragmentary sectional view for explaining a method of forming the semiconductor pellet.
第 9図は、 前記半導体ペレツ 卜の形成方法を説明するための要部断 面図である。  FIG. 9 is a fragmentary cross-sectional view for explaining a method of forming the semiconductor pellet.
第 1 0図は、 前記半導体ペレツ 卜の実装方法を説明するための断面 図である。  FIG. 10 is a cross-sectional view for explaining a method for mounting the semiconductor pellet.
第 1 1図は、 前記半導体ペレツ 卜の実装方法を説明するための要部 拡大断面図である。  FIG. 11 is an enlarged sectional view of a main part for describing a method of mounting the semiconductor pellet.
第 1 2図は、 前記半導体ペレツ 卜の変形例を示す要部断面図である。 第 1 3図は、 第 1 2図に示す半導体ペレッ トの実装方法を説明する ための要部拡大断面図である。 FIG. 12 is a sectional view of a principal part showing a modification of the semiconductor pellet. Fig. 13 explains the mounting method of the semiconductor pellet shown in Fig. 12 It is an important section enlarged sectional view for the.
第 1 4図は、 前記半導体ペレツ 卜の他の変形例を示す要部断面図で ある。  FIG. 14 is a sectional view of a principal part showing another modified example of the semiconductor pellet.
第 1 5図は、 前記半導体ペレツ 卜の他の変形例を示す要部断面図で ある。  FIG. 15 is a sectional view of a principal part showing another modification of the semiconductor pellet.
第 1 6図は、 本発明の実施形態 2である半導体装置の要部断面図で ある。  FIG. 16 is a cross-sectional view of a principal part of a semiconductor device that is Embodiment 2 of the present invention.
第 1 7図は、 実装工程が施される前の状態を示す半導体ペレツ 卜の 平面図である。  FIG. 17 is a plan view of a semiconductor pellet showing a state before a mounting process is performed.
第 1 8図は、 本発明の実施形態 3であるバンプ電極が配置された基 体の断面図である。  FIG. 18 is a cross-sectional view of a base on which bump electrodes according to Embodiment 3 of the present invention are arranged.
第 1 9図は、 前記基体の要部拡大断面図である。  FIG. 19 is an enlarged sectional view of a main part of the base.
第 2 0図は、 前記バンプ電極の形成方法を説明するための要部断面 図である。  FIG. 20 is a fragmentary cross-sectional view for explaining the method for forming the bump electrode.
第 2 1図は、 前記バンプ電極を用いた半導体べレッ 卜の実装方法を 説明するための断面図である。  FIG. 21 is a cross-sectional view for explaining a method of mounting a semiconductor battery using the bump electrode.
第 2 2図は、 前記バンプ電極を用いた半導体ペレツ 卜の実装方法を 説明するための断面図である。  FIG. 22 is a cross-sectional view for explaining a method of mounting a semiconductor pellet using the bump electrodes.
第 2 3図は、 前記バンプ電極を用いた半導体ペレツ 卜の実装方法を 説明するための断面図である。  FIG. 23 is a cross-sectional view for explaining a method of mounting a semiconductor pellet using the bump electrodes.
第 2 4図は、 前記バンプ電極の変形例を示す断面図である。 発明を実施するための最良の形態  FIG. 24 is a sectional view showing a modification of the bump electrode. BEST MODE FOR CARRYING OUT THE INVENTION
本発明の構成について、 実施形態とともに説明する。  The configuration of the present invention will be described together with embodiments.
なお、 実施形態を説明するための全図において、 同一機能を有する ものは同一符号を付け、 その繰り返しの説明は省略する。 Note that all the drawings for describing the embodiments have the same function. Those are denoted by the same reference numerals, and their repeated description is omitted.
(実施形態 1 )  (Embodiment 1)
本発明の実施形態 1である半導体装置の概略構成を第 1図（断面図） に示す。  FIG. 1 (cross-sectional view) shows a schematic configuration of a semiconductor device which is Embodiment 1 of the present invention.
第 1図に示すように、 半導体装置は、 実装基板 1の実装面上にバン プ電極 1 4を介在して半導体ペレツ 卜 8を実装している。  As shown in FIG. 1, the semiconductor device has a semiconductor pellet 8 mounted on a mounting surface of a mounting substrate 1 with a bump electrode 14 interposed therebetween.
前記実装基板 1は、 例えば配線基板 2及び薄膜配線層 3で構成され ている。 配線基板 2は例えばガラス繊維にエポキシ樹脂又はポリイミ ド樹脂を含浸させた樹脂基板で構成されている。 この配線基板 2は例 えば多層配線構造で構成されている。 薄膜配線層 3は例えばポリイミ ド樹脂を絶緣層とする多層配線構造で構成されている。 つまり、 本実 施例の実装基板基板 1は、 ガラス繊維にエポキシ樹脂又はポリイ ミ ド 樹脂を含浸させた樹脂基板を母体とする構造で構成されている。 この 場合の実装基板 1の耐熱温度は 2 6 0 [ °C ] X 6 0秒〜 1 2 0秒程度 である。  The mounting board 1 includes, for example, a wiring board 2 and a thin film wiring layer 3. The wiring board 2 is formed of, for example, a resin substrate in which glass fiber is impregnated with an epoxy resin or a polyimide resin. The wiring board 2 has, for example, a multilayer wiring structure. The thin film wiring layer 3 has a multilayer wiring structure in which, for example, polyimide resin is an insulated layer. That is, the mounting substrate 1 of the present embodiment has a structure in which a resin substrate in which glass fiber is impregnated with an epoxy resin or a polyimide resin is used as a base. The heat-resistant temperature of the mounting board 1 in this case is about 260 [° C] × 60 seconds to about 120 seconds.
前記実装基板 1の薄膜配線層 3には複数の外部端子 5及びその下層 に形成された複数の内部端子 4が配置されている。 この複数の外部端 子 5の夫々は薄膜配線層 3の最終保護膜 3 Bに形成された開口（第 2 図に示す符号 3 A )を通して複数の内部端子 4の夫々に電気的にかつ 機械的に接続されている。  In the thin film wiring layer 3 of the mounting board 1, a plurality of external terminals 5 and a plurality of internal terminals 4 formed thereunder are arranged. Each of the plurality of external terminals 5 is electrically and mechanically connected to each of the plurality of internal terminals 4 through an opening (reference numeral 3A shown in FIG. 2) formed in the final protective film 3B of the thin film wiring layer 3. It is connected to the.
前記実装基板 1の配線基板 2の裏面には複数の内部端子 6が配置さ れている。 この複数の内部端子 6の夫々には外部端子 7を介在して球 形状のバンプ電極 1 6が電気的にかつ機械的に接続されている。 バン プ電極 1 6は例えば P b - S n系の合金材で形成されている。  A plurality of internal terminals 6 are arranged on the back surface of the wiring board 2 of the mounting board 1. A spherical bump electrode 16 is electrically and mechanically connected to each of the plurality of internal terminals 6 via an external terminal 7. The bump electrode 16 is made of, for example, a Pb-Sn alloy material.
前記半導体ペレツ ト 8は例えば単結晶珪素からなる半導体基板 9 を 主体に構成されている。 半導体基板 9の素子形成面（第 1図において 下面）には論理回路システム、 記憶回路システム、 或はそれらの混合 回路システムが塔載されている。 また、 半導体基板 9の素子形成面上 には複数の外部端子 1 3及びその下層に形成された複数の内部端子 1 1が配置されている。 複数の外部端子 1 3の夫々は、 最終保護膜 1 2 に形成された開口（第 4図に示す符号 1 2 C )を通して複数の内部端子 1 1の夫々に電気的にかつ機械的に接続されている。 複数の内部端子 1 1の夫々は、 半導体基板 9の素子形成面に形成された半導体素子間 を電気的に接続する配線層のうち、 最上層の配線層に形成され、 例え ば A 1膜又は A 1合金膜で形成されている。 なお、 複数の内部端子 1 1の夫々は層間絶緣膜 1 2によって半導体基板 9から絶縁分離されて いる。 前記実装基板 1の外部端子 5と半導体ペレツ 卜 8の外部端子 1 3とはバンプ電極 1 4で電気的にかつ機械的に接続されている。 つ まり、 半導体ペレツ ト 8は実装基板 1 の実装面上に C C B実装技術で 実装されている。 The semiconductor pellet 8 includes a semiconductor substrate 9 made of, for example, single crystal silicon. It is mainly composed. On the element formation surface (the lower surface in FIG. 1) of the semiconductor substrate 9, a logic circuit system, a storage circuit system, or a mixed circuit system thereof is mounted. A plurality of external terminals 13 and a plurality of internal terminals 11 formed thereunder are arranged on the element formation surface of the semiconductor substrate 9. Each of the plurality of external terminals 13 is electrically and mechanically connected to each of the plurality of internal terminals 11 through openings (reference numeral 12 C shown in FIG. 4) formed in the final protective film 12. ing. Each of the plurality of internal terminals 11 is formed on the uppermost wiring layer among wiring layers for electrically connecting the semiconductor elements formed on the element forming surface of the semiconductor substrate 9, for example, an A1 film or It is formed of an A1 alloy film. Each of the plurality of internal terminals 11 is insulated and separated from the semiconductor substrate 9 by an interlayer insulating film 12. The external terminals 5 of the mounting board 1 and the external terminals 13 of the semiconductor pellet 8 are electrically and mechanically connected by bump electrodes 14. In other words, the semiconductor pellet 8 is mounted on the mounting surface of the mounting board 1 using the CCB mounting technology.
前記実装基板 1 と半導体ペレツ ト 8との間の隙間領域には樹脂 1 5 が充填されている。 樹脂 1 5は、 例えばエポキシ系熱硬化樹脂にシリ 力充填剤、 硬化促進剤、 カップリング剤等を添加した絶縁性樹脂で形 成されている。 このように、 実装基板 1 と半導体ペレッ ト 8との間の 隙間領域に樹脂 1 5を充填することにより、 バンプ電極 1 4の機械的 強度を樹脂 1 5の機械的強度で補うことができるので、 実装基板 1 と 半導体ペレツ ト 8との熱膨張係数の差に起因するバンプ電極 1 4の破 損を防止することができる。  A resin 15 is filled in a gap region between the mounting board 1 and the semiconductor pellet 8. The resin 15 is formed of, for example, an insulating resin obtained by adding a silicone filler, a curing accelerator, a coupling agent, and the like to an epoxy-based thermosetting resin. By filling the gap between the mounting board 1 and the semiconductor pellet 8 with the resin 15 as described above, the mechanical strength of the bump electrode 14 can be supplemented by the mechanical strength of the resin 15. In addition, it is possible to prevent the bump electrodes 14 from being damaged due to a difference in thermal expansion coefficient between the mounting substrate 1 and the semiconductor pellet 8.
前記実装基板 1の外部端子 5は、 バンプ電極 1 4 との高い濡れ性を 確保するため、 バンプ電極 1 4の下地金属膜 （B L M ： B all L imit ing etalization)として構成されている。 外部端子 5は、 この構造 に限定されないが、 第 2図 （実装工程が施される前の状態を示す実装 基板の要部断面図） に示すように、 内部端子 4の表面側から、 最終保 護膜 3 Bに対して接着性を有する金属膜 2 0、 バンプ電極 1 4に対し て濡れ性を有する金属膜 2 1 , 非酸化性を有する金属膜 2 2の夫々を 順次積層した積層構造で構成されている。 金属膜 2 0は高融点金属膜 である例えば C r膜で形成され、 その膜厚は例えば 0. 1 [ m] 程 度に設定されている。 金属膜 2 1は例えば C u膜で形成され、 その膜 厚は例えば 0. 5〜 5 [ μ πι] 程度に設定されている。 金属膜 2 2は 例えば A u膜で形成され、 その膜厚は 0. 1 [ μ ιη] 程度に設定され ている。 The external terminals 5 of the mounting substrate 1 are formed with a base metal film (BLM: Ball Limit) of the bump electrodes 14 in order to ensure high wettability with the bump electrodes 14. ing etalization). Although the external terminals 5 are not limited to this structure, as shown in FIG. 2 (a cross-sectional view of a main part of the mounting board showing a state before the mounting process is performed), the final terminals are placed on the front side of the internal terminals 4. It has a laminated structure in which a metal film 20 having adhesiveness to the protective film 3B, a metal film 21 having wettability to the bump electrode 14 and a metal film 22 having non-oxidizing property are sequentially laminated. It is configured. The metal film 20 is formed of a refractory metal film, for example, a Cr film, and its thickness is set to, for example, about 0.1 [m]. The metal film 21 is formed of, for example, a Cu film, and the thickness thereof is set to, for example, about 0.5 to 5 [μπι]. The metal film 22 is formed of, for example, an Au film, and its thickness is set to about 0.1 [μιη].
前記外部端子 7は、 バンプ電極 1 6との高い濡れ性を確保するため、 バンプ電極 1 6の下地金属膜として構成されている。 外部端子 7は、 この構造に限定されないが、 前述の外部端子 5 と同様に構成されてい る。  The external terminal 7 is configured as a base metal film for the bump electrode 16 in order to ensure high wettability with the bump electrode 16. The external terminal 7 is not limited to this structure, but has the same configuration as the external terminal 5 described above.
前記外部端子 5と外部端子 7とは、 配線 3 C、 スルーホール配線 2 B、 電極 6の夫々を介して電気的に接続されている。 スルーホール配 線 2 Bは、 配線基板 2に形成されたスルーホール 2 Aの内壁面に形成 されている。 このスルーホール 2 Aは機械的な加工（例えばドリル加 ェ）によって形成されるので、 その配列ピッチを 3 0 0 [ /i m] 以下 に設定するのは極めて困難である。 しかしながら、 本実施例の実装基 板 1は配線基板 2及び薄膜配線層 3で構成されているので、 内部端子 4、 外部端子 5の夫々の配列ピッチを 3 0 0 [ m] 以下に設定する ことができる。  The external terminal 5 and the external terminal 7 are electrically connected to each other via a wiring 3 C, a through-hole wiring 2 B, and an electrode 6. The through-hole wiring 2B is formed on the inner wall surface of the through-hole 2A formed in the wiring board 2. Since the through holes 2A are formed by mechanical processing (for example, drilling), it is extremely difficult to set the arrangement pitch to 300 [/ im] or less. However, since the mounting board 1 of this embodiment is composed of the wiring board 2 and the thin film wiring layer 3, the arrangement pitch of the internal terminals 4 and the external terminals 5 must be set to 300 [m] or less. Can be.
前記内部端子 4、 外部端子 5の夫々はフォ トリソグラフィ技術で形 成されている。 このフォ トリソグラフィ技術は内部端子 4、 外部端子 5の夫々の配列ピッチを 1 00 [μ πι] 程度まで微細化することがで きる。 本実施例の実装基板 1の外部端子 5は、 第 3図（実装工程が施 される前の状態を示す実装基板の平面図）に示すように、 1 00 [ μ m] の配列ピッチで配置されている。 なお、 第 3図において、 一点鎖 線は半導体ペレツ 卜 8の実装位置を示す。 Each of the internal terminal 4 and the external terminal 5 is formed by photolithography technology. Has been established. This photolithography technique can reduce the arrangement pitch of each of the internal terminals 4 and the external terminals 5 to about 100 [μπι]. The external terminals 5 of the mounting board 1 of this embodiment are arranged at an arrangement pitch of 100 [μm], as shown in FIG. 3 (a plan view of the mounting board showing a state before the mounting process is performed). Have been. In FIG. 3, the dashed line indicates the mounting position of the semiconductor pellet 8.
前記半導体ぺレッ ト 8の外部端子 1 3は、 バンプ電極 1 4との高い 濡れ性を確保するため、 バンプ電極 1 4の下地金属膜 （B LM ： B^al 1 imiting ^letalization)として構成されている。 外部端子 1 3は、 この構造に限定されないが、 第 4図（実装工程が施される前の状態を 示す半導体ペレツ 卜の要部断面図）に示すように、 内部端子 1 1の表 面側から、 最終保護膜 1 2に対して接着性を有する金属膜 2 0、 バン プ電極 1 4に対して濡れ性を有する金属膜 2 1、 非酸化性を有する金 属膜 2 2の夫々を順次積層した積層構造で構成されている。 金属膜 2 0は高融点金属膜である例えば C r膜で形成され、 その膜厚は例えば 0. 1 [ m] 程度に設定されている。 金属膜 2 1は例えば C u膜で 形成され、 その膜厚は例えば 0. 5〜 5 [ m] 程度に設定されてい る。 金属膜 2 2は例えば A u膜で形成され、 その膜厚は 0. 1 [ m] 程度に設定されている。 なお、 最終保護膜 1 2は、 例えば窒化珪素膜 1 2 A、 酸化珪素膜 1 2 Bの夫々を順次積層した積層構造で構成され ている。  The external terminal 13 of the semiconductor pellet 8 is formed as a base metal film (BLM: B ^ al 1 imiting ^ letalization) of the bump electrode 14 in order to ensure high wettability with the bump electrode 14. ing. The external terminal 13 is not limited to this structure, but as shown in FIG. 4 (a cross-sectional view of a main part of the semiconductor pellet before the mounting process is performed), the surface of the internal terminal 11 is From the metal film 20 having an adhesive property to the final protective film 12, the metal film 21 having a wettability to the bump electrode 14, and the metal film 22 having a non-oxidizing property. It has a laminated structure. The metal film 20 is formed of a refractory metal film, for example, a Cr film, and its thickness is set to, for example, about 0.1 [m]. The metal film 21 is formed of, for example, a Cu film, and its thickness is set to, for example, about 0.5 to 5 [m]. The metal film 22 is formed of, for example, an Au film, and its thickness is set to about 0.1 [m]. The final protective film 12 has a laminated structure in which, for example, a silicon nitride film 12A and a silicon oxide film 12B are sequentially laminated.
前記内部端子 1 1、 外部端子 1 3の夫々はフォ トリソグラフィ技術 で形成されている。 このフォ トリソグラフィ技術は内部端子 1 1、 外 部端子 1 3の夫々の配列ピッチを 1 0 0 [ in] 程度まで微細化する ことができる。 本実施例の半導体ぺレッ ト 8の外部端子 1 3は、 第 5 図 （実装工程が施される前の状態を示す半導体ペレッ トの平面図） に 示すように、 1 00 [ m] の配列ピッチで配置されている。 Each of the internal terminal 11 and the external terminal 13 is formed by photolithography. This photolithography technique can reduce the arrangement pitch of the internal terminals 11 and the external terminals 13 to about 100 [in]. The external terminals 13 of the semiconductor pellet 8 of this embodiment are As shown in the figure (a plan view of a semiconductor pellet showing a state before a mounting step is performed), the semiconductor pellets are arranged at an arrangement pitch of 100 [m].
前記バンプ電極 14は、 第 4図に示すように、 外部端子 1 3の表面 側から、 P b膜 14 B、 この P b膜 14 Bの膜厚に比べて薄い S n膜 14 Aの夫々を順次積層した積層構造で構成されている。 P b膜 14 Bの膜厚は例えば 50〜： L O O [ m] 程度に設定され、 S n膜 14 Aの膜厚は例えば 0. 4〜4 [^ m] 程度に設定されている。 P b膜 14 B、 S n膜 14 Aの夫々は真空蒸着法によって形成されている。 このように、 バンプ電極 14を、 外部端子 1 3の表面側から、 P b膜 14 B、 この P b膜 14 Bの膜厚に比べて薄い S n膜 14 Aの夫々を 順次積層した積層構造で構成することによ り、 バンプ電極 14の一端 部には P b原子と S n原子とが反応して共晶組成を形成する P b— S n界面が存在するので、 バンプ電極 14の一端部（ S n膜 14 A )を P b— S n共晶温度（1 8 3 [°C] )で溶融するこ とができる。  As shown in FIG. 4, the bump electrode 14 is formed by forming a Pb film 14B and a Sn film 14A thinner than the Pb film 14B from the surface side of the external terminal 13 respectively. It has a laminated structure in which layers are sequentially laminated. The thickness of the Pb film 14B is set to, for example, about 50 to: L O O [m], and the thickness of the Sn film 14A is set to, for example, about 0.4 to 4 [^ m]. Each of the Pb film 14B and the Sn film 14A is formed by a vacuum evaporation method. As described above, the bump electrode 14 is formed by sequentially laminating the Pb film 14 B and the Sn film 14 A thinner than the Pb film 14 B from the surface side of the external terminal 13. Since the Pb—Sn interface in which Pb atoms and Sn atoms react to form a eutectic composition exists at one end of the bump electrode 14, The portion (Sn film 14A) can be melted at the Pb-Sn eutectic temperature (183 [° C]).
前記バンプ電極 14は、 フォ トリソグラ フィ技術を用いたリフ トォ フ法で形成されている。 フォ トリソグラフィ技術を用いたリフ トオフ 法はバンプ電極 14の配列ピッチを 1 00 [ m ] 程度まで微細化す ることができる。 本実施例のバンプ電極 1 4は、 第 5図に示すように、 1 00 [ m] の配列ピッチで配置されている。  The bump electrodes 14 are formed by a lift-off method using photolithography technology. The lift-off method using the photolithography technique can reduce the arrangement pitch of the bump electrodes 14 to about 100 [m]. As shown in FIG. 5, the bump electrodes 14 of this embodiment are arranged at an arrangement pitch of 100 [m].
前記バンプ電極 14は、 熱処理によってその形状を球形状に成形す る工程、 即ちウエッ トバック処理が施されていない。 つまり、 バンプ 電極 14の形状は、 第 4図及び第 5図に示すように、 円錐台形状で形 成され、 その縦方向の断面形状は台状で形成されている。  The bump electrode 14 is not subjected to a step of forming the shape into a spherical shape by heat treatment, that is, not subjected to a wet back treatment. That is, as shown in FIGS. 4 and 5, the shape of the bump electrode 14 is formed in a truncated cone shape, and its vertical cross-sectional shape is formed in a trapezoidal shape.
次に、 前記半導体ペレッ ト 8の製造方法について、 第 6図乃至第 9 図 （各製造工程毎に示す要部断面図） を用いて説明する。 まず、 単結晶珪素からなる半導体基板 9で構成された半導体ゥェ一 ハを用意する。 Next, a method of manufacturing the semiconductor pellet 8 will be described with reference to FIG. 6 to FIG. 9 (cross-sectional views showing main parts in respective manufacturing steps). First, a semiconductor wafer composed of a semiconductor substrate 9 made of single crystal silicon is prepared.
次に、 前記半導体ゥエーハの表面（半導体基板 9の素子形成面）に半 導体素子、 その表面上に配線、 層間絶緣膜 1 0、 内部端子 1 1、 最終 保護膜 1 2等を形成し、 この半導体ゥエーハの表面に実質的に同一の 回路システムが塔載された半導体ぺレッ 卜形成領域を複数個行列状に 形成する。 最終保護膜 1 2は窒化珪素膜 1 2 A、 酸化珪素膜 1 2 Bの 夫々を積層した積層構造で構成されている。 内部端子 1 1は、 フォ ト リソグラフィ技術で形成され、 例えば A 1膜又は A 1合金膜で形成さ れている。  Next, semiconductor elements are formed on the surface of the semiconductor wafer (the element formation surface of the semiconductor substrate 9), and wiring, interlayer insulating films 10, internal terminals 11, final protective films 12, etc. are formed on the surface of the semiconductor elements. A plurality of semiconductor pellet forming regions having substantially the same circuit system mounted on the surface of a semiconductor wafer are formed in a matrix. The final protective film 12 has a laminated structure in which a silicon nitride film 12A and a silicon oxide film 12B are laminated. The internal terminal 11 is formed by a photolithography technique, for example, an A1 film or an A1 alloy film.
次に、 第 6図に示すように、 前記最終保護膜 1 2に前記内部端子 1 1の表面を露出させる開口 1 2 Cを形成する。  Next, as shown in FIG. 6, an opening 12 C for exposing the surface of the internal terminal 11 is formed in the final protective film 12.
次に、 第 7図に示すように、 前記開口 1 2 Cから露出された内部端 子 1 1の表面上を含む最終保護膜 1 2の表面上に、 この最終保護膜 1 2に対して接着性を有する金属膜 2 0、 バンプ電極 1 4に対して濡れ 性を有する金属膜 2 1、 非酸化性を有する金属膜 2 2の夫々を順次積 層する。 この金属膜 2 0、 金属膜 2 1、 金属膜 2 2の夫々は例えばス パッタ法で堆積される。 金属膜 2 0は、 高融点金属膜である例えば C r膜で形成され、 その膜厚は例えば 0 . 1 [ m ] 程度に設定される。 金属膜 2 1は例えば C u膜で形成され、 その膜厚は例えば 0 . 5〜5 ί μ τη ΐ 程度に設定される。 金属膜 2 2は例えば A u膜で形成され、 その膜厚は 0 . 1 [ m ] 程度に設定される。  Next, as shown in FIG. 7, the final protective film 12 is adhered to the final protective film 12 on the surface of the final protective film 12 including the surface of the internal terminal 11 exposed from the opening 12C. A metal film 20 having a wettability, a metal film 21 having a wettability to the bump electrode 14 and a metal film 22 having a non-oxidizing property are sequentially laminated. Each of the metal film 20, metal film 21, and metal film 22 is deposited by, for example, a sputtering method. The metal film 20 is formed of a refractory metal film, for example, a Cr film, and its thickness is set to, for example, about 0.1 [m]. The metal film 21 is formed of, for example, a Cu film, and its thickness is set to, for example, about 0.5 to 5 μμτηη. The metal film 22 is formed of, for example, an Au film, and its thickness is set to about 0.1 [m].
次に、 前記金属膜 2 2、 金属膜 2 1、 金属膜 2 0の夫々にパターン ニングを施し、 前記内部端子 1 1の表面上に、 金属膜 2 2、 金属膜 2 1、 金属膜 2 0の夫々からなる外部端子 1 3 を形成する。 この工程に おいて、 金属膜 22、 金属膜 21、 金属膜 20の夫々のパターンニン グは、 フォ トリソグラフィ技術で形成されたフォ トレジスト膜をマス クにして行なわれる。 つまり、 外部端子 1 3はフォ トリソグラフィ技 術で形成される。 Next, patterning is performed on each of the metal film 22, the metal film 21, and the metal film 20, and a metal film 22, a metal film 21, and a metal film 20 are formed on the surface of the internal terminal 11. An external terminal 13 is formed. In this process The patterning of each of the metal film 22, the metal film 21, and the metal film 20 is performed using a photoresist film formed by photolithography as a mask. That is, the external terminals 13 are formed by photolithography technology.
次に、 第 8図に示すように、 前記最終保護膜 1 2の表面上にフォ 卜 レジストマスク 23を形成する。 このフォ 卜レジストマスク 23はフ ォ 卜リソグラフィ技術で形成される。  Next, as shown in FIG. 8, a photoresist mask 23 is formed on the surface of the final protective film 12. This photoresist mask 23 is formed by a photolithography technique.
次に、 前記半導体ゥエーハ（半導体基板 9 )の全面に真空蒸着法で P b、 S nの夫々を順次蒸着し、 第 9図に示すように、 外部端子 1 3の 表面上に P b膜 14 Bと S n膜 1 4 Aとからなる積層体を形成する。 この工程において、 フォ トレジストマスク 23の表面上にも同様の積 層体が形成される。 外部端子 1 3の表面上に形成された積層体の形状 は円錐台形状で形成され、 その縦方向の断面形状は台形状で形成され る。 この積層体は、 フォ トレジストマスク 2 3の表面上に形成された 積層体と分離される。 なお、 P b膜 1 4 B、 S n膜 14 Aの夫々の膜 厚精度はスク リーン印刷法で形成される迎え半田の膜厚精度に比べて 高い。 次に、 リフ トオフ法を使用し、 前記フォ トレジストマスク 2 3を除去すると共に、 このフォ トレジス トマスク 23の表面上の積層 体 （P b膜 14 B、 S n膜 14 A) を除去する。 この工程において、 P b膜 14 Bと S n膜 14 Aとからなる積層構造のバンプ電極 14が 形成される。 なお、 P b膜 14 B、 S n膜 14 Aの夫々の膜厚精度が 高いので、 各バンプ電極 14の高さは均一になる。  Next, Pb and Sn were sequentially deposited on the entire surface of the semiconductor wafer (semiconductor substrate 9) by a vacuum deposition method, and a Pb film 14 was formed on the surface of the external terminal 13 as shown in FIG. A laminate composed of B and the Sn film 14A is formed. In this step, a similar laminated body is also formed on the surface of the photoresist mask 23. The shape of the laminated body formed on the surface of the external terminal 13 is formed in a truncated cone shape, and its vertical cross-sectional shape is formed in a trapezoid shape. This laminate is separated from the laminate formed on the surface of the photoresist mask 23. Note that the thickness accuracy of each of the Pb film 14B and the Sn film 14A is higher than the thickness accuracy of the contact solder formed by the screen printing method. Next, the photoresist mask 23 is removed using a lift-off method, and the laminate (Pb film 14B, Sn film 14A) on the surface of the photoresist mask 23 is removed. In this step, a bump electrode 14 having a laminated structure composed of the Pb film 14B and the Sn film 14A is formed. Since the thickness accuracy of each of the Pb film 14B and the Sn film 14A is high, the height of each bump electrode 14 is uniform.
次に、 前記半導体ゥエーハ（半導体基板 9)の表面に形成された半導 体ペレツ ト形成領域間をダイシングし、 半導体ゥェ一ハを各半導体べ レッ ト毎に分割することにより、 第 4図及び第 5図に示す半導体ペレ ッ ト 8が形成される。 なお、 バンプ電極 1 4はウエッ トバック処理が 施されていないので、 各バンプ電極 1 4の高さを均一にすることがで さる。 Next, by dicing between the semiconductor pellet forming regions formed on the surface of the semiconductor wafer (semiconductor substrate 9), the semiconductor wafer is divided for each semiconductor belt. And the semiconductor pellet shown in Fig. 5. Cut 8 is formed. Since the bump electrodes 14 are not subjected to the wet-back process, the height of each bump electrode 14 can be made uniform.
次に、 前記半導体装置の形成方法を説明しながら、 前記半導体ペレ ッ ト 8の実装方法について説明する。  Next, a method for mounting the semiconductor pellet 8 will be described while explaining a method for forming the semiconductor device.
まず、 第 2図及び第 3図に示す実装基板 1 を準備すると共に、 第 4 図及び第 5図に示す半導体ペレツ ト 8 を準備する。 実装基板 1の外部 端子 5の配列ピッチは、 1 0 0 [ μ ιη ] に設定されている。 また、 半 導体ペレツ 卜 8の外部端子 1 3及びバンプ電極 1 4の配列ピッチは、 1 0 0 [ μ m ] に設定されている。  First, the mounting board 1 shown in FIGS. 2 and 3 is prepared, and the semiconductor pellet 8 shown in FIGS. 4 and 5 is prepared. The arrangement pitch of the external terminals 5 of the mounting board 1 is set to 100 [μιη]. The arrangement pitch of the external terminals 13 and the bump electrodes 14 of the semiconductor pellet 8 is set to 100 [μm].
次に、 第 1 0図に示すように、 前記実装基板 1の実装面上に半導体 ペレッ ト 8を配置すると共に、 実装基板 1 の外部端子 5と半導体べレ ッ ト 8の外部端子 1 3との間にバンプ電極 1 4 を配置する。  Next, as shown in FIG. 10, the semiconductor pellet 8 is arranged on the mounting surface of the mounting board 1, and the external terminals 5 of the mounting board 1 and the external terminals 13 of the semiconductor pellet 8 are connected to each other. A bump electrode 14 is arranged between them.
次に、 熱処理を施し、 実装基板 1 の外部端子 5とバンプ電極 1 4の 一端部 （ 5 11膜1 4 ） とを電気的にかつ機械的に接続する。 熱処理 は、 P b原子と S n原子とが反応して共晶組織を形成する P b — S n 共晶温度 （ 1 8 3 [で] ) よりも若干高い温度雰囲気中で行う。 この 工程において、 第 1 1図に示すように、 実装基板 1の外部端子 5とバ ンプ電極 1 4の一端部との間に反応層（金属間化合物層） 2 4が形成さ れるので、 実装基板 1の外部端子 5とバンプ電極 1 4の一端部とを強 固に固着することができる。 つまり、 実装基板 1の外部端子 5の表面 上にスクリーン印刷法で形成される迎え半田を使用することなく、 耐 熱温度の低い樹脂基板からなる実装基板 1の実装面上にバンプ電極 1 4を介在して半導体ペレツ 卜 8を実装することができる。 なお、 外部 端子 5の金属膜 2 2、 外部端子 1 3の金属膜 2 2の夫々はバンプ電極 1 4に吸収される。 Next, a heat treatment is performed to electrically and mechanically connect the external terminals 5 of the mounting substrate 1 to one end (511 film 14) of the bump electrode 14. The heat treatment is performed in an atmosphere at a temperature slightly higher than the Pb-Sn eutectic temperature (183 [at]) at which Pb atoms and Sn atoms react to form a eutectic structure. In this step, as shown in FIG. 11, a reaction layer (intermetallic compound layer) 24 is formed between the external terminal 5 of the mounting board 1 and one end of the bump electrode 14, so that mounting is performed. The external terminal 5 of the substrate 1 and one end of the bump electrode 14 can be firmly fixed. In other words, the bump electrodes 14 are formed on the mounting surface of the mounting board 1 made of a resin substrate having a low heat resistance temperature without using a solder formed on the surface of the external terminal 5 of the mounting board 1 by a screen printing method. The semiconductor pellet 8 can be mounted therebetween. Each of the metal film 22 of the external terminal 5 and the metal film 22 of the external terminal 13 is a bump electrode. Absorbed in 14
次に、 前記実装基板 1 と半導体ペレツ 卜 8との間の隙間領域に樹脂 1 5を充填する。 この後、 実装基板 1の外部端子 7の表面上に球形状 のバンプ電極 1 6を形成することにより、 第 1図に示す半導体装置が ほぼ完成する。  Next, a resin 15 is filled in a gap region between the mounting board 1 and the semiconductor pellet 8. Thereafter, by forming a spherical bump electrode 16 on the surface of the external terminal 7 of the mounting board 1, the semiconductor device shown in FIG. 1 is almost completed.
このように、 本実施例によれば、 以下の作用効果が得られる。  As described above, according to the present embodiment, the following operational effects can be obtained.
( 1 ) 外部端子 1 3上にバンプ電極 1 4 を有する半導体ペレツ ト 8で あって、 前記バンプ電極 1 4 を、 前記外部端子 1 3の表面側から、 P b膜 1 4 B、 この P b膜 1 4 Bの膜厚に比べて薄い S n膜 1 4 Aの夫 々を順次積層した積層構造で構成する。 この構成により、 バンプ電極 1 4の一端部には P b原子と S n原子とが反応して共晶組成を形成す る P b — S n界面が存在するので、 バンプ電極 1 4の一端部（S n膜） を P b — S n共晶温度（1 8 3 [ °C ] )で溶融することができる。 この 結果、 実装基板 1の実装面上に半導体ペレ 'ノ 卜 8を実装する実装時に おいて、 実装基板 1の外部端子 5とバンプ電極 1 4の先端部とを P b 一 S n共晶温度 （ 1 8 3 [ °C ] ) で電気的にかつ機械的に接続するこ とができるので、 スクリーン印刷法で形成される低融点組成の迎え半 田を使用することなく、 耐熱温度の低い樹脂基板からなる実装基板 1 の実装面上にバンプ電極 1 4を介在して半導体ぺレッ ト 8を実装する ことができる。  (1) A semiconductor pellet 8 having a bump electrode 14 on an external terminal 13, wherein the bump electrode 14 is formed from a surface of the external terminal 13 by a Pb film 14 B, Each of the Sn films 14A, which is thinner than the thickness of the film 14B, is formed in a laminated structure in which they are sequentially laminated. With this configuration, at one end of the bump electrode 14, there is a Pb—Sn interface where Pb atoms and Sn atoms react to form a eutectic composition. (Sn film) can be melted at Pb-Sn eutectic temperature (183 [° C]). As a result, when mounting the semiconductor pellet 8 on the mounting surface of the mounting substrate 1, the external terminals 5 of the mounting substrate 1 and the tips of the bump electrodes 14 are connected to the Pb-Sn eutectic temperature. (183 [° C]), making it possible to connect electrically and mechanically without using a low melting point solder formed by screen printing. The semiconductor pellet 8 can be mounted on the mounting surface of the mounting substrate 1 made of a substrate via the bump electrodes 14.
また、 スクリーン印刷法で形成される低融点組成の迎え半田を使用 することなく、 耐熱温度の低い樹脂基板からなる実装基板 1の実装面 上にバンプ電極 1 4 を介在して半導体ぺレッ ト 8 を実装することがで きるので、 スクリーン印刷法で形成される低融点組成の迎え半田の制 約を受けずに、 実装基板 1の外部端子 5、 半導体ペレツ 卜 8の外部端 子 1 3、 バンプ電極 1 4の夫々の配列ピッチを設定することができ、 バンプ電極 1 4の配列ピッチを 3 0 0 [ μ τ ΐ 以下にすることができ る。 この結果、 耐熱温度の低い樹脂基板からなる実装基板 1の実装面 上にバンプ電極 1 4を介在して半導体ペレツ 卜 8を実装する半導体装 置の多ピン化を図ることができる。 Also, without using a low melting point solder formed by a screen printing method, the semiconductor pellet 8 is interposed on the mounting surface of the mounting substrate 1 made of a resin substrate having a low heat resistance with a bump electrode 14 interposed therebetween. As a result, the external terminals 5 of the mounting substrate 1 and the external terminals of the semiconductor pellet 8 can be mounted without being restricted by the low-melting-point composition solder formed by the screen printing method. The arrangement pitch of the electrodes 13 and the bump electrodes 14 can be set, and the arrangement pitch of the bump electrodes 14 can be set to 300 [μτΐ or less. As a result, it is possible to increase the number of pins of the semiconductor device in which the semiconductor pellet 8 is mounted on the mounting surface of the mounting substrate 1 made of a resin substrate having a low heat-resistant temperature with the bump electrode 14 interposed therebetween.
( 2 ) 前記 P b膜 1 4 B、 S η膜 1 4 Αの夫々を真空蒸着法で形成す る。 この構成により、 蒸着法で形成される P b膜 1 4 B、 S n膜 1 4 Aの夫々の膜厚精度は、 スクリーン印刷法で形成される低融点組成の 迎え半田の膜厚精度に比べて高いので、 実装基板 1の外部端子 5とバ ンプ電極 1 4の一端部との接続不良を防止することができる。 この結 果、 耐熱温度の低い樹脂基板からなる実装基板 1の実装面上にバンプ 電極 1 4を介在して半導体ぺレッ ト 8を実装する半導体装置の歩留ま リを高めることができる。 (2) Each of the Pb film 14 B and the S η film 14 Α is formed by a vacuum evaporation method. With this configuration, the film thickness accuracy of each of the Pb film 14B and Sn film 14A formed by the vapor deposition method is smaller than the film thickness accuracy of the low-melting-point solder formed by the screen printing method. Therefore, poor connection between the external terminal 5 of the mounting board 1 and one end of the bump electrode 14 can be prevented. As a result, the yield of a semiconductor device in which the semiconductor pellet 8 is mounted on the mounting surface of the mounting substrate 1 made of a resin substrate having a low heat-resistant temperature with the bump electrode 14 interposed therebetween can be increased.
なお、 前記最終保護膜 1 2に対して濡れ性を有する金属膜 2 0は高 融点金属膜である例えば T i膜で形成してもよい。  The metal film 20 having wettability with respect to the final protective film 12 may be formed of a refractory metal film, for example, a Ti film.
また、 前記バンプ電極 1 4に対して濡れ性を有する金属膜 2 1は例 えば N i膜で形成してもよい。  Further, the metal film 21 having wettability to the bump electrode 14 may be formed of, for example, a Ni film.
また、 前記外部端子 5、 外部端子 1 3の夫々は、 非酸化性を有する 金属膜、 最終保護膜に対して接着性を有する金属膜、 バンプ電極 1 4 に対して濡れ性を有する金属膜、 非酸化性を有する金属膜の夫々を順 次積層した積層構造で構成してもよい。  Further, each of the external terminal 5 and the external terminal 13 is a metal film having a non-oxidizing property, a metal film having an adhesive property to a final protective film, a metal film having a wettability to the bump electrode 14, Each of the non-oxidizing metal films may be sequentially laminated to form a laminated structure.
また、 前記バンプ電極 1 4は、 第 1 2図 （要部断面図） に示すよう に、 外部端子 1 3の表面側から、 S n膜 1 4 A、 この S n膜 1 4 Aの 膜厚に比べて厚い P b膜 1 4 B、 この P b膜 1 4 Bの膜厚に比べて薄 い S n膜 1 4 Aの夫々を順次積層した積層構造で構成してもよい。 こ の場合、 第 1 3図 （要部拡大断面図） に示すように、 半導体ペレッ ト 8の外部端子 1 3とバンプ電極 14の他端部との間にも反応層（金属 間化合物層） 24が形成されるので、 半導体ペレツ ト 8の外部端子 1 3とバンプ電極 14の他端部とを強固に固着することができる。 Further, as shown in FIG. 12 (a cross-sectional view of a main part), the bump electrode 14 is formed of a Sn film 14 A and a film thickness of the Sn film 14 A from the surface side of the external terminal 13. Alternatively, a Pb film 14B thicker than the Pb film 14B and an Sn film 14A thinner than the Pb film 14B may be formed in a laminated structure. This In this case, as shown in FIG. 13 (enlarged sectional view of the main part), a reaction layer (intermetallic compound layer) is also provided between the external terminal 13 of the semiconductor pellet 8 and the other end of the bump electrode 14. Thus, the external terminals 13 of the semiconductor pellet 8 and the other end of the bump electrode 14 can be firmly fixed.
また、 前記バンプ電極 14は、 第 14図 （要部断面図） に示すよう に、 外部端子 1 3の表面側から、 P b膜 14 B、 この P b膜 14 Bの 膜厚に比べて薄い S n膜 14 C 1と P b膜 1 4 C 2とからなる多層膜 14 Cの夫々を順次積層した積層構造で構成してもよい。 この場合、 バンプ電極 14の一端部には複数の P b— S n界面が存在することに なるので、 P b— S n共晶温度（ 1 83 [°C] )によるバンプ電極 14 の一端部（多層膜 14 C)の溶融を確実に行うことができる。 多層膜 1 4 Cの S n膜 14 C 1、 P b膜 14 C 2の夫々の膜厚は 3 7 [重量0 /0] P b - 63 [重量。/。] 前後の組成の合金層による膜厚に設定されてい る。 Further, as shown in FIG. 14 (a cross-sectional view of a main part), the bump electrode 14 has a Pb film 14 B, which is thinner than the Pb film 14 B from the surface side of the external terminal 13. Each of the multilayer films 14C including the Sn film 14C1 and the Pb film 14C2 may be sequentially laminated. In this case, since there are a plurality of Pb—Sn interfaces at one end of the bump electrode 14, one end of the bump electrode 14 is determined by the Pb—Sn eutectic temperature (183 [° C]). (Multilayer film 14 C) can be reliably melted. Multilayer film 1 4 C of S n film 14 C 1, P b film 14 C 2 are each of a thickness of 3 7 [wt 0/0] P b - 63 [ wt. /. ] It is set to the film thickness of the alloy layer of the composition before and after.
また、 前記バンプ電極 14は、 第 1 5図（要部断面図）に示すように、 外部端子 1 3の表面側から、 S n膜 14 C 1 と P b膜 14 C 2とから なる多層膜 14 C、 この多層膜 14 Cの膜厚に比べて厚い P b膜 14 B、 この P b膜 14 Bの膜厚に比べて薄い S n膜 14 C 1と P b膜 1 4 C 2とからなる多層膜 14 Cの夫々を順次積層した積層構造で構成 してもよい。 この場合、 バンプ電極の一端部及び他端部には複数の P b— S n界面が存在することになるので、 P b— S n共晶温度 （ 1 8 3 [°C] ) によるバンプ電極 14の一端部（多層膜 1 4 C)、 その他端 部の夫々の溶融を確実に行うことができる。  Further, as shown in FIG. 15 (a cross-sectional view of a main part), the bump electrode 14 is a multilayer film composed of a Sn film 14 C 1 and a Pb film 14 C 2 from the surface side of the external terminal 13. 14 C, a Pb film 14 B thicker than the thickness of the multilayer film 14 C, and a thinner Sn film 14 C 1 and a Pb film 14 C 2 than the Pb film 14 B May be formed in a laminated structure in which the respective multilayer films 14C are sequentially laminated. In this case, since there are a plurality of Pb-Sn interfaces at one end and the other end of the bump electrode, the bump electrode depends on the Pb-Sn eutectic temperature (183 [° C]). It is possible to surely melt one end (the multilayer film 14C) of 14 and the other end.
また、 前記バンプ電極 14は、 図示していないが、 外部端子 1 3の 表面側から、 S n膜 14 A、 この S n膜 14 Aの膜厚に比べて厚い P b膜 1 4 B、 この P b膜 1 4 Bの膜厚に比べて薄い S n膜 1 4 C 1 と P b膜 1 4 C 2とからなる多層膜 1 4 Cの夫々を順次積層した積層構 造、 若しくは、 外部端子 1 3の表面側から、 S n膜 1 4 C 1 と P b膜 1 4 C 2とからなる多層膜 1 4 C、 この多層膜 1 4 Cの膜厚に比べて 厚い P b膜 1 4 B、 この P b膜 1 4 Bの膜厚に比べて薄い S n膜 1 4 Aの夫々を順次積層した積層構造で構成してもよい。 Although not shown, the bump electrodes 14 are formed from the surface side of the external terminals 13 by an Sn film 14A, a P film having a thickness larger than that of the Sn film 14A. b film 14B, a multilayer film 14C comprising a Sn film 14C1 and a Pb film 14C2 thinner than the thickness of the Pb film 14B From the surface side of the structure or the external terminal 13, a multilayer film 14 C composed of an Sn film 14 C 1 and a Pb film 14 C 2, compared with the film thickness of the multilayer film 14 C The Pb film 14B may have a stacked structure in which a thick Pb film 14B and a Sn film 14A thinner than the thickness of the Pb film 14B are sequentially stacked.
(実施形態 2 )  (Embodiment 2)
本発明の実施形態 2である半導体装置の概略構成を第 1 6図 （要部 断面図） に示す。  A schematic configuration of a semiconductor device according to the second embodiment of the present invention is shown in FIG.
第 1 6図に示すように、 半導体装置は、 実装基板 1の実装面上に半 導体べレッ ト 8及び半導体部品 2 6を実装している。 半導体ぺレッ ト 8は実装基板 1の実装面上にバンプ電極 1 4 を介在して実装されてい る。 つまり、 半導体ぺレツ ト 8は C C B方式で（ ontroled C_ollaps e B_onding ) 実装されている。  As shown in FIG. 16, in the semiconductor device, the semiconductor belt 8 and the semiconductor component 26 are mounted on the mounting surface of the mounting board 1. The semiconductor pellet 8 is mounted on the mounting surface of the mounting board 1 with the bump electrode 14 interposed therebetween. That is, the semiconductor pallet 8 is mounted in the CCB scheme (ontroled C_ollaps eB_onding).
前記実装基板 1は例えばガラス繊維にエポキシ樹脂又はポリイミ ド 樹脂を含浸させた樹脂基板で構成されている。 この場合の実装基板 1 の耐熱温度は、 2 6 0 [ °C ] X 6 0秒〜 1 2 0秒程度である。  The mounting substrate 1 is formed of, for example, a resin substrate in which glass fiber is impregnated with an epoxy resin or a polyimide resin. In this case, the heat-resistant temperature of the mounting board 1 is about 260 [° C] × 60 seconds to about 120 seconds.
前記実装基板 1の外部端子 5と半導体べレッ ト 8の外部端子 1 3 と はバンプ電極 1 4で電気的にかつ機械的に接続されている。 実装基板 1の外部端子 5、 半導体ぺレッ ト 8の外部端子 1 3の夫々は、 バンプ 電極 1 4 との高い濡れ性を確保するため、 バンプ電極 1 4の下地金属 膜 （ B L M ： B_all limiting M.etalization)と して構成されている。 外部端子 5、 外部端子 1 3の夫々は、 この構造に限定されないが、 前 述の実施例 1 と同様に、 最終保護膜に対して接着性を有する金属膜、 バンプ電極 1 4に対して濡れ性を有する金属膜、 非酸化性を有する金 属膜の夫々を順次積層した積層構造で構成される。 The external terminals 5 of the mounting board 1 and the external terminals 13 of the semiconductor bellet 8 are electrically and mechanically connected by bump electrodes 14. Each of the external terminals 5 of the mounting substrate 1 and the external terminals 13 of the semiconductor pellet 8 is provided with a base metal film (BLM: B_all limiting M) of the bump electrode 14 in order to ensure high wettability with the bump electrode 14. .etalization). Each of the external terminal 5 and the external terminal 13 is not limited to this structure. However, as in the first embodiment, the external terminal 5 and the external terminal 13 are wetted by the metal film having an adhesive property to the final protective film and the bump electrode 14. Metal film, non-oxidizing gold It has a laminated structure in which the metal films are sequentially laminated.
前記バンプ電極 1 4は、 前述の実施例 1 と同様に、 外部端子 1 3の 表面側から、 P b膜（14 B)、 この P b膜の膜厚に比べて薄い S n膜 (14 A)の夫々を順次積層した積層構造で構成されている。  The bump electrode 14 is formed of a Pb film (14B) and an Sn film (14A) thinner than the Pb film from the surface side of the external terminal 13 in the same manner as in the first embodiment. ) Are sequentially laminated.
前記実装基板 1の外部端子 25と半導体部品 2 6のリード 26 Aと は半田 2 7で電気的にかつ機械的に接続されている。 半田 2 7は例え ば 3 7 [重量。/。] P b - 63 [重量。/。] S nの組成の合金材で形成さ れている。 この合金材は、 1 8 3 [°C] 程度の融点を有する。  The external terminals 25 of the mounting board 1 and the leads 26 A of the semiconductor component 26 are electrically and mechanically connected by solder 27. Solder 27 is, for example, 3 7 [weight. /. ] Pb-63 [weight. /. ] It is formed of an alloy material having a composition of Sn. This alloy material has a melting point of about 18 3 [° C].
前記半導体ペレツ ト 8の外部端子 1 3及びバンプ電極 1 4は、 第 1 7図 （実装工程が施される前の状態を示す半導体ペレツ 卜の平面図） に示すように、 2 0 0 [ m] の配列ピッチで配置されている。 前記 実装基板 1の外部端子 5は、 図示していないが、 同様に、 2 0 0 [ m] の配列ピッチで配置されている  As shown in FIG. 17 (a plan view of the semiconductor pellet before the mounting process is performed), the external terminals 13 and the bump electrodes 14 of the semiconductor pellet 8 are 200 [m ] Are arranged at an arrangement pitch of. Although not shown, the external terminals 5 of the mounting board 1 are similarly arranged at an arrangement pitch of 200 [m].
次に、 前記半導体装置の形成方法を説明しながら、 半導体ペレッ ト 8の実装方法を説明する。  Next, a method for mounting the semiconductor pellet 8 will be described while explaining a method for forming the semiconductor device.
まず、 実装基板 1及び半導体ペレツ ト 8 を準備する。 実装基板 1の 外部端子 5の配列ピッチは、 2 0 0 m] に設定されている。 また、 実装基板 1の外部端子 2 5の表面上にはスク リーン印刷法で半田べ一 スト材 （ 3 7 [重量％] P b - 6 3 [重量％] S n ) が形成されてい る。 半導体ペレツ 卜 8の外部端子 1 3及びバンプ電極 1 4の配列ピッ チは 2 0 0 [ m] に設定されている。  First, the mounting board 1 and the semiconductor pellet 8 are prepared. The arrangement pitch of the external terminals 5 of the mounting board 1 is set to 200 m]. On the surface of the external terminal 25 of the mounting board 1, a solder paste material (37 [% by weight] Pb-63 [% by weight] Sn) is formed by a screen printing method. The arrangement pitch of the external terminals 13 and the bump electrodes 14 of the semiconductor pellet 8 is set to 200 [m].
次に、 前記実装基板 1の実装面上に半導体ペレツ ト 8及び半導体部 品 2 6を配置し、 実装基板 1の外部端子 5と半導体ぺレツ 卜 8の外部 端子 1 3 との間にバンプ電極 1 4を配置すると共に、 実装基板 1の外 部端子 2 δと半導体部品 2 6のリード 2 6 Αとの間に半田ペースト材 を配置する。 Next, the semiconductor pellet 8 and the semiconductor component 26 are arranged on the mounting surface of the mounting substrate 1, and a bump electrode is provided between the external terminal 5 of the mounting substrate 1 and the external terminal 13 of the semiconductor pellet 8. 1 4 and solder paste material between the external terminals 2 δ of the mounting board 1 and the leads 26 Α of the semiconductor component 26. Place.
次に、 熱処理を施し、 実装基板 1の外部端子 5とバンプ電極 1 4の 一端部とを電気的にかつ機械的に接続すると共に、 実装基板 1の外部 端子 2 5と半導体部品 2 6のリード 2 6 Aとを半田 2 7で電気的にか つ機械的に接続する。 熱処理は、 P b原子と S n原子とが反応して共 晶組織を形成する P b — S n共晶温度 （ 1 8 3 [ °C ] ) よりも若干高 い温度雰囲気中で行う。 この工程において、 実装基板 1の外部端子 5 とバンプ電極 1 4の一端部との間に反応層（金属間化合物層）が形成さ れるので、 実装基板 1の外部端子 5とバンプ電極 1 4の一端部とを強 固に固着することができる。 つまり、 実装基板 1の外部端子 5の表面 上にスクリーン印刷法で形成される迎え半田を使用することなく、 耐 熱温度の低い樹脂基板からなる実装基板 1 の実装面上にバンプ電極 1 4を介在して半導体べレッ ト 8を実装することができる。  Next, heat treatment is performed to electrically and mechanically connect the external terminals 5 of the mounting substrate 1 to one end of the bump electrodes 14, and to connect the external terminals 25 of the mounting substrate 1 to the leads of the semiconductor components 26. 26 A is electrically and mechanically connected with solder 27. The heat treatment is performed in an atmosphere at a temperature slightly higher than the Pb-Sn eutectic temperature (183 [° C]) at which Pb atoms and Sn atoms react to form a eutectic structure. In this step, a reaction layer (intermetallic compound layer) is formed between the external terminal 5 of the mounting substrate 1 and one end of the bump electrode 14, so that the external terminal 5 of the mounting substrate 1 and the bump electrode 14 are formed. One end can be firmly fixed. That is, the bump electrodes 14 are formed on the mounting surface of the mounting substrate 1 made of a resin substrate having a low heat resistance temperature without using a solder formed on the surface of the external terminal 5 of the mounting substrate 1 by a screen printing method. The semiconductor bellet 8 can be mounted with the interposition.
次に、 前記実装基板 1 と半導体ペレツ ト 8 との間の隙間領域に樹脂 1 5を充填することにより、 第 1 6図に示す半導体装置がほぼ完成す る。  Next, a resin 15 is filled in a gap region between the mounting board 1 and the semiconductor pellet 8 to substantially complete the semiconductor device shown in FIG.
このように、 本実施例によれば、 前述の実施形態 1 と同様の効果が 得られる。  As described above, according to the present embodiment, the same effects as those of the first embodiment can be obtained.
(実施形態 3 )  (Embodiment 3)
本発明の実施形態 3であるバンプ電極の概略構成を第 1 8図（断面 図）に示す。  FIG. 18 (sectional view) shows a schematic configuration of the bump electrode according to the third embodiment of the present invention.
第 1 8図に示すように、 基体 3 0上に複数のバンプ電極 1 4が配置 されている。 基体 3 0は、 例えば、 単結晶珪素基板からなる支持基板 3 O Aと、 この支持基板 3 0 A上に形成され、 かつバンプ電極 1 4に 対して濡れ性が悪い酸化珪素膜 3 0 Bとで構成されている。 つまり、 複数のバンプ電極 14の夫々は、 濡れ性が悪い酸化珪素膜 30 B上に 配置されている。 As shown in FIG. 18, a plurality of bump electrodes 14 are arranged on a substrate 30. The base 30 is composed of, for example, a support substrate 3 OA made of a single-crystal silicon substrate and a silicon oxide film 30 B formed on the support substrate 30 A and having poor wettability to the bump electrodes 14. It is configured. That is, Each of the plurality of bump electrodes 14 is disposed on the silicon oxide film 30B having poor wettability.
前記バンプ電極 14は、 第 1 9図（要部拡大断面図）に示すように、 酸化珪素膜 30 Bの表面側から、 S n膜 14 A、 この S n膜 14 Aの 膜厚に比べて厚い P b膜 14 B、 この P b膜 14 Bの膜厚に比べて薄 い S n膜 14 Aの夫々を順次積層した積層構造で構成されている。 つ まり、 バンプ電極 14は、 P b膜 14 Bの一表面上及びその裏面上に、 その膜厚に比べて薄い S n膜 14 Aを設けた構成になっている。  As shown in FIG. 19 (enlarged cross-sectional view of a main part), the bump electrode 14 is formed from the front side of the silicon oxide film 30B as compared with the Sn film 14A and the film thickness of the Sn film 14A. It has a stacked structure in which a thick Pb film 14B and an Sn film 14A thinner than the thickness of the Pb film 14B are sequentially stacked. That is, the bump electrode 14 has a configuration in which the Sn film 14A thinner than the film thickness is provided on one surface and the back surface of the Pb film 14B.
なお、 基体 30は、 それ自体がバンプ電極（はんだ） 14に対して濡 れの悪いセラミ ックスの様な材料で形成してもよい。 また、 基体 30 は、 支持基板 3 OAと、 バンプ電極（はんだ） 14に対して濡れ性が悪 いじ r膜のような金属膜とで構成してもよい。  The base 30 itself may be formed of a material such as ceramics having poor wettability to the bump electrode (solder) 14. Further, the base 30 may be composed of a support substrate 3 OA and a metal film such as a r film having poor wettability to the bump electrodes (solder) 14.
次に、 前記バンプ電極 14の形成方法について、 第 20図（要部断 面図）を用いて説明する。  Next, a method of forming the bump electrode 14 will be described with reference to FIG. 20 (a cross-sectional view of a main part).
まず、 基体 30を準備する。  First, the base 30 is prepared.
次に、 前記基体 30の表面上にその表面の一部を露出したマスク 3 1 を形成する。 マスク 3 1は例えばフォ トリソグラフィ技術で形成さ れたフォ トレジス卜膜で形成される。  Next, a mask 31 exposing a part of the surface is formed on the surface of the base 30. The mask 31 is formed of, for example, a photo resist film formed by a photolithography technique.
次に、 前記基体 30の表面上の全面に、 S n膜 14 A, この S n膜 14 Aの膜厚に比べて厚い P b膜 14 B、 この P b膜 14 Bの膜厚に 比べて薄い S n膜 14 Aの夫々を真空蒸着法で順次形成する。  Next, over the entire surface of the base 30, an Sn film 14 A, a Pb film 14 B thicker than the Sn film 14 A, and a Pb film 14 B thicker than the Pb film 14 B Each of the thin Sn films 14A is sequentially formed by a vacuum deposition method.
次に、 前記マスク 3 1を除去すると共に、 このマスク 3 1上の S n 膜 14 A、 P b膜 14 B、 S n膜 14 Aの夫々を除去することにより、 第 1 9図に示すバンプ電極 14が形成される。  Next, by removing the mask 31 and removing each of the Sn film 14A, the Pb film 14B, and the Sn film 14A on the mask 31, the bump shown in FIG. Electrodes 14 are formed.
次に、 前記バンプ電極 14を用いた半導体ペレッ トの実装方法につ いて、 第 2 1図乃至第 2 3図を用いて説明する。 Next, a method for mounting a semiconductor pellet using the bump electrode 14 will be described. The description will be made with reference to FIGS. 21 to 23.
まず、 第 2 1図に示すように、 実装基板 1の実装面上に基体 3 0を 配置すると共に、 実装基板 1の実装面の外部端子 5上にバンプ電極 1 4を配置する。  First, as shown in FIG. 21, the base 30 is disposed on the mounting surface of the mounting substrate 1 and the bump electrodes 14 are disposed on the external terminals 5 on the mounting surface of the mounting substrate 1.
次に、 P b— S n共晶温度（1 8 3 [ °C ] )よりも若干高い温度で熱 処理を施し、 実装基板 1の外部端子 5とバンプ電極 1 4の一端部とを 固着する。 この工程において、 バンプ電極 1 4の他端部は濡れ性が悪 い酸化珪素膜 3 0 Bと接しているので、 バンプ電極 1 4の一端部はそ の他端部に比べて強固に接着される。  Next, heat treatment is performed at a temperature slightly higher than the Pb—Sn eutectic temperature (183 [° C]) to fix the external terminals 5 of the mounting substrate 1 to one end of the bump electrodes 14. . In this step, since the other end of the bump electrode 14 is in contact with the silicon oxide film 30B having poor wettability, one end of the bump electrode 14 is more firmly adhered than the other end. You.
次に、 前記実装基板 1の主面上から基体 3 0を取り除く ことにより、 第 2 2図に示すように、 実装基板 1の外部端子 5に強固に接続された バンプ電極 1 4は基体 3 0から離脱され、 実装基板 1 に転写される。 次に、 第 2 3図に示すように、 前記実装基板 1の実装面上に半導体 ペレッ ト 8を配置すると共に、 実装基板 1の外部端子 5と半導体べレ ッ ト 8の外部端子 1 3との間にバンプ電極 1 4を配置する。  Next, by removing the substrate 30 from the main surface of the mounting substrate 1, as shown in FIG. 22, the bump electrodes 14 firmly connected to the external terminals 5 of the mounting substrate 1 And transferred to the mounting board 1. Next, as shown in FIG. 23, the semiconductor pellet 8 is arranged on the mounting surface of the mounting board 1, and the external terminals 5 of the mounting board 1 and the external terminals 13 of the semiconductor pellet 8 are connected to each other. A bump electrode 14 is arranged between them.
次に、 P b— S n共晶温度（1 8 3 C ] )よりも若干高い温度で熱 処理を施し、 実装基板 1の外部端子 5とバンプ電極 1 4の一端部とを 固着する。 この工程により、 実装基板 1の実装面上にバンプ電極 1 4 を介在して半導体ペレツ 卜 8が実装される。  Next, heat treatment is performed at a temperature slightly higher than the Pb—Sn eutectic temperature (183 C]) to fix the external terminals 5 of the mounting substrate 1 to one end of the bump electrodes 14. By this step, the semiconductor pellet 8 is mounted on the mounting surface of the mounting substrate 1 with the bump electrode 14 interposed therebetween.
このように、 バンプ電極 1 4を、 P b膜 1 4 Bの一表面上及びその 裏面上に、 その膜厚に比べて薄い S n膜 1 4 Aを設けた構成にするこ とにより、 バンプ電極 1 4の一端部及びその他端部には P b— S n界 面が存在することになるので、 実装基板 1の外部端子 5とバンプ電極 1 4の一端部とを P b— S n共晶温度 （ 1 8 3 [ °C ] ) で電気的にか つ機械的に接続することができると共に、 半導体ペレツ 卜 8の外部端 子 1 3とバンプ電極 14の他端部とを P b— S n共晶温度 （ 1 83 [°C] ) で電気的にかつ機械的に接続することができる。 In this way, by forming the bump electrode 14 on one surface of the Pb film 14B and on the back surface thereof with the Sn film 14A thinner than the film thickness, the bump electrode 14 is formed. Since the Pb—Sn interface exists at one end of the electrode 14 and the other end, the external terminal 5 of the mounting board 1 and one end of the bump electrode 14 are shared by Pb—Sn. At the crystallographic temperature (183 [° C]), it can be electrically and mechanically connected, and the external end of the semiconductor pellet 8 The element 13 and the other end of the bump electrode 14 can be electrically and mechanically connected at the Pb—Sn eutectic temperature (183 [° C]).
なお、 バンプ電極 14は、 第 24図 （要部断面図） に示すように、 基体 3 0の表面側から、 S n膜 14 C 1 と P b膜 14 C 2とからなる 多層膜 14 C、 この多層膜 14 Cの膜厚に比べて厚い P b膜 14 B、 この P b膜 14 Bの膜厚に比べて薄い S n膜 14 C 1 と P b膜 14 C 2とからなる多層膜 14 Cの夫々を順次積層した積層構造で構成して もよい。 この場合、 バンプ電極の一端部及び他端部には複数の P b— S n界面が存在することになるので、 P b— S n共晶温度 （ 1 8 3 [°C] ) によるバンプ電極 1 4の一端部（多層膜 1 4 C)、 その他端部 の夫々の溶融を確実に行うことができる。  As shown in FIG. 24 (a cross-sectional view of a main part), the bump electrode 14 is composed of a multilayer film 14 C composed of an Sn film 14 C 1 and a Pb film 14 C 2 from the surface side of the substrate 30. A multilayer film 14 composed of a Pb film 14 B thicker than the thickness of the multilayer film 14 C and a Sn film 14 C 1 and a Pb film 14 C 2 thinner than the thickness of the Pb film 14 B It is also possible to form a laminated structure in which each of C is sequentially laminated. In this case, since there are a plurality of Pb-Sn interfaces at one end and the other end of the bump electrode, the bump electrode depends on the Pb-Sn eutectic temperature (183 [° C]). It is possible to surely melt one end of the 14 (multilayer film 14 C) and the other end.
また、 前記バンプ電極 14は、 図示していないが、 基体 3 0の表面 側から、 S n膜 14 A、 この S n膜 1 4 Aの膜厚に比べて厚い P b膜 14 B , この P b膜 1 4 Bの膜厚に比べて薄い S n膜 1 4 C 1 と P b 膜 14 C 2とからなる多層膜 1 4 Cの夫々を順次積層した積層構造、 若しくは、 外部端子 1 3の表面側から、 S n膜 14 C 1 と P b膜 14 C 2とからなる多層膜 1 4 C、 この多層膜 1 4 Cの膜厚に比べて厚い P b膜 14 B、 この P b膜 14 Bの膜厚に比べて薄い S n膜 14 Aの 夫々を順次積層した積層構造で構成してもよい。  Although not shown, the bump electrodes 14 are formed from the surface side of the base 30 from the Sn film 14 A, the Pb film 14 B, and the Pb film 14 B, which are thicker than the Sn film 14 A. a multilayer structure in which a multilayer film 14 C composed of an Sn film 14 C 1 and a Pb film 14 C 2 thinner than the film thickness of the b film 14 B is sequentially laminated, or an external terminal 13 From the front side, a multilayer film 14 C composed of a Sn film 14 C 1 and a Pb film 14 C 2, a Pb film 14 B thicker than the multilayer film 14 C, and a Pb film 14 Each of the Sn films 14A, which is thinner than the film thickness of B, may be formed in a laminated structure in which each of them is sequentially laminated.
以上、 本発明者によってなされた発明を、 前記実施形態に基づき具 体的に説明したが、 本発明は、 前記実施形態に限定されるものではな く、 その要旨を逸脱しない範囲において種々変更可能であることは勿 mである。  As described above, the invention made by the inventor has been specifically described based on the above-described embodiment. However, the present invention is not limited to the above-described embodiment, and can be variously modified without departing from the gist thereof. Is of course m.

Claims

請 求 の 範 囲 The scope of the claims
1. 外部端子上にバンプ電極を有する半導体ペレツ 卜であって、 前記 バンプ電極が、 前記外部端子の表面側から、 P b膜、 この P b膜の膜 厚に比べて薄い S n膜の夫々を順次積層した積層構造で構成されてい ることを特徴とする半導体ぺレッ ト。  1. A semiconductor pellet having a bump electrode on an external terminal, wherein the bump electrode is formed of a Pb film and a Sn film thinner than the Pb film from the surface side of the external terminal. A semiconductor pellet having a laminated structure in which are sequentially laminated.
2. 外部端子上にバンプ電極を有する半導体ぺレッ トであって、 前記 バンプ電極が、 前記外部端子の表面側から、 S n膜、 この S n膜の膜 厚に比べて厚い P b膜、 この P b膜の膜厚に比べて薄い S n膜の夫々 を順次積層した積層構造で構成されていることを特徴とする半導体べ レツ 卜。  2. A semiconductor pellet having a bump electrode on an external terminal, wherein the bump electrode is a Sn film, a Pb film thicker than the film thickness of the Sn film, from a surface side of the external terminal, A semiconductor belt characterized by having a laminated structure in which Sn films each having a thickness smaller than that of the Pb film are sequentially laminated.
3. 外部端子上にバンプ電極を有する半導体ペレッ トであって、 前記 バンプ電極が、 前記外部端子の表面側から、 P b膜、 この P b膜の膜 厚に比べて薄い S n膜と P b膜とからなる多層膜の夫々を順次積層し た積層構造で構成されていることを特徴とする半導体べレッ ト。  3. A semiconductor pellet having a bump electrode on an external terminal, wherein the bump electrode is formed of a Pb film, a Sn film and a Pn film, which are thinner than the Pb film from the surface side of the external terminal. A semiconductor berlet comprising a multilayer structure in which each of a multilayer film composed of a b film is sequentially laminated.
4. 外部端子上にバンプ電極を有する半導体ペレツ 卜であって、 前記 バンプ電極が、 前記外部端子の表面側から、 S n膜と P b膜とからな る多層膜、 この多層膜の膜厚に比べて厚い P b膜、 この P b膜の膜厚 に比べて薄い S n膜と P b膜とからなる多層膜の夫々を順次積層した 積層構造で構成されていることを特徴とする半導体ペレツ ト。 4. A semiconductor pellet having a bump electrode on an external terminal, wherein the bump electrode is a multilayer film composed of an Sn film and a Pb film from the surface side of the external terminal, and the thickness of the multilayer film. A semiconductor characterized by a multilayer structure in which a Pb film thicker than the Pb film and a multilayer film composed of the Sn film and the Pb film thinner than the Pb film are sequentially stacked. Pellets.
5. 外部端子上にバンプ電極を有する半導体ぺレツ 卜であって、 前記 バンプ電極が、 前記外部端子の表面側から、 S n膜、 この S n膜の膜 厚に比べて厚い P b膜、 この P b膜に比べて薄い S n膜と P b膜とか らなる多層膜の夫々を順次積層した積層構造、 若しくは、 前記外部端 子の表面側から、 S n膜と P b膜とからなる多層膜、 この多層膜の膜 厚に比べて厚い P b膜、 この P b膜の膜厚に比べて薄い S n膜の夫々 を順次積層した積層構造で構成されていることを特徴とする半導体ぺ レツ 卜。 5. A semiconductor pellet having a bump electrode on an external terminal, wherein the bump electrode is formed of a Sn film, a Pb film thicker than the Sn film from the surface side of the external terminal, A multilayer structure in which a multilayer film composed of a Sn film and a Pb film thinner than the Pb film is sequentially laminated, or a Sn film and a Pb film from the surface side of the external terminal. A multilayer film, a Pb film thicker than the thickness of this multilayer film, and an Sn film thinner than the thickness of this Pb film, respectively Characterized by having a laminated structure in which are sequentially laminated.
6 . 前記多層膜の S n膜、 P b膜の夫々の膜厚は、 3 7 [重量％] P b— 6 3 [重量％] S n前後の組成の合金層になる膜厚に設定されて いることを特徴とする請求の範囲第 3項乃至請求の範囲第 5項のうち いずれか 1項に記載の半導体ペレツ ト。  6. The thickness of each of the Sn film and the Pb film of the multilayer film is set to a film thickness of an alloy layer having a composition around 37 [wt%] Pb—63 [wt%] Sn. The semiconductor pellet according to any one of claims 3 to 5, characterized in that:
7 . 前記 P b膜、 S n膜の夫々は蒸着法で形成されていることを特徴 とする請求の範囲第 1項乃至請求の範囲第 6項のうちいずれか 1項に 記載の半導体ペレツ 卜。  7. The semiconductor pellet according to any one of claims 1 to 6, wherein each of the Pb film and the Sn film is formed by an evaporation method. .
8 . 実装基板の実装面上にバンプ電極を介在して実装される半導体ぺ レツ 卜の実装方法であって、 請求の範囲第 1項乃至請求の範囲第 7項 のうちいずれか 1項に記載の半導体ペレツ 卜を準備する工程と、 実装 基板の実装面上に前記半導体ペレツ トを配置すると共に、 前記実装基 板の実装面の外部端子と前記半導体べレッ 卜の外部端子との間にバン プ電極を配置する工程と、 熱処理を施し、 前記実装基板の外部端子と 前記バンプ電極の先端部とを電気的にかつ機械的に接続する工程とを 備えたことを特徴とする半導体ペレツ 卜の実装方法。  8. A method for mounting a semiconductor pellet mounted on a mounting surface of a mounting substrate with a bump electrode interposed therebetween, according to any one of claims 1 to 7. Preparing the semiconductor pellet of the present invention; and arranging the semiconductor pellet on a mounting surface of a mounting board, and connecting a bump between an external terminal of the mounting surface of the mounting substrate and an external terminal of the semiconductor pellet. A semiconductor pellet comprising: a step of arranging a bump electrode; and a step of performing a heat treatment to electrically and mechanically connect an external terminal of the mounting substrate and a tip end of the bump electrode. Implementation method.
9 . P b膜の一表面上及び裏面上にその膜厚に比べて薄い S n膜を設 けた構成になっていることを特徴とするバンプ電極。 9. A bump electrode having a structure in which an Sn film thinner than the film thickness is provided on one surface and the back surface of a Pb film.
1 0 . P b膜の一表面上及び裏面上にその膜厚に比べて薄い S n膜と P b膜とからなる多層膜を設けた構成になっていることを特徴とする バンプ電極。 10. A bump electrode having a structure in which a multilayer film composed of an Sn film and a Pb film thinner than the film thickness is provided on one surface and the back surface of a Pb film.
1 1 . P b膜の一表面上にその膜厚に比べて薄い S n膜と P b膜とか ら成る多層膜、 前記 b膜の裏面上にその膜厚に比べて薄い S n膜の 夫々を設けた構成、 若しくは、 前記 P b膜の一表面上にその膜厚に比 ベて薄い S II膜、 前記 P b膜の裏面上にその膜厚に比べて薄い S n膜 と P b膜とから成る多層膜の夫々を設けた構成になっていることを特 徴とするバンプ電極。 11. Multilayer film composed of a Sn film and a Pb film thinner on one surface of the Pb film, and a Sn film thinner on the back surface of the b film, respectively. Or on one surface of the Pb film in proportion to its film thickness. It is characterized in that it has a configuration in which a multilayer film composed of an Sn film and a Pb film, which are thinner than the film thickness, is provided on the back surface of the very thin SII film and the Pb film. Bump electrode.
1 2 . 前記多層膜の P b膜、 S n膜の夫々の膜厚は、 3 7 [重量 P b - 6 3 [重量％] S n前後の組成の合金層になる膜厚に設定され ていることを特徴とする請求の範囲第 9項乃至請求の範囲第 1 1項の うちいずれか 1項に記載のバンプ電極。  12. The thickness of each of the Pb film and the Sn film of the multilayer film is set to a film thickness of an alloy layer having a composition around 37 [weight Pb−63 3 [% by weight] Sn. The bump electrode according to any one of claims 9 to 11, wherein:
1 3 . 前記 P b膜、 S n膜の夫々は、 蒸着法で形成されていることを 特徴とする請求の範囲第 9項乃至請求の範囲第 1 2項のうちいずれか 1項に記載のバンプ電極。  13. The Pb film and the Sn film are each formed by a vapor deposition method. The method according to any one of claims 9 to 12, wherein Bump electrode.
PCT/JP1996/000432 1995-07-12 1996-02-26 Semiconductor pellet, method of its packaging, and bump electrode WO1997003465A1 (en)

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JP50565997A JP3582014B2 (en) 1995-07-12 1996-02-26 Semiconductor pellet mounting method
TW085103809A TW380361B (en) 1995-07-12 1996-04-01 Semiconductor pellet and the assembly method thereof and the bump electrode

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JP2001196409A (en) * 2000-01-03 2001-07-19 Motorola Inc Semiconductor device
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