WO1997007543A1 - Single deposition layer metal dynamic random access memory - Google Patents
Single deposition layer metal dynamic random access memory Download PDFInfo
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- WO1997007543A1 WO1997007543A1 PCT/US1996/001183 US9601183W WO9707543A1 WO 1997007543 A1 WO1997007543 A1 WO 1997007543A1 US 9601183 W US9601183 W US 9601183W WO 9707543 A1 WO9707543 A1 WO 9707543A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Definitions
- the present invention pertains generally to integrated circuit memory design, and in particular to dynamic random access memory design.
- DRAM Dynamic Random Access Memory
- the present invention solves the above-mentioned needs in the art and other needs which will be understood by those skilled in the art upon reading and understanding the present specification.
- the present invention includes a memory having at least 16 megabits (2 24 bits) which is uniquely formed in which highly conductive interconnects (such as metal) are deposited in a single deposition step.
- highly conductive interconnects such as metal
- the invention is described in reference to an exemplary embodiment of a 16 megabit Dynamic Random Access Memory in which only a single deposition layer of highly conductive interconnects are deposited in a single deposition step.
- the resulting semiconductor die or chip fits within an existing industry-standard 300 mil SOJ (Small Outline J-wing), TSOP (Thin, Small Outline Package) or other industry standard packages with little or no speed loss over previous double metal deposition layered 16 megabit DRAM physical architectures.
- This is accomplished using a die orientation that allows for a fast single metal speed path, together with the novel use of a lead frame to remove a substantial portion ofthe power busing from the single deposition layer metal, allowing for a smaller speed-optimized DRAM.
- the use of a single deposition layer metal design results in lower production costs, and shorter production time for a wide variety of memory parts, including but not limited to, DRAM, SRAM, VRAM, SAM, and the like.
- Figures IA, IB and IC shows a prior art package for a TSOP (Small, Thin Outline Package) used as an industry standard plug-compatible package for a 16 megabit DRAM die;
- TSOP Small, Thin Outline Package
- Figures 2A, 2B and 2C show a prior art package for a SOJ (Small Outline J-wing) used as an industry standard plug-compatible package for a 16 megabit DRAM die;
- Figure 3 is a functional block diagram of one configuration of a SOJ (Small Outline J-wing) used as an industry standard plug-compatible package for a 16 megabit DRAM die;
- Figure 4 is a physical layout view ofthe entire die surface of a 16 megabit single deposition layer metal DRAM die
- Figure 5 is a detailed portion ofthe physical layout view ofthe 16 megabit single deposition layer metal DRAM die of Figure 4;
- Figure 6 is an even more detailed portion ofthe physical layout view ofthe 16 megabit single deposition layer metal DRAM die of Figure 5;
- Figure 7 is a detailed cross section ofthe physical layout view of the 16 megabit single deposition layer metal DRAM die of Figure 5, showing placement ofthe memory cell arrays, I/O paths, p-sense amplifiers, n-sense amplifiers and column decoder circuitry;
- Figure 8 is a block diagram ofthe lead frame used for the 16 megabit single deposition layer metal DRAM die of Figure 4;
- Figure 9 is a mechanical diagram ofthe lead frame used for the 16 megabit single deposition layer metal DRAM die of Figure 4;
- Figure 10 is a diagram showing only the power bussing architecture for the 16 megabit single deposition layer metal DRAM of Figure 4;
- Figure 1 1 is an electrical schematic diagram ofthe n-sense amplifiers, including precharge, equalization, and isolation circuitry;
- Figure 12 is an electrical schematic diagram ofthe p-sense amplifiers, including input/output circuitry.
- Figure 13 is an electrical schematic diagram of the row decoder and row driver circuitry in one embodiment of the 16 megabit single deposition layer metal DRAM of Figure 4;
- Figure 14 is a layout diagram showing a portion ofthe row decoder pitch cell area and memory cell array area with the highly conductive interconnects and the semiconductor interconnects identified;
- Figure 15 is a layout diagram showing a portion ofthe n-sense amplifier pitch cell area and memory cell array area with the highly conductive interconnects and the semiconductor interconnects identified; and Figure 16 is a detailed block diagram ofthe electrical interconnect ofthe address and data flow ofthe 16 megabit single deposition layer metal DRAM of Figure 4.
- the present invention is directed to a novel design for a memory device in which a plurality of highly conductive interconnects (such as metal) are deposited in a only single deposition step.
- the present invention is described in an exemplary embodiment as a CMOS Dynamic Random Access Memory (DRAM) memory part having at least a 16 million (2 24 ) bit storage capacity fabricated using a single deposition layer metal and having an overall die size manufactured specifically to fit in an industry standard 300 mil wide package.
- the die size is approximately 210 mils by 440 mils.
- This memory part includes an improved lead frame within the package for off-chip power distribution, an improved row decoder/driver design using isolation techniques such as grounded gate technology, a new layout for the sense amplifier design utilizing grounded gate isolation, and a new staggered design for the on pitch cell layout to enable greater density and global routing using a single deposition layer of highly conductive interconnect.
- Confining the use of highly conductive interconnect to one layer deposited in a single process step puts a severe limitation on the design ofthe memory but through the use ofthe novel physical architecture and lead frame, the present single deposition layer metal DRAM design is implemented in the same or similar area previously used to implement two or more metal layer DRAM designs.
- references to "highly conductive interconnects” shall refer to any interconnect materials having a sheet resistance of less than one ohm per square and includes metal interconnect materials.
- References to a "single deposition layer metal” shall refer to a mask- defined, highly conductive interconnect layer which is deposited in a single deposition step. Deposition techniques are methods known to those skilled in the semiconductor arts. Some examples of highly conductive interconnects include, but are not limited to, aluminum, tungsten, titanium, titanium nitride, and titanium tungsten.
- a "semiconductive interconnect” is any interconnect comprising a material having greater than 1 ohm per square sheet resistivity.
- MATERIAL SHEET RESISTANCE (ohms/squarel n+ diffusion 75 p+ diffusion 75 n- diffusion 4000 unstrapped polysilicon 200 tungsten silicide strapped polysilicon 6
- TSOP Thin, Small Outline Package
- SOJ industry standard small outline J-wing
- DRAM Dynamic Random Access Memory
- MT4C4M4B1 See page 2- 53 of the 1995 Micron DRAM Data Book published and distributed by Micron Technology, Inc., the assignee ofthe present invention, which is hereby incorporated by reference). This part is available in SOJ and TSOP package outlines having standard operating parameters and is viewed as a fungible commodity in a market for semiconductor memories. Those skilled in the art will readily recognize that a wide variety of standard 16 megabit DRAM configurations and pinouts are available within the industry, such as 2 Mb by 8 bit, 16 Mb by 1 bit, and other configurations such as are used in video RAMs.
- Figure 3 is a functional block diagram of a typical memory configuration for the single deposition layer metal 16 Mb DRAM in a 4 Mb by 4 bit configuration.
- the present invention can be configured to operate according to this functional block diagram.
- Those skilled in the art will readily recognize that different functional configurations may be implemented using the physical architecture and the single deposition layer metal technology ofthe present invention.
- the 4 Mb by 4 bit configuration of Figure 3 is illustrative only and the present invention is not so limited.
- the implementation of memory parts using the present invention allows the production of a 16 megabit single deposition layer metal DRAM which operates identically to and is plug compatible with the other 16 megabit DRAMs available in the 300 ml wide SOJ and TSOP package outlines.
- the memory shown in the functional block diagram of Figure 3 operates according to well known principles.
- the eleven address lines shown to the left of Figure 3 are clocked into the ROW ADDRESS BUFFER by the signal RAS (row address strobe) to select the row in the memory array to be read or written.
- RAS row address strobe
- the same eleven address lines are clocked into the COLUMN ADDRESS BUFFER by the signal CAS (column address strobe) to select the column in the memory array to be read or written.
- the data lines shown on the right of Figure 3 are bidirectional data ports used for both reading and writing data.
- circuitry for controlling the spare memory cell areas and the fuses used to substituted good memory cell areas for areas found to be defective after manufacture. This circuitry is used only for the repair of memory chips after manufacture but before delivery to the customer.
- the physical architecture ofthe present invention is shown in block diagram form in Figure 4.
- the overall semiconductor die 400 is approximately 210 mils wide by 440 mils long with signal bonding pads 401a, 401b, 401c, etc. shown on the longitudinal edges ofthe semiconductor die.
- the power for the semiconductor die is also available through peripheral bonding pads 405a, 405b, 405c, etc. on the longitudinal edges and also through interior bonding pads 404a, 404b, 404c, etc. found in the interior portions ofthe die.
- a portion ofthe power busing to the circuitry on the semiconductor die is performed off chip through the use of a novel lead frame in which some power distribution to the interior portions ofthe chip is accomplished through the lead frame. Power is brought to the interior regions ofthe die through the interior bonding pads 404a, 404b, 404c, etc. by wire bonding from this unique lead frame which is positioned over the top ofthe die.
- the lead frame is described more fully below.
- the 16 Mb DRAM physical architecture has the memory cells and active support circuitry divided into four quadrants, with I/O path areas 403 and 406 between the quadrants.
- Each 256 Kb cell subarray is serviced by row decoders, column decoders, and sense amplifiers which are collectively referred to as pitch cells.
- Pitch cells are the circuits linearly aligned with the memory cells in an array along row and column lines. The pitch cells are so called because the cells are said to be on the same pitch as the line of memory cells serviced by the pitch cells. The layout of these pitch cells is described below in more detail.
- Signal lines are all highly conductive interconnect lines to provide rapid distribution ofthe data into or out ofthe memory arrays.
- the digit or bit lines in the memory cell arrays are implemented in highly conductive interconnect material and the word or row lines are implemented in semiconductive material.
- the word lines in the memory cell arrays are implemented in a highly conductive interconnect material and the bit lines are implemented in semiconductive material.
- highly conductive materials may be used in the implementation ofthe present invention such as metals including titanium, aluminum, tungsten, titanium nitride, titanium tungsten, etc. deposited using vapor deposition or other known techniques. The aforementioned list of selected metal types is illustrative only and not intended to be limiting.
- the memory cell areas are subdivided into small regions. With more subdivisions of cell area, more pitch cells are required to service those cell areas. But within the global restriction of a die size remaining approximately the same size as the prior art multiple metal layer DRAM parts, the size ofthe cell areas in the present invention is reduced and the pitch cells are closely spaced and staggered to conserve space.
- Figure 5 an expanded view of a portion of memory cell area and active support circuit area of Figure 4 is shown.
- Figure 5 shows several 256 Kb subarrays 402a, 402b, 402c, 402d, etc. of memory cells from the upper left quadrant ofthe semiconductor die of Figure 4 and several 256 Kb subarrays 402e, 402f, 402g, 402h, etc. of memory cells from the lower left quadrant ofthe semiconductor die of Figure 4.
- the novel architecture shown in Figures 4 and 5 is specifically designed to minimize read and write times between the input and output (I/O) pins for accessing the memory cells in the array.
- the data line to the output bonding pad would be quite short.
- a memory cell which has a short physical connection to the input address bonding pads may have a long data path to the output data line. In this fashion, the overall access time of any one cell in the array is averaged to be 70 nanoseconds or less.
- the 256 Kb subarrays of memory cells are arranged as 512 bits by 512 bits in an array.
- the subarrays are serviced by n-sense amplifiers (NSA) 502a and p-sense amplifiers (PSA) shown in the vertical rectangles in Figure 5.
- NSA n-sense amplifiers
- PSA p-sense amplifiers
- the column address decoders (COL DECODER) for the memory subarrays are collocated with the p-sense amplifiers in the vertical rectangular areas 503a.
- Figure 7 The placement ofthe column address decoders and the p-sense amplifiers is shown in further detail in Figure 7 in which, due to the orientation of Figure 7, the n-sense amplifiers (NSA) 102, memory cell array 402b, the p-sense amplifiers (PSA) and the column address decoders 503a for the memory subarrays appear in a horizontal stack.
- the common area 503a in Figure 7 shows in more detail the location ofthe PSA area 701, the I/O path area 702, the column decoder area 703, more I/O area 704 and another PSA area 705. The specific layout of these areas is described more fully below. Referring once again to Figure 5, the row address decoders
- ROWDEC are located in the horizontal areas 501a, 504a, 505a, etc. between the memory subarrays. For the subarray in the upper half of Figure 5, the array control and output data flow toward the upper portion ofthe die and for the subarray in the lower half of Figure 5, the array control and output data flow toward the lower portion of the die.
- Figure 6 shows the subarrays further divided into 16K blocks 603a, 603b, 603c, etc. of memory cell areas arranged as 128 bits by 128 bits.
- the bit or digit lines 601 across the memory cell blocks are implemented in highly conductive interconnect material (such as metal) and connect the memory cell areas 603n to the column decoders.
- the word lines 602 across the memory cell blocks 603n are polysilicon connecting the memory cells to the row decoders.
- the data paths to and from the cell areas are connected to the peripheral signal bonding pads by routing the data paths in areas 503a toward the die periphery located toward the top left of Figure 6.
- the word lines 602 across the memory cell blocks may also be implemented using conductively strapped polysilicon to connect the memory cells to the row decoders.
- the digit lines 601 are implemented in polysilicon or conductively strapped polysilicon.
- the word lines 602 across the memory cell blocks 603n are implemented in highly conductive interconnect material to connect the memory cells to the row decoders.
- pitch cells As described above, row drivers, row decoders, column decoders. and sense amplifiers are collectively referred to as pitch cells.
- the pitch cells are so called because the cells are said to be on the same pitch as the line of memory
- V cc (power) and V ss (ground) connections to the circuitry of the die 400 require metal connections from the bonding pads to the circuits.
- the restriction of using a single deposition layer metal of interconnect and the restriction in the die size require that at least some ofthe power distribution be performed off-chip. This is accomplished by placing some power bonding pads in the interior regions ofthe die 400 and using a novel lead frame shown in block diagram form in Figure 8. The mechanical layout ofthe lead frame is shown in Figure 9.
- the power and ground pins are located along the longitudinal edges ofthe chip.
- the power is brought to the interior ofthe die by on-chip metal interconnects connecting the peripheral power bonding pads to the on-chip power buses for distribution. This required that the V cc (power) and V ss (ground) buses have their metal interconnect paths go over or under one another on the die.
- Figures 8 and 9 allows the V cc and V ss to be distributed from within the interior regions ofthe die without the need for on-chip power buses to go over or under one another.
- the lead frame shown in Figure 8 can be overlaid onto the die architecture layout of Figure 4 to show the arrangement ofthe lead frame over the power bonding pads of the die.
- dashed outline 400 indicates the location ofthe die of Figure 4 beneath the lead frame.
- the V cc (power) buses are identified with reference numbers 802a and 802b.
- the V ss (ground) buses are identified with reference numbers 803a and 803b.
- the lead frame buses 802a, 802b, 803a and 803b are insulated from touching the top ofthe die by a polyimide die coat and two insulating tape strips 801 a and 801b.
- the primary function ofthe insulating tape 801a and 801b is to provide a mechanical backing for the metal traces ofthe lead frame.
- power buses 802a, 802b for V cc and the ground buses 803a and 803b for V ss are located over the top ofthe interior portions of die 400, the buses are wire bonded to the interior bonding pads 404a, 404b, 404c, etc., to complete the power and ground distribution.
- the block diagram ofthe lead frame in Figure 8 also shows a portion of each package lead as a cross hatch metal lead 808, 809, etc. There are more bonding pads indicated on the die than pins on the package since multiple wire bonds are made from bonding pads to the leads frame for I/O signals.
- the pin out shown for Figure 8 is plug compatible with existing memory parts.
- lead frame pin 808 would correspond to pin DQ1 (in out data line number one), which is pin number 2 in the 24/26 pin SOJ and the 24/26 TSOP packages for part no. MT4C4M4B1 available from Micron Technology, Inc., the assignee ofthe present invention.
- V cc power bus 802b is a part of pin 1
- V ss ground bus 803 is a part of pin 26.
- Figure 10 shows the on-chip power bussing architecture which relies upon the off-chip power bussing ofthe lead frame to complete the power and ground distribution.
- Power and ground distribution generally requires substantially larger traces than signal interconnects.
- the lead frame provides power distribution across the die to reduce consumption ofthe highly conductive interconnect layer for power distribution.
- a lead frame design must also distribute the power over the extent ofthe die without large ohmic losses to prevent unnecessary thermal dissipation and voltage gradients across the circuits on the die.
- the power bonding pads shown in Figure 10 correspond to the power bonding pads shown and described in conjunction with Figures 8 and 4.
- bonding pads 404a and 404b are wire bonded to the power bus 802a of lead frame 800 of Figure 8 to distribute V cc to the interior areas ofthe die 400 along on-chip busses 1002a and 1002b, respectively.
- the bonding pads 404c and 404d of Figure 10 are wire bonded to ground bus 803a of lead frame 800 of Figure 8 to distribute V ss to the interior areas ofthe die 400 along on-chip busses 1004a and 1004b, respectively.
- the bonding pads 407a and 407b of Figure 10 are also wire bonded to ground bus 803a of lead frame 800 of Figure 8 to distribute V ss to the interior areas ofthe die 400 along on-chip busses 100 la and 1001b, respectively.
- Corner bonding pad 405a is wire bonded to the ground bus 803b of lead frame 800 of Figure 8 to distribute V ss to the interior areas ofthe die 400 along on-chip buss 1003a which is also connected to bonding pads 407a and 404c and busses 1001a and 1004a.
- Corner bonding pad 405d is wire bonded to the ground bus 803a of lead frame 800 of Figure 8 to also distribute V ss to the interior areas ofthe die 400 along on-chip buss 1003b which is also connected to bonding pads 407b and 404d and busses 1001 b and 1004b.
- Corner bonding pad 405b is wire bonded to the power bus 802b of lead frame 800 of Figure 8 to distribute V cc to the interior areas ofthe die 400 along on-chip buss 1005 which is also connected to bonding pad 404b and corner bonding pad 405c.
- Corner bonding pad 405c is wire bonded to the power bus 802a of lead frame 800 of Figure 8 to distribute V cc to the interior areas of the die 400 along on-chip buss 1005 which is also connected to bonding pads 404b and corner bonding pad 405b.
- Bonding pad 804 is wire bonded to power bus 802b of lead frame 800 of Figure 8 to distribute V cc to the output driver areas ofthe die 400 along on-chip bus 1007.
- Bonding pad 807 is wire bonded to power bus 802b of lead frame 800 of Figure 8 to distribute V cc to the output driver areas ofthe die 400 along on-chip bus 1008.
- Bonding pad 805 is wire bonded to power bus 803a of lead frame 800 of Figure 8 to distribute V ss to the output driver areas ofthe die 400 along on-chip bus 1006.
- Bonding pad 806 is wire bonded to power bus 803b of lead frame 800 of Figure 8 to distribute V ss to the output driver areas ofthe die 400 along on-chip bus 1009.
- the preferred embodiment to the present invention is implemented using a submicron process in a dense packing architecture using a single deposition layer metal. Interconnects to the pitch cells are shared between the single deposition layer metal and semiconductive interconnects.
- Those skilled in the art will readily recognize that several semiconductive interconnects could be inco ⁇ orated into the design.
- conductivity of semiconductive interconnects is improved by strapping the polysilicon with a refractory metal (such as tungsten or titanium) using a vapor deposition process and annealing the metal to the polysilicon. This is done as a separate step to the highly conductive interconnect deposition.
- a Salicide (self-aligned silicide) process may be used to selectively place a silicide on specific active areas.
- the n-sense amplifiers, p-sense amplifiers, and row decoders and drivers are placed on pitch with the memory cell array.
- On-pitch interconnects are a much more efficient usage of the single deposition layer metal than off pitch interconnects, since on-pitch interconnects are less likely to overlap and require semiconductive interconnects to complete a circuit.
- the pitch cells are necessarily larger in width than the memory cells so the pitch cells are staggered to enable the wider pitch cells to stay on pitch with the memory cells.
- the pitch cells are constructed to be narrow which, in the case of a row driver pitch cell, requires that the row driver transistors be especially immune to failure due to the increase voltage they are required to source.
- a novel row driver design is described below which provides staggered on-pitch layout using isolation circuits to eliminate punch through and channel leakage current effects.
- the preferred embodiment to the present invention incorporates n-sense and p-sense amplifiers for reading cells and refreshing cells.
- the block diagram shows a detailed enlargement ofthe column decoder/PSA 503a of Figure 5.
- n-sense amplifiers 502a, 502b are shared between adjacent memory cell arrays 402a and 402c, and dual p-sense amplifiers 701 and 705 service memory cell arrays 402a and 402c, respectively.
- column decoder 703 is situated between I/O paths 702 and 704.
- I/O paths 702 and 704 are the pathways for data to the data pins after proper row and column selection performing row access strobe (RAS) and column access strobe (CAS) commands to access a particular word ofthe memory.
- RAS row access strobe
- CAS column access strobe
- Figure 11 shows a schematic diagram of one configuration of an n-sense amplifier and related circuity.
- a memory cell subarray 1102 is connected to an array of n-sense amplifiers for both reading the state ofthe memory cells and refreshing each cell as it is read.
- the n-sense amplifier comprises two cross coupled n-channel enhancement mode field effect transistors Ql and Q2, a latch transistor Q3, and bias network transistors Q4, Q5, Q6, and Q7.
- Digit lines D and D* are adjacent digit line pairs which are connected to cell x 1003 and cell y 1004, respectively.
- the row decoding and column decoding hardware is designed such that any single memory access activates either D or D*, but never both at the same time.
- the present n-sense amplifier will precharge lines D and D* to intermediate voltage DVC2 (midpoint between V cc and V ss ) via transistors Q4, Q5, Q6, and Q7.
- Transistors Q4 and Q6 are switching transistors to connect the reference voltage to D and D*.
- Transistors Q5 and Q7 are long channel transistors which are used as current limiters in the event that a defective cell attempts to ground the DVC2 source. Q5 and Q7 are "on" all ofthe time.
- Cell x 1003 is connected to digit line D, therefore, after both D and D* are charged to voltage DVC2, transistor Qx will be switched on to connect capacitor Cx to D, and D* will be the reference at voltage DVC2. Since the capacitance of Cx is much less than the capacitance of D, the amount of charge on Cx will vary the voltage on D by a hundred millivolts or so. This voltage differential is sensed by cross-coupled transistor pair Ql and Q2, which are activated when Q3 is activated (during a read operation of cell Cx). Ql and Q2 will operate to drive D low if Cx is a logic zero on the read, and alternatively, will drive D* low if Cx is a logic one on the read. The p-sense amplifier discussed in the next section will be used to drive a digit line high if the cell contains a logic one, or alternatively drive the reference digit line high if the cell contains logic zero.
- n-sense amplifiers contain an equilibrate transistor, Q8, which is switched on to equilibrate the voltages ofthe digit lines before a cell capacitor is connected to one ofthe digit lines.
- the isolation circuit comprised of transistors Q9, Q10, Ql 1, and Q12 allows the n-sense amplifier to be shared between different memory cell arrays, as stated above. For example, Q9 and Q10 are switched on and Ql 1 and Q12 are switched off to allow the n-sense amplifier access to cells x and y, above. If Q9 and Q10 are switched off and Ql 1 and Q12 are switched on, then the n-sense amplifier is connected to another memory cell array, which includes cell q 1005. The sharing ofthe n-sense amplifiers is another space-saving technique which allows the present design to fit within a confined die size.
- One configuration of a p-sense amplifier 701 is shown in Figure 12.
- the digit lines communicate with I/O device pitch cells which serve as isolation for outputs to the data bus.
- Column decoder logic 1120 is used to activate the appropriate I/O device to ensure one bit is driving the data bus.
- One embodiment of a row decoder/driver circuit is shown in Figure 13. Conservation of row driver circuitry is obtained by increasing the number of columns (digit lines) driven by a single row driver circuit. The voltage necessary to drive a row is boosted on the word line to allow a full- voltage "one" to be written into the cell capacitors. However, as the number of columns per row increases, the boost voltage must also be elevated to allow faster speed as the number of columns increase. Thus the row driver pitch cells are designed to be protected from the effects of punch through and other voltage elevation effects.
- transistors Q1-Q16 of Figure 13 are enhancement mode n-channel transistors.
- the signal input denoted by “ ⁇ " (herein “PHI") is both a decode and clock signal which is used to synchronize row activations ofthe memory cell array.
- PHI goes low an entire bank of row decoders is selected.
- A1-A8 would go high and then one of A9-A16 must go high. For example, if Al goes high and A9 goes high, then row z is activated and goes high to activate the cell switches (FETs) per each memory cell of row z.
- Row driver 1206 includes an inverter circuit which inverts the PHI low to a high signal to drive the row z word line.
- Transistors 1210 and 1212 separately control each stage voltage level to ensure that lines 121 1 and 1213 are not floating, respectively. Bringing lines 121 1 and 1213 to a high level in between PHI switching ensures that Q9 does not experience indeterminate switching due to an intermediate voltages on 121 1 and 1213.
- the row transistors 1214 are closely spaced and employ short channel devices to accommodate the placement ofthe driver cells on pitch with the memory cells. Reduction in both transistor spacing and in channel length increases the possibility of punch through and the leakage current ofthe transistors. These undesirable effects are reduced using an advanced transistor isolation system and by increasing the threshold voltages ("VT"s) ofthe transistors, as described below.
- VT threshold voltages
- the proximity of row driver transistors enables placement ofthe row driver cells on pitch with the array of memory cells. This reduces necessity of using limited highly conductive interconnect real estate for off-pitch cell contacts, thereby freeing the single deposition layer metal for other interconnect purposes. Placing the row drivers on pitch also minimizes the necessity of using semiconductive interconnects, since most ofthe interconnects are non- overlapping and many can be accomplished using the single deposition layer metal. Therefore, placing the row driver cells on pitch with the memory cell array provides maximum cell array density using the available single deposition metal layer real estate with minimal semiconductive interconnects.
- Reduced channel length between the non-parasitic transistors also increases the leakage current through the channel regions of these transistors.
- the leakage current is reduced by p-doping the substrate regions under the gates ofthe n-channel transistors.
- Figure 14 is a layout diagram showing a portion ofthe row decoder pitch cell area and memory cell area with the highly conductive interconnects and the semiconductor interconnects identified according to the key in Table 2 below.
- the grounded gate over field implant 1401 is shown in the layout diagram of Figure 14 which serves to isolate drive transistors in area 1402 from adjacent transistors in area 1403 which corresponds to the drive transistors 1214 of Figure 13.
- Implant 1404 serves to protect each transistor within area 1403 from punch through to the adjacent transistor.
- Figure 15 is a layout diagram showing a portion of the n-sense amplifier pitch cell area and memory cell array area with the highly conductive interconnects and the semiconductor interconnects identified according to the key in Table 2 above.
- the memory array area is the same as that shown in
- the metal bit lines 1416 connect the cells in the memory array to the n-sense amplifier which correspond to lines D and D* in Figure 1 1.
- Grounded gate isolation is provided at 1501.
- Figure 16 is a detailed block diagram ofthe electrical interconnect ofthe address and data flow ofthe 16 megabit single deposition layer metal DRAM of Figure 4.
- the entire memory array shown in electrical schematic form in Figure 16 corresponds generally to the physical layout and architecture of Figure 4.
- address lines 1601 distribute the address signal to access a particular memory subarray, for example, subarray 402a.
- Each subarray contains 256 Kb of memory cells, as described above.
- the address lines 1601a and 1601 b are driven by line drivers 1602a and 1602b, respectively. While address distribution is done from the center ofthe die, the data paths are on the periphery ofthe die.
- the data lines from the array are selected through multiplexors 1605 and line drive circuits 1604.
- Data paths 1603a and 1603b are terminated at the line drivers connected to the data I/O pads ofthe die which are located, in the exemplary embodiment, to the left ofthe die shown in Figure 16 since the data I/O pins are all placed on that side ofthe die.
- Figure 10 By overlaying Figure 10 onto Figure 16, one can see how the highly conductive power and ground distribution buses (implemented in metal in the exemplary embodiment) do not interfere with the address and data distribution, which is also done primarily in highly conductive interconnect such as metal.
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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JP50924797A JP3790853B2 (en) | 1995-08-17 | 1996-01-26 | DRAM and manufacturing method thereof |
AU48600/96A AU4860096A (en) | 1995-08-17 | 1996-01-26 | Single deposition layer metal dynamic random access memory |
KR1019980701155A KR100279800B1 (en) | 1995-08-17 | 1996-01-26 | Single deposition layer metal dynamic random access memory |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/516,171 | 1995-08-17 | ||
US08/516,171 US6388314B1 (en) | 1995-08-17 | 1995-08-17 | Single deposition layer metal dynamic random access memory |
Publications (1)
Publication Number | Publication Date |
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WO1997007543A1 true WO1997007543A1 (en) | 1997-02-27 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/US1996/001183 WO1997007543A1 (en) | 1995-08-17 | 1996-01-26 | Single deposition layer metal dynamic random access memory |
Country Status (6)
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US (4) | US6388314B1 (en) |
JP (1) | JP3790853B2 (en) |
KR (1) | KR100279800B1 (en) |
AU (1) | AU4860096A (en) |
TW (1) | TW296477B (en) |
WO (1) | WO1997007543A1 (en) |
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AU4860096A (en) | 1997-03-12 |
US6388314B1 (en) | 2002-05-14 |
TW296477B (en) | 1997-01-21 |
US5907166A (en) | 1999-05-25 |
KR19990037676A (en) | 1999-05-25 |
JP3790853B2 (en) | 2006-06-28 |
US6274928B1 (en) | 2001-08-14 |
US6569727B1 (en) | 2003-05-27 |
JPH11501772A (en) | 1999-02-09 |
KR100279800B1 (en) | 2001-02-01 |
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