WO1997007547A1 - High density trenched dmos transistor - Google Patents
High density trenched dmos transistor Download PDFInfo
- Publication number
- WO1997007547A1 WO1997007547A1 PCT/US1996/013289 US9613289W WO9707547A1 WO 1997007547 A1 WO1997007547 A1 WO 1997007547A1 US 9613289 W US9613289 W US 9613289W WO 9707547 A1 WO9707547 A1 WO 9707547A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- body region
- region
- conductivity type
- principal surface
- transistor
- Prior art date
Links
- 210000000746 body region Anatomy 0.000 claims abstract description 68
- 239000000758 substrate Substances 0.000 claims description 23
- 238000002513 implantation Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 9
- 230000005669 field effect Effects 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 230000000873 masking effect Effects 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims 1
- 239000007943 implant Substances 0.000 abstract description 16
- 238000009792 diffusion process Methods 0.000 abstract description 11
- 210000004027 cell Anatomy 0.000 description 18
- 239000005380 borophosphosilicate glass Substances 0.000 description 10
- 239000002019 doping agent Substances 0.000 description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 7
- 230000001066 destructive effect Effects 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
Definitions
- This invention relates to transistors, and more specifically to a high density trenched DMOS transistor.
- DMOS diffused metal oxide semiconductor
- Some DMOS transistors are trenched transistors; the gate electrode is a conductive material, typically polycrystalline silicon (polysilicon) , located in a trench in the transistor substrate, where the sidewalls and bottom of the trench are insulated with silicon dioxide.
- the trenched structure increases transistor density, i.e. reduces the surface area consumed by the polysilicon gate of each transistor.
- transistors are used in low voltage applications where a transistor includes a large number (thousands) of cells. Each cell is defined by a source region diffused into the substrate and by the gate electrode trenches.
- the transistor cells each must be relatively large in surface area so that the lateral diffusion does not allow such coalescing. This increases the surface area consumed by each cell, or in other words increases the size of the transistor. As is well known, it is a primary goal of power MOSFET fabrication to minimize chip surface area. This lateral diffusion of the P+ deep body region prevents optimization of transistor density and hence wastes chip surface area.
- cell density is increased in a DMOS transistor. In some embodiments this is accomplished by providing a very narrow (in lateral dimension) P+ deep body region with little or no lateral diffusion.
- the P+ deep body region is implanted at high energy (i.e. 140 to 160 KeV) so as to drive the P+ deep body region down further into the substrate. This is approximately three times the conventional implantation energy for such a P+ deep body region.
- This deep (high energy) implantation is performed after the P body diffusion and is usually carried out at high temperature. This reduces the amount of the P+ deep body diffusion, and achieves the final desired depth of the P+ deep body region with lower subsequent temperature cycles.
- a double epitaxial layer is provided underlying the body region, with the P+ deep body P+ region not extending below the depth of the trench. Instead, the double epitaxial layer provides the desired current path away from the bottom of the trenches.
- the P+ deep body implant is high energy but is shallower in depth than in the first embodiment due to less diffusion.
- the destructive breakdown at the bottom of the trench characterized by the accompanying gate oxide rupture due to an excessive local electric field
- Figure 1 shows a cross-section of a transistor in accordance with the first embodiment of the invention using a high energy P+ deep body implant.
- Figure 2 shows a cross-section of a transistor in accordance with the second embodiment of the invention using a shallower P+ deep body implant with a double epitaxial layer.
- Figure 3 shows a third embodiment of the invention with no deep P+ body implant and with a double epitaxial layer.
- Figure 1 shows a cross-section of a transistor in the first embodiment of the invention. It is to be understood that this cross-section is drawn conventionally showing a portion of several cells of a typical transistor which may include thousands of such cells. However, a single cell transistor is also possible. Also, while the present disclosure is directed to a transistor having a negatively (N) doped substrate, a positively (P) doped body region and an N doped source region, it is to be understood that complementary devices are also possible wherein each doping type is reversed in terms of conductivity type. Also, the cross-sections shown here are not drawn to scale but are intended to be illustrative. While the various transistor doped regions shown here are conventionally delineated by lines, this is intended to be illustrative rather than representative.
- FIG. 1 therefore shows a cross-section of several cells of the transistor which includes a drain region 10 N+ doped to a resistivity of 1 to 5 milliohm*cm and of conventional thickness. Conventionally a metallized drain electrode (not shown) is formed on the bottom surface of this drain region 10 as an electrical contact thereto.
- N- doped epitaxial layer 12 (this need not be an epitaxial layer but is conventionally so formed) which has a resistivity of 0.7 to 1.0 milliohm»cm and hence a typical dopant level of 5xl0 15 to lxl0 16 /cm 3 .
- the N- doped portion of the epitaxial layer in the transistor is called a drift region.
- the epitaxial layer 12 has a total thickness typically of 8 to 12 ⁇ m.
- a P doped body region 14 is formed in the upper portion of the epitaxial layer 12.
- a typical dopant level of the body region 14 is 5xl0 15 /cm 3 .
- a P+ deep body region 16 which has a total depth from the principal surface of the semiconductor body of about 2.5 ⁇ m.
- a typical doping level of the P+ deep body region 16 is 2xl0 19 /cm 3 .
- Penetrating from the principal surface of the semiconductor body into the drift region 12 is a set of trenches. Each trench is lined with a gate oxide layer 24 which is typically 0.07 ⁇ m thick and each trench is filled with a conductive doped polysilicon gate electrode 22.
- a typical depth of each trench is 1 to 2 ⁇ m.
- the P+ deep body region 16 extends 0.5 ⁇ m below the bottom of the trench.
- P+ deep body region 16 approaches to within 2 ⁇ m of drain region 10.
- P+ deep body region 16 is formed by a high energy implant, as described below.
- N+ doped source regions 20 Formed in the upper portion of the epitaxial layer 12 are N+ doped source regions 20, having a typical depth of 0.5 ⁇ m. A typical doping level of the N+ source regions 20 is 6xl0 19 /cm 3 at the principal surface. Penetrating through the middle of each source region 20 is a trench in which is formed a conductive gate electrode 22. Also formed immediately over each P+ deep body region 16 is a P+ doped body contact region 18, to promote electrical contact between the body region 14 and the overlying source-body metallization layer 30 which also contacts the source regions 20. Insulating the upper portion of each conductive gate electrode 22 is a BPSG (boro-phosphosilicate glass) insulating layer 28.
- BPSG boro-phosphosilicate glass
- each transistor active portion is surrounded by a termination portion, typically including doped regions and sometimes a trench.
- Conventional terminations are suitable in accordance with the present invention and the termination portion hence is not portrayed herein.
- this structure using the high energy implantation to achieve the deep P+ body region 16 reduces further diffusion time to establish the final depth of region 16. That is, the high energy implantation step by itself establishes the ultimate depth of deep body region 16 and hence no additional diffusion is needed. This advantageously minimizes the lateral width (due to lateral diffusion) of each transistor cell, and hence maximizes cell surface area density.
- a t". ical width of each trench is 0.8 to 1.0 ⁇ m.
- a typical cell pitch is 6.0 ⁇ m. This is an improvement over the pitch of a prior art cell not having the high energy P+ deep body implant, which has a cell pitch of 7.5 ⁇ m.
- FIG. 2 depicts a transistor in the second embodiment of the invention. Most of the elements are the same and have similar reference numbers as in Figure 1. However, this transistor also includes a second (upper) epitaxial layer (drift region) 34 which is N-doped to a concentration of 5xl0 15 /cm 3 and has a thickness of 1.0 ⁇ m. Also, each cell of this transistor includes a shallower P+ deep body region 36 which does not extend as deep as the bottom of the trenches but instead only extends approximately 0.5 ⁇ m from the principal surface of the semiconductor body. A typical doping concentration of P+ deep body region 36 is 2xl0 19 /cm 3 . A typical depth is 2.5 ⁇ m.
- the non-destructive (avalanche) breakdown occurs between the P+ deep body region 36 and the underlying drain region 10.
- This embodiment has one advantage over that of the first embodiment in that the parasitic JFET (junction field effect transistor) extending laterally from the P+ deep body region 36 can be significantly reduced.
- the third embodiment shown in Figure 3 includes the double epitaxial layer (drift region) structure of Figure 2 but does not include a P+ deep body region. Thus this is relatively simpler to fabricate than the embodiment of Figure 2. It is believed however that the embodiment of Figure 2 is likely to perform better in typical applications than the embodiment of Figure 3, since the Figure 3 transistor may have some residual problem of oxide rupture, i.e. destructive breakdown at the bottom of the trenches, due to the higher elective field between a P+ deep body region and the drain region 10.
- An epitaxial layer 12 is then grown thereon having a resistivity of 0.7 to 1 milliohm*cm and a thickness of 6 to 11 ⁇ m.
- the second epitaxial layer 34 is more strongly doped N type and has a resistivity of 0.5 to 0.6 milliohm*cm.
- the total thickness of the epitaxial layer(s) in each of the embodiments of Figures 1, 2, and 3 is typically 1 to 2 ⁇ m.
- the principal surface of the semiconductor body including the epitaxial layer(s) then has a conventional active mask layer formed thereon and patterned.
- This active mask may be oxide or other suitable material.
- This active mask defines the active portion of the transistor and hence masks off the termination portion thereof. It is to be understood that each of the embodiments of Figures 1, 2, and 3 illustrates only the active portion, with the termination portion not being shown as being outside the drawing edges.
- a trench mask layer is then formed and patterned. Using the trench mask as a pattern, the trenches are then etched anisotropically. The trenches are then subject to a sacrificial oxide step to smooth their sidewalls and bottoms. The gate oxide layer 24 is then grown to a thickness of 0.05 to 0.07 ⁇ m. A layer of polysilicon is then formed on the principal surface of the semiconductor body and filling all the trenches.
- the polysilicon layer is then doped to achieve maximum conductivity with a N-type dopant.
- a gate mask layer (poly mask) is formed over the entire surface of the polysilicon and patterned. This gate mask is then used to etch away the polysilicon except from the trenches, while also leaving gate contact fingers on the principal surface connecting the gate electrodes in the various trenches.
- a blanket P type implant forms the P doped body region 14.
- This implant uses a dosage of IO 13 to 10 I4 /cm 2 at an energy of 50 to 60 KeV, typically using boron as a dopant for an N-channel device.
- a P+ region mask layer is formed and patterned, masking off all portions of the principal surface of the semiconductor body except where the P+ regions are to be formed. As shown, typically these P+ regions are located intermediate each adjacent pair of trenches.
- the P+ implant is performed using boron as a dopant.
- this implantation uses an energy of 140 to 160 KeV and a dosage of 5xl0 15 to lxl0 ,6 /cm 2 .
- this uses a lower implant energy of 50 to 60 KeV and a dosage of 5xl0 15 to lxl0 16 /cm 2 .
- the P+ dopant is boron.
- Figure 1 and Figure 2 represents a high energy P+ implant
- Figure 3 a low energy P+ implant
- the P+ implant forms the P+ doped body contact region 20, and in the case of Figures 1 and 2 it also at the same time forms the deep body P+ regions respectively 16 and 36.
- the P+ region mask is stripped and an N+ source region mask layer is formed and patterned to define the N+ source regions 20.
- the N+ source implant is then performed at an energy level of 80 to 100 KeV and a dosage of 5xl0 15 to 8xl0 18 /cm 2 , the dopant being arsenic.
- the N+ source mask is then stripped and a trench mask layer is formed and patterned to define the trenches.
- a layer of boro-phosphosilicate glass is conventionally deposited and doped. This layer has a thickness of 1 to 1.5 ⁇ .
- a BPSG mask layer is then formed and patterned over the BPSG layer and then the BPSG mask is used to etch the BPSG, defining BPSG regions 28 insulating the top side of each conductive gate electrode 22.
- conventional steps complete the device, i.e. stripping the BPSG mask, depositing the source-body metal layer, and masking the metal layer to define source-body contacts 30.
- a passivation layer is formed and a pad mask is formed and patterned and used to define the pad contacts through the passivation layer.
- the formation of the metal layer 30 has a corresponding step to form the contact to drain 10 (not shown) on the backside of the substrate.
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019980701176A KR100306342B1 (en) | 1995-08-21 | 1996-08-21 | High density trenched dmos transistor |
EP96928888A EP0958611A1 (en) | 1995-08-21 | 1996-08-21 | High density trenched dmos transistor |
JP09509501A JP3109837B2 (en) | 1995-08-21 | 1996-08-21 | Field effect transistor device and method of manufacturing the same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US533,814 | 1995-08-21 | ||
US08/533,814 US5689128A (en) | 1995-08-21 | 1995-08-21 | High density trenched DMOS transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1997007547A1 true WO1997007547A1 (en) | 1997-02-27 |
Family
ID=24127550
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1996/013289 WO1997007547A1 (en) | 1995-08-21 | 1996-08-21 | High density trenched dmos transistor |
Country Status (5)
Country | Link |
---|---|
US (1) | US5689128A (en) |
EP (1) | EP0958611A1 (en) |
JP (1) | JP3109837B2 (en) |
KR (1) | KR100306342B1 (en) |
WO (1) | WO1997007547A1 (en) |
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US6828195B2 (en) | 1997-11-14 | 2004-12-07 | Fairchild Semiconductor Corporation | Method of manufacturing a trench transistor having a heavy body region |
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Also Published As
Publication number | Publication date |
---|---|
EP0958611A4 (en) | 1999-11-24 |
US5689128A (en) | 1997-11-18 |
KR100306342B1 (en) | 2001-11-15 |
JP3109837B2 (en) | 2000-11-20 |
JPH11501459A (en) | 1999-02-02 |
KR19990037697A (en) | 1999-05-25 |
EP0958611A1 (en) | 1999-11-24 |
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