WO1997008707A1 - Dispositif de memoire non volatile a semi-conducteur et systeme informatique faisant appel a ce dispositif - Google Patents
Dispositif de memoire non volatile a semi-conducteur et systeme informatique faisant appel a ce dispositif Download PDFInfo
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- WO1997008707A1 WO1997008707A1 PCT/JP1996/002419 JP9602419W WO9708707A1 WO 1997008707 A1 WO1997008707 A1 WO 1997008707A1 JP 9602419 W JP9602419 W JP 9602419W WO 9708707 A1 WO9708707 A1 WO 9708707A1
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
- G11C16/3413—Circuits or methods to recover overprogrammed nonvolatile memory cells detected during program verification, usually by means of a "soft" erasing step
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
- G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
- G11C16/3409—Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
- G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
Definitions
- the present invention relates to a semiconductor non-volatile storage device including a transistor capable of electrically rewriting the value voltage, and is suitable for a case where the threshold voltage is frequently electrically rewritten. And the computer system using it, especially in the technical field which enables the stable read operation of the semiconductor non-volatile storage device driven by a single power supply voltage and the miniaturization of the device.
- Flash memory is a semiconductor non-volatile storage device with a 1-transistor Z-cell configuration that can electrically erase the stored contents all at once. Due to its configuration, flash memory occupies a small area per bit and can be highly integrated. Therefore, it has been attracting attention in recent years, and research and development on its structure and driving method are being actively carried out.
- the DIN 0 R method described in Symposium on VL SI Circuits Digest of Technical Papers pp 97 --98 1 99 3 and secondly, N 0 R described in pp 99 --1 00 1 993.
- the third method is the AND method described in pp6 1-62 1 9 94
- the fourth method is the HICR method described in International Electron Devices meeting Tech. Dig. Pp 1 9-22.
- the voltage line potential is set to the power supply voltage V cc at the time of reading, and a low voltage of about 1 V is applied to the bit line potential so that weak electrons are not extracted, and the memory cell is used in the sense amplifier circuit. Read the information of. If the state in which electrons are stored in the floating potential is defined as the erased state, the memory cell threshold voltage becomes high in the erased state, so even if the word line is selected at the time of reading, the drain current does not flow and the bit line does not flow. The potential holds a precharge potential of 1 V.
- the memory cell threshold voltage will be low in the write state, so selecting the edge line will cause current to flow.
- the bit line potential is lower than the precharge potential of 1 V.
- the bit line potential is amplified by the sense amp, and the information "0" and "1" are judged.
- the first is the AND method described in International Electron Devices meeting Tech. Dig. P 99 1 --993 1 992, and the second is the same.
- the HI CR method described in ppl 9 _ 22 1 993 has been proposed.
- the operation of raising the threshold voltage of the memory cell in the sector of each line is defined as the erasing operation.
- the AND method elimination operating voltage described in 994 applies a positive high voltage of 16 V to the selected sector, that is, the selected word line.
- the drain and source terminal voltage of the memory cell is set to 0 V of the ground voltage V ss.
- C A voltage difference occurs between the floating gate and the channel of the memory cell of the selected sector, and the electrons in the channel flow into the floating gate. Injected by the Fowler-Nordheim tunnel phenomenon, it can be erased by raising the threshold voltage of the memory cell.
- the write operation sequence shown in Fig. 29 is executed.
- the AND method write operation which is the third conventional technique, a unit write time is set for a group of memory cells (sectors) connected to a predetermined line of a memory cell array, and data is written in a batch. After that, the memory cell data is read, and if there is an insufficiently written memory cell, rewriting is performed (verify operation).
- the word line potential at the time of verification operation is the memory in the section in consideration of the spread of the write threshold voltage distribution.
- the threshold of all memory cells in the cell group is set to a value such that the value voltage does not become a negative value, for example, 1.5 V.
- Symposium on VLSI Technology Digest of Techni cal Papers pp 8 3— 8 4 1 9 9 3 is due to erratic defects, that is, the injection and emission of electrons in the floating gate through the tunnel membrane, which is an insulating membrane.
- the write operation is an operation of lowering the threshold voltage of the selected memory cell.
- the AND type is equipped with a sense latch circuit that performs rattling operation of write data for each bit line of the memory cell, and writes in sector units at once.
- a negative voltage of 19 V is applied to the control gate of the memory cell, that is, the ed wire, and the drain terminal voltage of the memory cell is set to 4 V in the selected cell and 0 in the non-selected cell according to the data of the sense latch circuit.
- V A voltage difference occurs between the floating game and the drain of the selected memory cell, and the electrons in the floating gate are drawn to the drain side by the Forler-Nordheim tunnel phenomenon. In non-selected memory cells, the voltage difference between the floating game and the drain is small, so it is possible to prevent the emission of electrons in the floating gate.
- the memory cells in the non-selected sector are weakened by the selected drain terminal voltage, and the threshold voltage drops. To prevent this, a power supply voltage V c c is applied to the non-selected word line.
- the withstand voltage of the M 0 S transistor constituting the device is the edge voltage of the erasing operation in which the potential difference is the largest among the writing and erasing operations 1 6 Must be V or higher.
- the gate insulating film of the M ⁇ S transistor is thickened to, for example, 25 nm or more to reduce the electric field strength applied to the gate oxide film, and the diffusion layer has a high withstand voltage structure, 0.4 ⁇ m. Even if the minimum machining rule of was used, the transistor length had to be, for example, 1.5 HI or more. As a result, the layer area of the MOS transistor is large. There is a problem that the chip size of the semiconductor non-volatile storage device becomes large.
- Fig. 19 shows the connection diagram of the memory cells
- Fig. 20 shows the schematic layout diagram of Fig. 1 of Japanese Patent Application Laid-Open No. 7-1 7 6 7 0 5.
- multiple unit probes are connected to the bit line. As shown in Fig.
- the common source line is formed by a diffusion layer in the direction perpendicular to the bit lines, and is parallel to the bit lines for each sub-several bit lines. It is wired in the direction using the metal wiring M l (SL) of the same layer as the bit wire.
- the read operation and the verification operation of the threshold voltage of the memory cell after rewriting are performed collectively for each sector of the memory cell group connected to the wire.
- the common source line L (SL) is formed by the diffusion layer, the memory cell current flowing through the common source line L (SL) causes the common source line L (SL) as shown in the equivalent circuit of the memory cell array in Fig. 53. ), A voltage effect occurs.
- the memory cell is effectively subjected to the substrate bias, and the threshold voltage is changed.
- the amount of fluctuation of this threshold voltage differs depending on the information pattern stored in the memory cell and the position of the memory cell.
- the Sub Source Line is also formed by a diffusion layer, but since only the current for one memory cell flows, it does not cause a memory cell gap with respect to the sector and cause voltage fluctuation.
- Figure 56 shows the threshold voltage dependence of the memory cell bit line position: the board bias has the greatest effect on the memory cell far from the source line, and the memory cell threshold is due to the board bias effect.
- the voltage goes up. It is maximized when all memory cell bits are written, that is, when the threshold voltage is low and cell current flows.
- the threshold pressure is the lowest in the write cell where only one bit of the cell adjacent to the source line is written.
- the above threshold voltage difference th is the memory cell in the sector It causes the threshold voltage variation.
- the threshold voltage difference AV t h must be reduced to stabilize the read operation. For this reason, it is necessary to form the common source line M l (SL) in Fig. 20 for every 3 bit lines, but there is a problem that the area of the memory array part increases by 3% or more.
- one object of the present invention is a semiconductor that can newly set an operation sequence in a semiconductor non-volatile storage device capable of being electrically rewritable, suppress the erratic phenomenon inside the device, and improve rewrite resistance. It is an object of the present invention to provide a non-volatile storage device and a computer system using the non-volatile storage device.
- Another object of the present invention is to reduce the maximum voltage of the erasing operation of the electrically rewritable semiconductor non-volatile storage device to the same level as the maximum operating voltage of the writing operation to reduce the chip size of the semiconductor non-volatile memory. It is to provide a device and a computer system using the device.
- Another object of the present invention is to stabilize the reading of information on a sector-by-sector basis in an electrically rewritable semiconductor non-volatile storage device, that is, to reduce threshold voltage variation, and further.
- the purpose of the present invention is to provide a semiconductor non-volatile storage device in which the area of the device is reduced.
- the semiconductor non-volatile storage device that solves the first problem of the present invention is a semiconductor non-volatile storage composed of transistors capable of electrically rewriting (erasing, writing) the threshold voltage represented by FIG. It is applied to the device, and the memory that is newly connected to the word line after the memory cells are collectively or selectively lowered the threshold voltage in the write operation (operation to lower the threshold voltage) sequence.
- Transistor non-volatile with an operation sequence that collectively verifies (verifies) the threshold voltage for each cell group and then raises the threshold voltage in response to the threshold voltage for each memory cell. It is a storage device.
- Memory cell as shown in the functional block diagram of the semiconductor non-volatile storage device in Fig. 12
- a flip-flop that latches the sense operation and write data and data during the operation to raise the threshold voltage for each bit line, and a flip-flop opening for each bit according to the threshold value state of the memory cell after verification.
- a circuit that automatically sets flip-flop data, a generic sense latch circuit, and a semiconductor non-volatile storage device that generates a voltage that returns the memory cell threshold voltage and a verified line voltage with the built-in power supply voltage circuit.
- the computer system of the present invention has at least a central processing unit and its peripheral circuits in addition to the semiconductor non-volatile storage device.
- a memory cell newly automatically connected to the word line inside the device is added to the write operation (operation of lowering the threshold voltage) sequence.
- the memory cell threshold voltage that has dropped due to the erratic phenomenon can be restored, and the threshold voltage distribution can be reduced.
- the verify word line voltage at the ground voltage (V s s) the bit debridement due to the errat ic phenomenon can be selectively selected, the value voltage is restored, and erroneous reading can be prevented.
- the threshold voltage of the memory cell after writing is set to 1.5 V, the emission of electrons in the floating gate and the verification eye operation are repeated, and the threshold voltage of all the memory cells to be written is 1.5 V or less. After that, verify (read) the potential of the selected wire with the ground potential (V ss), and select the cell whose memory cell threshold voltage is 0 V or less (depression) due to the erratic phenomenon.
- the read data is used as the data of the flip edge of the sense latch circuit, the bit line, that is, the drain voltage is selectively grounded potential (V ss), and the potential of the selected word line that has been written is 1
- the memory cell threshold voltage is selectively returned by injecting electrons into the floating gate using the Fowler-Nordhe im tunnel phenomenon over the entire channel with a high voltage of about 6 V. Since the data of the flip-off opening of the sense latch circuit connected to the memory cell that is not debris is the power supply voltage, the channel potential (power supply voltage) is used during the operation to raise the value voltage. ) And the word line do not have a sufficient electric field difference, so write It can hold the later memory cell threshold voltage of 1.5 V.
- the number of rewrites can be significantly improved by the present invention without determining the restriction on the number of rewrites in consideration of the errati c phenomenon.
- a positive high voltage is conventionally applied only to the selected word line, whereas in the present invention, the edge line voltage is used.
- a positive voltage is applied to the memory wells by distributing a negative voltage to supply the erasing operating voltage.
- the absolute value of the memory well voltage shall be about the same as or less than the word line voltage at the time of reading.
- Figure 33 shows a conceptual diagram of the memory pine of the present invention.
- the erase operation is selected and the positive voltage is applied to the word line (selected sector), and the erase is not selected and the word line voltage and memory well voltage are selected. It has sectors with different sectors (non-selected sectors), and sectors with non-selected erase and equal word line voltage and memory cell source-drain voltage (channel voltage) (completely non-selected sectors).
- a completely non-selected sector consists of a memory cell in which a negative voltage is applied to the memory wheel in the erase operation and the channel voltage and the ed wire voltage become the ground voltage, or a memory cell in which the memory voltage, the channel voltage, and the ed wire voltage are the ground voltage. ..
- the memory cell is connected by connecting a unit block in which a plurality of memory cells are connected in parallel, and the drain of the memory cell is connected to a bit line via an M ⁇ S transistor, and the source of the memory cell is It is connected to the source line via an M ⁇ S transistor. Therefore, the selected sector and the non-selected sector are the same unit block, and the other sectors that make up the block are completely non-selected sectors.
- 35 shows a schematic cross-sectional view of a memory cell of a semiconductor non-volatile storage device.
- the memory cell's fuel DP well, the above MOS transistor evening wheel, and the MOS transistor wheel that transfers the potential of the memory cell's source line and bit line are stored in the storage device. It is formed in the blocking separation layer ni so region to separate it from the substrate p_sub.
- the circuit MW that divides the memory mat without breaking the sector unit and switches the wall voltage of the memory mat. It is equipped with VC, a row decoder circuit XDCR that selects an edge line or sector, a sense latch circuit SL that performs sense operation and latch operation of write data, and also has a word line voltage Vh of the erase operation voltage, a memory voltage V mw, and a write operation voltage. It is equipped with a built-in power supply circuit VS that generates the field voltage VI, bit line voltage VI b, etc.
- the rising waveform of the erasing voltage in the erasing operation is added with a load capacitance and started up in a few seconds to a few tens of seconds to prevent a sudden electric field from being applied to the memory cell.
- the semiconductor non-volatile storage device is equipped with a mode control circuit MC in which the voltage arrival time at the rising edge of the memory voltage is equal to the voltage arrival time of the edge line voltage.
- the computer system of the present invention includes at least a central processing unit and its peripheral circuits in addition to the semiconductor non-volatile storage device.
- 12 V is applied to the selected word line via the row decoder circuit XDCR, and -4 V is applied to the memory wall via the memory circuit switching circuit MWVC to the memory cells required for the erase operation.
- the applied voltage of 16 V has been achieved. Therefore, the maximum voltage applied to the M ⁇ S transistor of the row decoder circuit XDCR is 12 V, and the withstand voltage can be reduced from the conventional 16 V to 12 V.
- the unselected word line voltage is applied to the selected memory cell by applying 9 V to the word line via the row decoder circuit XDCR and 4 V to the selected bit line according to the data of the sense latch circuit SL.
- the power supply voltage is V c c. Therefore, select 19 V and power supply voltage V cc for the MOS transistor of the row decoder circuit XDCR.
- V cc voltage of the MOS transistor of the row decoder circuit XDCR.
- a withstand voltage of 1 2.3 V is required for the MO S transistor.
- the MOS transistor constituting the apparatus of the present invention it is sufficient to secure a withstand voltage of up to 12.3 V by the above-mentioned erasing operation and writing operation, and a gate length of about 1 m can be used.
- connection force of memory cells is a unit block in which multiple memory cells are connected in parallel, a common drain is connected to the bit line via a MOS transistor, and the source of that unit is connected to the source line via a MOS transistor.
- Fig. 4 9 shows the layout of the metal wiring layer in which a plurality of unit blocks are arranged in the bit line direction to solve the third problem
- Fig. 2 is a schematic diagram of the layout of the metal wiring layer of the memory mat. Is shown.
- the common source line (Ml) in the memory mat of the memory cell array, is not arranged between the bit lines but is arranged in parallel with the word line.
- the metal wiring layer of the common source wire (M l) is formed in the manufacturing process prior to the metal wiring layer used for the bit wire.
- a common source line (M2 or higher) in the column direction (parallel to the bit line) is arranged in the same metal wiring layer as the bit line. ..
- the width of the common source line should be about 100 times thicker than the width of the bit line.
- the memory cell connection method of the present invention is at least a unit block configuration in which a plurality of memory cells are connected to a bit line via a MO S transistor, and the source for each unit block is a common source line (Ml). It is connected.
- the semiconductor non-volatile storage device of the present invention is a row decoder circuit that divides the memory mat and selects a word line, that is, a sector, without breaking the sector unit, as shown in the functional block diagram of the semiconductor non-volatile storage device in FIG. XD CR, sense operation and write data — Equipped with a sense lattice circuit SNS that performs the evening rattling operation, and further rewriting operation power It has a built-in power supply circuit VS that generates pressure.
- the size of the memory cell can be reduced by connecting the common memory cell rows of the memory cell array for each memory cell row of the unit block and not arranging the dummy memory cell row between the bit lines.
- the wiring width of the common source line is made about 100 times thicker than the bit line width, the board bias added to the same ed line, that is, the memory cell connected to the sector, becomes constant, and the threshold value is set. Voltage variation is reduced. Therefore, the reading of information on a sector-by-sector basis is stable.
- FIG. 1 is a flowchart of a write operation (an operation of lowering the memory cell threshold voltage), which is the first embodiment of the present invention.
- FIG. 2 is a flow chart diagram of the writing operation according to the second embodiment of the present invention c .
- FIG. 3 is a flow chart diagram of the writing operation according to the third embodiment of the present invention c
- FIG. 4 Is a flow chart diagram of a writing operation according to a fourth embodiment of the present invention.
- C FIG. 5 is a cross-sectional view showing a transistor of a semiconductor non-volatile memory cell.
- FIGS. 6A and 6B are cross-sectional views showing an example of voltage application in an operation of selectively lowering the threshold voltage of the transistor of the semiconductor non-volatile memory cell.
- Figures 7 A and 7 B are cross-sectional views showing an example of voltage application in the operation of selectively increasing the threshold voltage of the transistor of the semiconductor non-volatile memory cell.
- FIG. 8 is a diagram showing the data of the flip flap in the sense ratchet circuit of the operation (writing operation) of selectively lowering the memory cell threshold voltage of the present invention.
- FIG. 9 is a diagram showing flip-flop data in the sense ratchet circuit of the operation of selectively returning the value voltage to the memory cell in one operation of the present invention.
- FIG. 10 is a diagram showing flip flip data when the operation of selectively returning the memory cell threshold voltage of the present invention is selectively returned based on the flip flip data in the sense latch circuit. ..
- FIG. 11 is a diagram showing the data of the flip flap in the sense ratchet circuit of the operation of selectively lowering the memory cell threshold voltage of the present invention (writing operation).
- FIG. 12 is a functional block diagram showing the semiconductor non-volatile storage device of the present invention.
- Figure 1 3 shows the timing chart of the serial access method.
- Figures 1 4 A and 1 4 B are the output state diagrams of memory cells.
- Figure 15 is a random access timing chart.
- Figure 16 is a memory cell output phase diagram.
- Figure 17 is a circuit diagram showing a connection example (NO R) of the memory cells that make up the memory mat.
- Figure 18 is a circuit diagram showing a connection example (DINOR) of the memory cells that make up the memory pine.
- DINOR connection example
- Figure 19 is a circuit diagram showing a connection example (AND) of the memory cells that make up the memory mat.
- Figure 20 is a circuit diagram showing a connection example (HICR) of the memory cells that make up the memory cell.
- HICR connection example
- Fig. 21 is a block diagram in which the sense latch circuit of the present invention is an open bit line system for a memory pine.
- Fig. 22 is a block diagram in which the sense latch circuit of the present invention is a folded bit line system with respect to the memory circuit.
- FIG. 23 is a circuit diagram showing in detail the sense latch circuit of the present invention.
- Figure 24 is a waveform diagram showing the operation timing during the conventional operation of selectively lowering the threshold voltage (writing operation).
- FIG. 25 is a waveform diagram showing the operation timing during the operation of selectively returning the memory cell threshold voltage in one operation of the present invention.
- FIG. 26 is a waveform diagram showing the operation timing of the operation of selectively returning the memory cell threshold voltage of the present invention at the time of the selective return operation based on the data of the flip flap in the sense latch circuit.
- FIG. 27 is a waveform diagram showing the operation timing during the operation (writing operation) of selectively lowering the memory cell threshold voltage of the present invention.
- FIG. 28 is a functional block diagram showing a computer system using the semiconductor non-volatile storage device of the present invention.
- Figure 29 shows the conventional write operation (operation to lower the memory cell threshold voltage). It is a low chart diagram.
- Figure 3 shows the write state when the conventional memory cell threshold voltage lowering operation (write operation) is performed.
- Figures 3 1 A, 3 1 B, and 3 1 C are diagrams showing the writing state when the operation (writing operation) of lowering the threshold voltage of the memory cell of the present invention is performed.
- FIG. 32 is a diagram showing a voltage applied to the terminals of the memory cell of the present invention.
- FIG. 3 3 is a conceptual diagram of a memory pine of a semiconductor non-volatile storage device according to an embodiment of the present invention.
- Figures 3 4 A and 3 4 B are cross-sectional views of a transistor showing an example of voltage application in the erasing operation of a conventional semiconductor non-volatile memory cell.
- FIG. 35 is a cross-sectional view of a transistor showing a voltage application example of the selected memory cell in the erasing operation of one embodiment of the present invention.
- FIG. 37 is a functional block diagram showing the semiconductor non-volatile storage device according to the embodiment of the present invention.
- FIG. 38 is a circuit diagram showing in detail the sense latch circuit according to the embodiment of the present invention.
- FIG. 39 is a circuit diagram showing in detail a memorandum composed of AND type memory cells in one embodiment of the present invention.
- FIG. 40 is a functional block diagram for generating a voltage supplied to the memory pine by the erasing operation according to the embodiment of the present invention.
- FIG. 41 is a circuit diagram of a memory well voltage switching circuit according to an embodiment of the present invention.
- FIG. 4 2 is a circuit diagram of a row decoder circuit that selects a word line according to an embodiment of the present invention.
- Figure 4 3 is a waveform diagram showing the timing of the erasing operation of the conventional example.
- FIG. 44 is a waveform diagram showing the timing of the first erasing operation according to the embodiment of the present invention.
- FIG. 45 is a waveform diagram showing the timing of the second erasing operation according to the embodiment of the present invention.
- FIG. 46 is a waveform diagram showing the timing of the third erasing operation according to the embodiment of the present invention.
- FIG. 47 is a waveform diagram showing the timing of the fourth erasing operation according to the embodiment of the present invention.
- FIG. 48 is a diagram showing the layout of the metal wiring layer of the memory cell array mat portion of the present invention.
- FIG. 49 is a diagram showing a layout of the metal wiring layer of the memory cell array mat portion of the present invention.
- FIG. 50 is a diagram showing an outline of the layout of the conventional memory cell array section.
- FIG. 51 is a diagram showing an outline of the layout of the memory cell array portion of the present invention.
- Figure 52 is a circuit diagram showing a connection example of N AND type memory cells.
- Figure 53 shows the equivalent circuit diagram of a conventional memory cell array.
- FIG. 54 shows an equivalent circuit diagram of the memory cell array of the present invention.
- Figure 55 shows the ratio of the area of the source line to the number of bit lines between the source lines.
- Figure 56 shows the dependence of the threshold voltage on the bit line position of the memory cell.
- FIG. 57 is a functional block diagram showing the semiconductor non-volatile storage device of this embodiment.
- FIG. 58 is a circuit diagram showing in detail the sense latch circuit of this embodiment.
- FIG. 59 is a waveform diagram showing the timing of the read operation of this embodiment.
- Figure 60 is a block diagram showing an example of application to a PC card.
- the semiconductor non-volatile storage device of this embodiment is, for example, an EE PR OM composed of a plurality of memory mats composed of transistors whose values and voltages can be electrically rewritten.
- the control signal buffer circuit CSB is not particularly limited, but for example, chip enable signals and output rice supplied to external terminals ZCE, / OE, / WE, SC, etc. Bull signal, A write enable signal, serial clock signal, etc. are input, and a timing signal of an internal control signal is generated according to these signals.
- the mode control circuit MC has a ready / busy signal force from the external terminal (/ B). Has been entered.
- "/" such as CE, / OE, ZWE represents a complementary signal.
- the power supply voltage Vc is not particularly limited.
- read word line voltage V rw When c is input, read word line voltage V rw, write word line voltage Vww, write verify word line voltage Vwv, erase word line voltage V ew, erase verify line voltage V e V, read bit line Voltage V rb, Read reference bit line voltage Vr r, Write drain terminal voltage Vwd, Write transfer voltage Vw t, Low threshold verify word line voltage V lv, Select return word line voltage V pw, Select return non-selection channel ⁇ Drain voltage VP c, selective return transfer voltage Vpt, high threshold validated line voltage Vhv, reselective write word line voltage V sw, reselective write drain terminal voltage Vs d, reselective write transfer voltage V st etc. are being generated.
- each of the above voltages may be supplied from the outside.
- Each voltage generated here is read word line voltage V rw, write word line voltage Vww, write verify word line voltage Vwv, erase word line voltage Vew, erase verify line voltage V ev, write transfer.
- Voltage Vw t Low threshold validated line voltage V 1 v, Selective return word line voltage Vpw, Selective return transfer voltage Vp t, High threshold verify voltage Vh v, Reselective write ⁇ Line voltage V sw, Reselective write transfer voltage V s 1 line address decoder XDCR, read bit line voltage Vrb, read reference bit line voltage Vr r, write drain terminal voltage Vwd, Selective return non-selective channel ⁇ Drain voltage Vp c, Reselective write drain terminal voltage V sd, Write transfer voltage Vwt, Selective return voltage target voltage Vp t, Reselective write transfer voltage Vs t are sense latch circuits SL Is entered in each.
- the power supply voltage may be shared.
- erase word line voltage V ew and select return word line voltage V p w write word line voltage V ww and reselect.
- Selective write voltage V sw, write drain terminal voltage V wd and reselective write drain terminal voltage V s d, write transfer voltage V wt and reselective write transfer voltage V s t can be shared voltages.
- the row supplied from the external terminal, the row receiving the column address signal AX and AY, the complementary address signal formed through the column address buffer XADB and YADB are the row, and the column address decoder XDCR. , Supplied to YDCR.
- the above row and column address buffers XADB and YADB are activated by the chip enable selection signal ZCE inside the device and capture the address signals AX and AY from the external terminals. It forms a complementary adapter signal consisting of an internal adapter signal that is in phase with the adapter signal supplied from the outer endpoint and an adapter signal that is out of phase.
- the row address decoder XDCR forms the selection signal of the edge line W of the memory cells according to the complementary address signal of the row address buffer XADB, and the column address recorder YDCR becomes the complementary address signal of the column address buffer YADB. Therefore, the selection signal of the bit line B of the memory cell group is formed. As a result, in the memory mat Memory Mat, arbitrary word line W and bit line B are specified and a desired memory cell is selected.
- the memory cell selection is 8 bits or 16 bits, and the memory cell is 8 by the row address decoder XDCR and the column address decoder YDCR to write and read.
- One or sixteen are selected. Assuming that there are m memory cells in the yard line direction (row direction) and n memory cells in the bit line direction (column direction), there are mx n memory cell group memory cells. It consists of 8 or 16 pieces.
- the serial access method for the memory cell and the random access method are used.
- the case of use will be described with reference to FIGS. 13 to 16.
- a particularly large effect can be expected by providing a sense latch circuit that latches temporary data at the time of output and adopting a serial access method.
- the timing chart is as shown in Fig. 13 and the data is output as shown in Fig. 14 A and 14 B, which outline a part of the memory matrix.
- the chip enable signal ZCE, the output enable signal ZOE, and the light enable signal / WE are activated and the address signal Address is input after the data input command Din is input, it synchronizes with the serial clock signal SC. Then, the input signal is sequentially incremented or decremented, and for example, 5 1 2 bit data data from 0 bit to 5 1 1 bit is output sequentially.
- one word line WL i is specified as shown in Fig. 14 A, and then the data line DL j is specified in order.
- the memory cells connected to the line BL j are sequentially selected and data is taken into the sense latch circuit. Then, the data captured in this sense latch circuit is sequentially output through the main amplifier as shown in Fig. 14B.
- the time twsc from the input of the address signal Address to the output of the first data can be 1 is, and the time tscc at which one data is output can be 5 Ons, which enables fast reading of data. It will be possible.
- the timing chart is as shown in Fig. 15, and the data is output as shown in Fig. 16 which shows a partial outline of the memory matrix. That is, when the first address signal Address is input, one word line WL i and one bit line BL j are specified in the memory matrix Memory Matrix, and this one line WL i and one bit line BL j are specified. The memory cell connected to j is selected. Then, the data of the selected memory cell is output through the sense amplifier. Similarly, for the next address signal Address, the memory cell selected by the ed line WL i and the bit line BL j can be output after a time tacc from the input of this address signal Address. can.
- the above memory cell is not particularly limited, but has a configuration similar to that of an EPROM memory cell, for example, a known memory cell having a control gate and a floating gate, or a control gate and a floating gate, and a selection gate. It is a known memory cell having.
- the structure of a memory cell having a control gate and a floating gate Will be explained with reference to Fig. 5.
- this non-volatile memory cell is, for example, a flash memory memory cell published in 1987 at the International Electron Devices Meeting Tech. Dig. Pp. 5 6 0 --56 3. It has the same structure as a transistor.
- This memory cell is not particularly limited, but is formed on a semiconductor substrate made of, for example, single crystal P-type silicon.
- this non-volatile memory cell has a control gate electrode 1, a drain electrode 2, a source electrode 3, a floating gate 4, an eyebrow insulation film 5, a tunnel insulation film 6, a P-type substrate 7, and a drain'source.
- Two flash-erasable EE P ROM cells are configured.
- connection examples have been proposed for a group of memory cells that connect multiple of these memory cells, and are not particularly limited.
- NOR type and DI as shown in Fig. 17 to Fig. 20.
- NOR type, AND type, HI CR type, etc. which will be explained in order below.
- Figure 17 shows an example in which memory cells are connected by NOR type.
- Word lines W 1,..., Wm and bit lines B 1,..., Bn, and Source Line are connected to the MO S transistor of the memory cell. Are connected, and rewriting (writing, erasing) operation or reading operation is performed through these. That is, the word lines W1 and Wm are connected to the gate of the MOS transistor, the bit lines B1,..., and Bn are connected to the drain of the MOS transistor, and the source line is connected to the source of the MOS transistor.
- Figure 18 shows an example of connecting memory cells using the DI NOR type. Select Gate and Sub Bit Line are added, and the source of the MOS transistor of Select Gate is connected to bit lines B 1,..., Bn, and this MO The drain of the S transistor is connected to the drain of the MOS transistor of each memory cell through the Sub Bit Line.
- Figure 19 shows an example of AND type connection, which has Select Gate 1 and Select Gate 2, and also Sub Source Line, and is a MOS transistor of Select Gate 1.
- the bus is connected to the bit lines Bl,..., Bn, and the drain of this MOS transistor is connected to the drain of the MOS transistor of each memory cell through the Sub Bit Line.
- the source of the MOS transistor of Select Gate 2 is connected to the Source Line, and the drain of this MOS transistor is connected to the source of the MO S transistor of each memory cell through the Sub Source Line.
- Figure 20 shows an example of HI CR type memory cell connection.
- the source of the MOS transistor of Select Gate 1 is connected to the bit lines B 1, ..., Bn, and the drain of this MOS transistor is connected through the Sub Bit Line. It is connected to the drain of the MOS transistor of the memory cell.
- the source of the MOS transistor of Select Gate 2 is connected to the Source Line, and the drain of this MOS transistor is connected to the source of the MOS transistor of each memory cell through the Sub Source Line.
- Figures 6A and 6B show the operation of selectively lowering the threshold voltage of the memory cell.
- Fig. 6 A and Fig. 6 B are memory cells in which each control device is connected to a common ed wire, and the terminal applied voltage in Fig. 6 A is when the threshold voltage of the memory cell is lowered.
- the terminal applied voltage in Fig. 6B is shown, and the terminal applied voltage in Fig. 6B shows the terminal applied voltage when holding the threshold voltage of the memory cell.
- a negative voltage of, for example, about 10 V is applied to the word line to which the control game of Fig. 6 A and Fig. 6 B is connected in common, and for example, 5 is selectively applied to the drain terminal of the memory cell of Fig. 6 A.
- the voltage of the non-selected word line is a positive voltage to prevent the discharge (electron discharge) due to the drain voltage. It has been applied. Therefore, in the rewriting operation, the source electrode is opened to prevent the constant current from flowing.
- Figures 7 A and 7 B show the operation of selectively increasing the threshold voltage of the memory cell.
- Fig. 7 A and Fig. 7 B are memory cells in which each control gate is connected to a common word line, and the terminal applied voltage in Fig. 7 A is the terminal for raising the threshold voltage of the memory cell. The applied voltage is shown, and the terminal applied voltage in Fig. 7B shows the terminal applied voltage when holding the threshold voltage of the memory cell.
- a high voltage of, for example, about 16 V is applied to the word line to which the control devices of Fig. 7 A and Fig. 7 B are connected in common, and for example, 0 V is selectively applied to the drain terminal of the memory cell of Fig. 7 A.
- control gate that is, the word line voltage
- drain voltage that is, the channel voltage
- the threshold voltage of the memory cell is selectively rewritten by selectively controlling the voltage value applied to the drain terminal of the memory cell. Be done.
- To selectively control the voltage value applied to the drain terminal of the memory cell connect a sense latch circuit having a flip-edge opening for each bit wire to which the drain terminal of the memory cell is connected, as described later.
- the sense latch circuit may have data related to the voltage information of the drain terminal.
- FIGS. 21 and 22 The outline of the connection between the memory mat Memory Mat of this embodiment and the sense latch circuit SL will be described with reference to FIGS. 21 and 22.
- one sense latch circuit SL is provided for each bit line B 1 to B n.
- the sense latch circuits SL 1 to SL n are used as memory mats.
- Memory Mat a, b bit lines B a 1 to B an, B b 1 to B b n are arranged by the open bit line method, and bit lines B 1 to B n as shown in Fig. 22 It is arranged by the folded bit wire method provided by the two sense latch circuits SL on the two lines.
- Figure 2 3 shows the circuit diagram of the sense latch circuit SL when the connection between the memory mat Memory Mat and the sense latch circuit SL is arranged by the open bit wire method shown in Fig. 21.
- the sense latch circuit SL including the flip-flop is connected to the bit lines Ban and Bbn, and the bit lines Ban and Ban, Bbn-1 are connected. It has the same (equivalent) connection configuration for Bbn. Furthermore, the sense latch circuit SL divides the control signal for the even Z odd number of the bit line, and has the same (equivalent) connection configuration for the bit line Ban-1 and B bn. .. This is to prevent the influence of the parasitic line capacitance of the bit line on the sense operation. For example, during the sense operation of the memory cell connected to the even bit line side (hereinafter referred to as the even side). Reads the memory cell on the even side with the potential on the odd bit line side (hereinafter referred to as the odd side) as V ss and the capacitance between parasitic lines at a constant value.
- the bit line B a 1 of the memory transistor Memory Mat a is input to the gate signal BD eu that displays the potential of the bit line to the ground voltage V s s.
- the MOS transistor M 2 that inputs the get signal RC eu that precharges the potential of the bit line, and the MOS transistor M 4 that uses the flip flop information as the gate input signal.
- the MOS transistor M3 whose gate is the voltage signal PC eu is connected.
- the connection between M 3 and M 4 is not limited, and the power supply voltage V cc side may be M 3 and the bit line side may be M 4.
- a MOS transistor M5 that inputs the game signal TRe u is connected between the bit wire B a 1 and the flip-flip side wiring B a 1 f.
- the flip-flop side wiring B a 1 f has a MOS transistor M 6 that inputs the gate signal RS L eu that displays the potential of the flip-flop to the ground voltage V ss, and a column gate according to the column address. It is connected to a MOS transistor M7 that receives a voltage signal Y add and outputs flip-flop information as data, and a MOS transistor M8 that uses a get input signal as flip-flop information.
- the drain of the MOS transistor M 8 is a shared signal AL eu, the source is a ground voltage V ss, and a multi-stage input NOR circuit connection is established. That is, all connected flip flocs It is a MO S transistor that determines that the information of the device is the ground voltage V s s.
- the basic configuration of the semiconductor non-volatile storage device of this embodiment has been described above.
- the operation of lowering the threshold voltage (writing operation) which is a feature of this embodiment, is the operation of FIGS. 1 to 4. It will be described by a sequence.
- Figure 1 shows the operation sequence of the first embodiment of this embodiment.
- the B sequence that is, the memory cell data is read, and the memory cell is overwritten by a predetermined level or higher (hereinafter, low).
- a low-threshold verification operation is performed to check if there is a memory cell with a threshold value, and an operation to selectively return the threshold voltage of a memory cell with a low threshold voltage (selective return operation) has been added.
- FIG. 3 1 A details the B sequence.
- the edge line potential during low threshold verification operation should be set to a voltage that does not cause the threshold voltage of the memory cell to become a negative value, for example, the ground voltage V s s. If you select an edge wire connected to a low-threshold memory cell whose threshold voltage is V s s or less, current will flow, so you can check the existence of the low-threshold memory cell. If a low-threshold memory cell exists, set the unit return time and the threshold voltage of the low-threshold memory cell due to the full-channel Fowler-Nordhe im tunnel phenomenon shown in Fig. 7. Is selectively returned to the threshold value of V ss or higher in one operation.
- Figure 2 shows the operation sequence of the second embodiment of this embodiment.
- the selection / return operation is performed by one operation
- the low-threshold verification operation and the selection / return operation are performed in a plurality of times. Perform after the sequence.
- a memory cell whose threshold voltage has returned while repeating the C sequence that is, a memory cell that is no longer at a low threshold, is excluded from the operation target of the C sequence, and an unnecessary reselection operation is performed. It is set so that it will not be damaged.
- the edge line voltage at the time of low threshold verification performed first in the C sequence and the edge line voltage at the time of low threshold verification repeated after the second time do not have to match.
- the word line voltage is set to the ground voltage VSS, the depressing memory cell is determined as in the B sequence described above, the unit return time is set, and the threshold voltage of the low threshold memory cell is set to once.
- the threshold voltage of the memory cell may be returned to 0.5 V or higher.
- Figure 3 shows the operation sequence of the third embodiment of this embodiment.
- the third embodiment after performing the low-threshold verification operation and the reselection operation, it is confirmed whether or not there is a memory cell whose write has not reached a predetermined level (hereinafter referred to as a high-threshold memory cell).
- Performs a high-threshold verification operation and if there is a high-threshold memory cell, performs a selective write operation of the threshold voltage (hereinafter referred to as reselective write) for that memory cell. Since the threshold voltage is lowered between the reselective write operation and the reselective write operation, the redata input verification operation is required. This is to distinguish between those that maintain the threshold voltage and those that have a slight fluctuation in the threshold voltage.
- the read data is latched on the flip-flop by applying a voltage of about 2 V, for example, to the edge line voltage of the re-data input verification.
- a voltage of about 2 V for example, to the edge line voltage of the re-data input verification.
- the memory cell to be reselectively written is determined according to the written data and the result of the high threshold verification operation. For example, apply a voltage of about 1.5 V to the line voltage during high threshold verification operation to reduce the threshold voltage of the cell to be written to 1.5 V or less.
- the reselective write operation can be realized by the same sequence as the write operation.
- the threshold voltage level in the write state can be kept between the threshold voltage 0.5 V at the low threshold level and the threshold voltage 1.5 V at the high threshold level. can.
- Figure 4 shows the operation sequence of the fourth embodiment of this embodiment.
- the operation sequence of the fourth embodiment is a C sequence and a D sequence, that is, an operation sequence in which the selection return operation and the reselection writing operation are repeated a predetermined number of times.
- FIG. 8 shows the data of the flip waveform in the sense ratchet circuit SL when performing the A, B, and CD sequences shown in FIGS. 1 to 4 of this embodiment, respectively.
- the timing waveform diagram of the internal signal in the sense latch circuit SL of Fig. 2 3 when performing the A, B, C, D sequence is shown in Fig. 24, Fig. 25, Fig. 26, and Fig. 27. ..
- the flip flop data "1" is defined as the state where the threshold voltage of the memory cell is low (write state), and the flip flop data is, for example, the external power supply voltage V cc, which is internal during rewriting operation.
- the timing waveform diagrams in Figures 2 4 to 27 are waveform diagrams in which the memory cell group (sector) on the Memory Mat a side is selected (on the target Memory Mat Memory Mat side), and the solid line waveforms are shown in Figure 2 3
- the waveform of the control signal with the subscript u in, and the waveform of the broken line is the waveform diagram of the control signal with the subscript d in Fig. 19
- the writing operation sequence (A sequence) is shown in Fig. 8. explain.
- a memory that sets the flip-flop in the sense latch circuit connected to the memory cell that holds the high threshold state (erased state) via a bit wire to "0" and rewrites it to the low threshold state (write).
- Figure 24 shows the timing waveform diagram of the internal signal in the sense latch circuit SL during the write operation sequence (A sequence).
- the write data input up to t 1 is the flip flop connected to the bit lines B 1,..., Bn corresponding to the memory cell for which the threshold voltage of the memory cell is to be selectively lowered. Let the data be at a high level and the data for which you do not want to lower the threshold voltage be the ground voltage V ss.
- the flip flip data is selectively transmitted to the bit lines B 1,..., Bn.
- TR eu and TRo u are selected between t 2 and t 4 to supply the write drain voltage.
- the potentials of TRe u, TRo u and SG 1 aZb are set to 6 V in order to transfer the drain voltage of 5 V ( ⁇ 3?
- TR eu, TRo u and SG 1 a Zb take into account the threshold voltage of M ⁇ S transit of Select Gate 1 on the drain side of the gate signal SG 1 a / b. Set the voltage level. Select SG 1 a Zb after lowering the potential of the selection edge voltage W a (t 2) (t 3) The delay time of the word line is larger than that of Select Gate 1 on the drain side. Because. The net write time is between t 3 and t 4, and by setting the word line to a negative voltage of 10 V and selectively setting the bit line voltage to 5 V, the desired memory cell floats.
- the PC eu is used to selectively switch the bit line based on the flip-flop data and to supply the reference potential to the bit line of the non-selective memory mat.
- RC ed are selected.
- the precharge potential is 1.0V
- the PC eu potential is 2.0V
- R 6 The potential of 3 is 1.5 V.
- the internal power supply voltages VS P e / o and VSN eZo are activated to retain the flip flip data. From t 5 to t 10 0, the selected volt potential is 1.5 V of the verify voltage.
- the discharge time of the memory cell during even-side verification is from the selection of the gate signal SG 2 a of the source side Select Gate 2 of t 6 to the inactivity of the gate signal SG I a of the drain side Select Gate 1 of t 7.
- the flip-flop on the even side is reset by the activity of the RS Leu / d signal.
- the verify eye operation on the odd side is performed between t 9 and t 10 in the same manner as the verification on the even side.
- the end of all bits of the memory cell threshold voltage is judged between T l 1 and t 1 3.
- the data on the flop is the ground voltage V s s, and this V s s is determined.
- After activating AL eu and AL ou (between t 1 1 and t 1 2), verify the potential, and if the ground voltage Vs s, repeat to t 1 to continue the writing operation. If ALe u and AL 0 u are at High level, the write operation is terminated.
- Figure 9 shows the flip-flop data in the sense latch circuit during the B sequence.
- Conventional write operation (A sequence) After completion, perform the above-mentioned low-threshold verification operation for all memory cells connected to the line to be written.
- the word line voltage during low threshold verification operation is, for example, the contact voltage V s s, and pre-charging is performed for all bits.
- bit (depression bit) where the threshold voltage is lower than the verify line voltage, the cell current flows and the flip-flop data becomes "0".
- the precharge voltage is maintained and becomes "1".
- the data of the flap flop is judged, and if all the data is "1", the operation is terminated, and even 1 bit is "0", that is, it is higher than the word line voltage at the time of low threshold verification. If the value voltage is low and a bit (depression bit) is present, the selection return operation is performed.
- the potential of the word line to be written is set to a high voltage such as 16V
- the channel of the memory cell selected by the flip-flop data is set to the ground voltage V ss
- the channel of the non-selected memory cell is the drain voltage Vp.
- c for example 8 V, performs the selection / return operation.
- Figure 25 shows the timing waveform of the internal signal in the sense latch circuit SL during the B sequence. Whether or not to perform the low threshold value verification operation on the even side between t 1 force and t 3 and the odd side between t 3 and t 4 and the selection return operation between t 4 and t 5. Is judged, and the selection return operation is performed between t 6 and t 9.
- RC eu has a potential of 2.0 ⁇ ⁇ ⁇ ⁇ ⁇ 601 and the potential of 601 is set to 1.5 V.
- the selection return operation first, PC eu and PC ou are activated between t 5 and t 6 to transmit the flip flop data to the bit line. After that, the same as the write operation By activating the signal line in this way, the selection return operation can be executed.
- the word line voltage Vpw during selective return operation applies a high voltage of, for example, 16 V
- the flip-flop power supply voltage VSP e Z 0 is the non-selective channel / drain voltage V pc during selective return operation, for example.
- the voltage is 8 V
- the potentials of the MOS transition gate signals TR u / d, TRO uZd, and SG 1 uZ d that transfer the drain voltage are the transfer voltage Vpt at the time of selection return, for example, 9 V.
- Figure 10 shows the data of the flip-flop in the sense latch circuit during the C sequence.
- the low threshold voltage of the memory cell connected to the wire to be written is verified in the same manner as in Fig. 9, and the threshold voltage is low. If (depression bit) exists, the selection / reselection operation is performed. After that, the low threshold voltage verification operation is performed again at the voltage at which the threshold voltage is desired to be returned. For example, if the low threshold voltage line voltage is 0.5 V, the threshold voltage of the memory cell can be 0.5 V or higher. The case where the voltage of the selected word line is 0.5V is described in the low threshold verification performed again. First, precharge all selections on the bit line side.
- the flip-flop data holds "0".
- the cell current does not flow and becomes a Pass, and the potential of the bit line keeps the precharged voltage and is rewritten to "1" in the flip flop data.
- the flip-flop data after verification is used as the data for reselection return, and the selection return and low threshold verification operation are repeated. The operation ends when all the days of the flip-off mouth-up become "1". This batch judgment is automatically performed in the chip.
- Figure 26 shows the timing waveform of the internal signal in the sense latch circuit SL during the C sequence.
- the voltage of RC eu is 2.0 V, RC to supply the precharge potential to all selected bit lines and the reference potential to the bit lines of the non-selected side memorial pine.
- the voltage of ed is 1.5 V.
- the discharge time of the memory cell at the time of verifying even side is from the selection of the gate signal SG 2 a of the source side Select Gate 2 of t 3 to the non-gate signal SG 1 a of the drain side Select Gate 1 of t 4. Up to activity.
- the verification operation on the odd side is performed between t 8 and t 9 in the same manner as the verification on the even side. After that, it is judged whether or not the threshold voltage of the memory cell returns to the predetermined voltage or more during t 9 force and t 10 0. If the threshold and value voltage of all memory cells are returned, the flip-flop data will be the potential (High level) of the power supply voltage VS PeZo, so the memory cell threshold value will be based on the flip-flop data. The voltage can be judged. Verification of flip-flop data is performed by activating AL e d and AL o d on the non-selected side.
- the selection return operation from t 10 is performed, and as a result, the operation ends when the flip flop data reaches the high level.
- the selection return operation is performed in the same manner as in Fig. 21. After t 1 1 when the selection return operation is completed, the process returns to t 2 and the operation sequence is continued.
- Figure 1 1 shows the flip-flop data in the D sequence. Apply a voltage of about 2 V to the edge wire voltage of the re-data input verifi, for example, to rattle the write data to the flip-flop, and set the edge line voltage at the time of high threshold verifi to about 1.5 V, for example. Apply voltage to the threshold of the memory cell to be written Set the voltage to 1.5 V or less.
- the flip-flop data for the reselective write operation is similar to the flip-cap data for the write described in Figure 8.
- Figure 2.7 shows the timing waveform of the internal signal in the sense ratchet circuit SL during the D sequence. The timing waveform diagram for operating the circuit SL is shown.
- Figure 32 shows the voltage applied to the memory cell terminals during execution of the A, B, C, and D sequences, as well as during read, erase, and erase verification.
- the semiconductor non-volatile storage device of this embodiment has been described when it is applied to a flash memory (EEPROM), but the present invention is not limited to the above embodiment, and electricity such as EEPROM and EPROM. It is also widely applicable to other non-volatile storage devices that can be rewritten.
- EEPROM flash memory
- the semiconductor non-volatile storage device of this embodiment not only when it is used as a flash memory in a storage device unit, but also for storage of various systems such as a computer system, a digital still camera system, and an automobile system. It is widely used as a device, and as an example, a computer system will be described with reference to Fig. 24.
- this computer system is a memory control unit that accesses a central processing unit CPU as an information device, an IZO bus built in the information processing system, a Bus Unit, and high-speed memory such as main memory and extended memory.
- Computer Control Unit DR AM as main memory, ROM containing basic control programs, keyboard controller KBDC with a keyboard connected to the tip, etc.
- the Display Adapter as a display adapter is I-No 0. It is connected to the bus, and the display is strongly connected to the tip of the Display Adapter.
- the above I / O bus has a parallel port Parallel Port IF, a serial port Serial Port I / F such as a mouse, a floppy disk drive FDD, and a buffer controller HDD Buffer that converts to an HDD I / F from the above I / O bus. Be connected. In addition, it is connected to the bus from the above-mentioned memory control unit Me operation control unit, and is connected to the extended RAM and the DRAM as the main storage memory.
- the central processing unit C PU When the power is turned on and the operation is started, the central processing unit C PU first accesses the ROM through the IZO bus to perform initial diagnosis and initial setting. Then, the system program is loaded from the auxiliary storage device into the DRAM as the main storage memory. In addition, the CPU of the central processing unit described above operates as if accessing the HDD to the HDD controller through the above 1 bus.
- the processing proceeds according to the processing request of the user.
- the user proceeds with the work while inputting / outputting the processing by the keyboard controller KBDC on the above I-No. 0 bus and the display adapter Display Adapter. Then, if necessary, use the input / output device connected to the parallel port Parallel Port 1 F and the serial port Serial Port I ZF.
- the extended RAM supplements the main memory.
- the user wants to read / write a file, the user requests access to the auxiliary storage device assuming that the HDD is the auxiliary storage device. Then, the flash file system configured by the flash memory of the present invention receives the flash file system and accesses the file data.
- the semiconductor non-volatile storage device such as the flash memory of the embodiment can be widely applied as a flash file system of a computer system or the like.
- FIG. 33 is a schematic diagram of a memory pine showing the concept of an embodiment of the present invention
- FIGS. 34 A, 3 4 B is a cross-sectional view showing a transistor of a semiconductor non-volatile memory cell, which is a conventional example, and a diagram showing a voltage application example in an erasing operation.
- FIG. 37 is a functional block diagram which shows the semiconductor non-volatile storage device of this invention
- FIG. 38 is a sense latch circuit of this invention.
- the circuit diagram shown, Fig. 39 is a circuit diagram showing the memory mat of the present invention
- FIG 40 is a functional block diagram for generating the voltage supplied to the memory mat
- Fig. 4 1 and Fig. 42 are memory well voltage switching circuits.
- FIGS. 4 3 to 4 7 are waveform diagrams showing the timing of the erasing operation
- Fig. 48 is a functional block diagram showing the computer system using the semi-conductor non-volatile storage device of this embodiment. be.
- the semiconductor non-volatile storage device of this embodiment is, for example, a flash memory composed of a plurality of memory mats composed of transistors capable of electrically rewriting the value voltage, and is used for switching between the memory mat and the memory mat well voltage.
- Circuit MWV C row address buffer circuit XADB, row address decoder circuit XDCR, sense amplifier and data latch shared sense transistor circuit SL and column gateway circuit YG, column address buffer circuit YADB, column address data circuit YDCR, input It consists of a buffer circuit DIB, an output buffer circuit DOB, a multiplexer circuit MP, a mode control circuit MC, a control signal buffer circuit CSB, and a built-in power supply circuit VS.
- one sense latch circuit SL is provided for each bit line B 1 force and B n.
- Fig. 38 and Fig. 39 are shown.
- the sense latch circuits SL 1 to SL n are arranged in the open bit line system with respect to the bit lines B u 1 to B un and B u 1 to B un of the memory mat u and d.
- the control signal buffer circuit CSB is not particularly limited, but for example, chipnable signals supplied to external terminals / CE, ZOE, / WE, SC, etc. , Output enable signal, write enable signal, serial clock signal, etc. are input, and these The timing signal of the internal control signal is generated according to the signal, and the ready / busy signal is input from the external terminal RZ (/ B) to the mode control circuit MC.
- "/" such as / CE, / OE, / WE represents a complementary signal.
- the power supply voltage Vcc and the ground voltage Vs s are input from the outside, and the word line voltage during erasing (raising the threshold voltage) operation.
- Vh its verification word line voltage Vhv
- Vmw memory well voltage
- the read bit line voltage Vrb, the read reference bit line voltage Vr r, the drain terminal voltage VI d during write operation, and its transfer gate voltage V 1 t are generated.
- the voltage name subscript is the same as the supplied memory mat subscript uZd.
- each of the above voltages may be supplied from the outside.
- Each voltage generated here is the voltage Vh, Vh v, V VIV and the transfer voltage V 1 t to the row address decoder circuit XDCR, and the voltage V rb, V rr, VI d and
- the transfer voltage V 1 t is input to the sense ratchet circuit S
- the memory voltage Vmw is input to the memory circuit voltage switching circuit MWVC, the array decoder XDCR circuit, and the sense ratchet circuit SL, respectively.
- the rows supplied from the external terminals, the rows receiving the column address signals AX and AY, and the complementary address signals formed through the column address buffer circuits XADB and YADB are the rows and columns.
- the above row, column address buffer circuit XADB, YADB is activated by the chip enable selection signal / CE inside the device, and takes in the address signals AX and AY from the external terminal. Only, a complementary address signal consisting of an internal address signal having the same phase as the address signal supplied from the external terminal and an address signal having the opposite phase is formed.
- the row address decoder circuit XDCR forms a selection signal of the edge line W of the memory cell group according to the competing address signal of the row address buffer XADB, and the column address device is used.
- the coder circuit YDCR forms the selection signal of the bit line B of the memory cell group according to the complementary address signal of the column address buffer circuit YADB.
- memory cell selection is performed by the row address decoder circuit XDCR and the column address decoder circuit YDCR to write and read in 8-bit or 16-bit units. Eight or sixteen memory cells are selected. Assuming that there are m memory cells in the word line direction (row direction) and n memory cells in the bit line direction (column direction) in one data block, there are 8 or 16 memory cells in the mxn memory cell group. It is composed of pieces and so on.
- the above memory cell is not particularly limited, but has a configuration similar to that of the EPR OM memory cell, for example, a known memory cell having a control gate and a floating gate, or a control gate and a floating gate, and a selection gate. It is a known memory cell having and.
- To i 1 2 8 memory cells are connected via a selective MOS transistor with the gate signal S i D as input.
- the common source line is connected to the sub source line for each unit block via a selective MO S transistor that takes the game signal S i S as an input.
- Figures 35 and 36 A, 36 B, and 36 C show cross-sectional views of memory cells showing an example of voltage application of selected and non-selected memory cells, which is the erasing operation of the present invention.
- the memory cells in Figures 35 and 36 A, 36 B, and 36 C are formed in the wel DP wel l in the device separation layer ni so region to separate from the storage device substrate p—sub.
- the voltage of the board p—sub is the same ground voltage V ss as before, and there is no particular limitation, but the voltage of the element separation layer ni so is higher than the source and drain terminal voltages, for example, the power supply voltage V cc and Supply the ground voltage V s s. The present invention Then, let the voltage of the element separation layer niso be the power supply voltage V c c.
- the voltage of the erase operation of the selected memory cell in Fig. 35 is 12 V applied to the control gate, and a negative voltage ⁇ 4 V is applied to the wall D P well and the source terminal. A voltage difference occurs between the floating gate and the channel, and electrons in the channel are injected into the floating gate by the Fowler-Nordheim tunnel phenomenon.
- the drain electrode of the memory cell is set to open to prevent steady current from flowing through the memory cell.
- the erase operation can be performed in the same time (about lm seconds) as the conventional erase time.
- the threshold voltage of the memory cell at the time of erasing can be set to be equal to or higher than the upper limit voltage Vc cma X of the power supply voltage Vcc, which is the selected word line voltage at the time of reading.
- the erasing is performed by repeatedly applying the erasing pulse divided into several times, and the operation of verifying the threshold voltage of the memory cell is performed after each erasing (verification).
- the erase verify wordline voltage is set to about 4.2 V.
- Figures 36 A, 36 B, and 36 C show the voltage application method to non-selected memory cells.
- 0V is used for the control gate
- -4V is used for the fuel DP well and the source terminal
- the drain terminal is open.
- Non-selected memory cells are disturbed by a channel voltage of 14 V.
- the applied voltage of this disturb is the same as the voltage applied by reversing the ⁇ -d line disturb at the time of reading.
- the selected voltage at read time is V cc at the power supply voltage
- its maximum voltage V c cma X is 3.6 V
- the general guaranteed voltage is 3.9 V
- the guaranteed time is 10 years (10 years). 3 X 1 0 8 seconds).
- the memory mat configuration is an open bit line system for the sensor latch circuit SL as shown in Fig. 8, the memory mat is divided into two.
- the number of parallel bits j which is a unit sector, is used.
- the Riseru receives erase disturb of the word line voltage corresponding 4 V 8 X 1 0 7 seconds. Therefore, the voltage value of the erasure disturb life is about the same as the guaranteed voltage value of the power supply voltage V cc, and the maximum guaranteed time is within the read hold SE time.
- the control gate is 0 V
- the fuel DP wel l is -4 V
- the source terminal is open
- the drain terminal is 0 V
- the control gate voltage and channel voltage are 0 V at the same potential.
- the control gate and memory DP wel l are set to 0 V
- the drain terminal and source terminal are set to 0 V or open
- the control gate voltage and channel voltage are 0 V at the same potential as in Fig. 36 B. V, which completely prevents the injection of electrons into the floating gates of non-selected memory cells.
- the maximum guaranteed erase time is 6.3 X 1 0. It can be reduced to s seconds.
- Figure 33 shows a conceptual diagram of the memory mat of the present invention.
- the sectors that make up the memory mat of the semiconductor non-volatile storage device are the sector in which the erase operation is selected and a positive voltage is applied to the word line (selected sector), and the sector in which the erase is not selected and the word line voltage and the memory well voltage are different. (Non-selected sector) In addition, it has a sector (completely non-selected sector) in which erasure is not selected and the word line voltage and the source-drain voltage (channel voltage) of the memory cell are equal.
- Fig. 39 shows the circuit diagram of the memory pine with AND type connection of the memory cells
- Fig. 40 shows the functional block diagram of the voltage generated to the memory mat.
- the circuit diagram of the well power supply switching circuit MWV C is shown in Fig. 41
- the voltage conversion circuit and driver circuit of the row recorder circuit XDCR etc. are shown in Fig. 42.
- the built-in power supply circuit VS in Fig. 40 consists of a reference voltage generation circuit, a step-down circuit, a booster pump circuit, a limiter circuit, and a power supply switching circuit, and is controlled by the mode control circuit MC.
- the write verification word line voltage V 1 V (1.5 V) can be generated by using the reference voltage of the step-down circuit composed of the current mirror circuit and the reference voltage generation circuit.
- the word line voltage V h at the time of erasing is 1 2 V
- the memorial voltage V mw is 14 V
- the word line voltage V 1 at the time of writing is -9 V, after each voltage is generated by the boost pump circuit.
- Limiter the reference voltage of the reference voltage generation circuit Used for circuits.
- FIG. 4 Memory power supply switching circuit
- the MWVC is a circuit that switches the memory voltage between the ground voltage V ss and the negative voltage 1 4 V, and is built-in during the erasing operation when the input signal MC 1 becomes low.
- the power supply voltage of 14 V in the power supply circuit VS is also activated, and the rising waveform of the voltage of the memory wheel rises in several / sec to several tens of seconds depending on the junction capacitance between the memory DP well and the element separation layer ni so.
- the voltage conversion circuit and driver circuit in Fig. 4 2 are the gate signals of the word line W, drain, source side selection MOS transformer, S i D, S i S, and the gate of the MOS transistor that distorts the potential of the bit line. It is connected to the MOS transistor that constitutes the sense latch circuit SL in the same wheel as the signal BDC and memory pine, for example, the gate signal TR.
- This circuit has a voltage higher than the power supply voltage, an erased word line voltage Vh of 12 V, a write voltage transfer voltage of V 1 h of 5 V, and a negative voltage, an eraser voltage of Vmw of 1 4 V, and a write word line voltage. It is a circuit that switches between V 1 and 9 V.
- the source voltage of the PMO S transistor of the voltage conversion circuit and the driver circuit is connected to the power supply voltage Vc during the write operation and to 1 2 V of the erase word line voltage Vh during the erase operation.
- the source voltage of the NMOS transistor in the element separation layer niso region in the same circuit is connected to the erasing voltage V mw, which becomes -4 V only during the erasing operation.
- the control signals MC 2 and NC are activated to a high level, and only the word line "W" for which the address signal is selected to be high becomes a voltage of 1 2 V, and the voltage of the non-selected ground line. Is the ground voltage V ss.
- the control signals MC 2 and / NC are activated to high, and only the word "W" for which the address signal is selected becomes the voltage of 19 V and is not selected.
- the voltage of the word line is the power supply voltage V cc.
- the word line voltage Vh at the time of erasing is raised from the power supply voltage V cc to 12 V. Due to the word line load capacitance of several pF, the rising waveform rises in several / i seconds to several tens / z seconds. This is because when the built-in power supply voltage is turned on and then the sector address get signal is switched, the MOS transistor is destroyed by passing through the minimum drain-source withstand voltage BVd sm in of the M ⁇ S transistor. Prevent that It's stopped.
- the threshold of the memory cell is set by setting the rising waveform of the voltage applied to the wire and the memory for the sector selected to be erased from a few ⁇ seconds to a few + seconds. It is possible to prevent a sudden application of an electric field that rewrites the value voltage, and it is possible to improve the number of rewrites.
- FIGS. 43 to 47 show the timing waveform diagram for one erase pulse for which the ed line W1 1 was selected in the erase operation. This waveform diagram is based on the circuit diagram of the memory pine shown in Fig. 39.
- FIG. 43 shows a conventional example
- FIGS. 4 to 47 show the erasure timing waveform of the present invention.
- the waveform of the selected word line Wl 1 is selected at the timing of t 1 and rises at the rising edge of the erased word line voltage Vh.
- S 1 D, SI S and BDC u be the power supply voltage V c c so that the drain and source, which are the channel voltages, are the ground voltage V s s of V mwu.
- FIG. 44 shows the first erasing operation timing waveform diagram of this embodiment.
- the edge line is not selected, and the activation of the erase edge line voltage Vh is terminated.
- the period between t 2 and t 3 is the erasure time for one pulse.
- FIG. 44 shows the first erasing operation timing waveform diagram of this embodiment.
- select the word line Wl 1 and memory wall of the selected sector and start the Vh and Vmwu voltages. Even if S 1 D, S 1 S, S i D, S i S, and BDC u are V ss, the MOS transistor is in the ON state, so the channel voltage of the memory cell on the selected sector side is V mwu — 4 V. It becomes.
- Figure 45 shows the second erasing operation timing waveform diagram of this embodiment. Raise the V h and V m wu voltages as in Figure 44.
- the channel voltage in the same block is set to 14 V, and the channel voltage of other blocks is set to V s s.
- Set TRu to BDC u to 1 4 V connect V s s of B unf supplied from the sense latch side to the bit line Bn, set S 1 S to V s s, and set S 1 D to 1 4 V in the selection block.
- Deselect the word line at the timing of t 4 erase the word line voltage Vh, and activate the memory voltage Vmwu. finish.
- the period from t 3 to t 4 is the erasure time for one pulse.
- Fig. 4 6 and Fig. 4 7 are waveforms with the rise of V h as t 2, and the other timings are the same as those in Fig. 15 and Fig. 16.
- the time to reach the ultimate potential differs depending on the current supply capacity of the built-in power supply voltage and the load capacity. Therefore, the erasure start time is clarified by starting the voltage generation circuit at the timing when the voltage arrival time at the rise of the memory wall voltage is equal to the voltage arrival time of the edge line voltage.
- the control gate during write operation that is, the wire is floated by applying a negative voltage of, for example, about 19 V, and selectively applying a voltage of, for example, about 4 V to the drain terminal of the write memory cell. A voltage difference occurs between the free gate and the drain, and the electrons in the floating gate move to the drain side.
- Fowl er-Nordheim Pulled out by the tunnel phenomenon By applying 0 V to the drain terminal of the non-selected memory cell, the voltage difference between the floating gate and the drain is suppressed, and the emission of electrons in the floating gate is prevented.
- the power supply voltage V c c is applied to prevent the discharge (electron discharge) due to the drain voltage. Therefore, the source electrode of the memory cell is opened to prevent steady current from flowing through the memory cell.
- the threshold voltage of the memory cell at the time of writing is the lower limit voltage V cc min of the power supply voltage V cc, which is the selected ed line voltage at the time of reading, and 0 V of the ground voltage V ss, which is the unselected ed line voltage. Must be in between. If the threshold voltage of a non-selected memory cell drops to a negative voltage, current will flow through the non-selected memory cell, resulting in an erroneous read. Therefore, the write operation is performed by repeatedly applying the write pulse divided into several times, and the operation and verification of verifying the threshold voltage of the memory cell are performed after each write.
- the write verification voltage is set to about 1.5 V so that the threshold voltage of all the memory cells to be written does not become 0 V.
- FIG. 38 shows the circuit diagram of the sense latch circuit SL when the connection between the memory mat and the sense latch circuit SL is arranged by the open bit line method shown in Fig. 37.
- the sense latch circuit SL including the flip-flop is connected to the bit wires Bun and Bdn. It has the same (equivalent) connection configuration for bit lines Bun and Bdn. Further, the sensor latch circuit S L may be connected to the even Z odd number of bit lines by dividing the control signal. This is to prevent the interparasitic capacitance of the bit line from affecting the sense operation. For example, during the sense operation of the memory cell connected to the even bit line side, the potential of the odd bit line Is V s s, and the memory cell on the even-numbered bit line side is read with a constant value between parasitic lines.
- the bit line Bu 1 is a gate signal RCu that precharges the potential of the bit line.
- the MOS transistor Ml used as the input and the MOS transistor M2 used as the gate of the pre-charge signal PC u are connected via the MOS transistor M 3 which uses the flip-flop information as the gate input signal.
- the connection between M 2 and M 3 is not limited, and the power supply voltage V c c side may be M 2 and the bit line side may be M 3.
- a MOS transistor M4 that inputs the gate signal TRu is connected between the bit line B u 1 and the flip-flop side wiring B u 1 f.
- the flip-flip side wiring B u 1 f has a MOS transistor M5 that inputs RSLu, a gate signal that charges the flip-flip potential to the ground voltage V ss, and a column gate signal Y according to the column address.
- a MOS transistor M6 that takes add as an input and outputs flip flop information overnight is connected to a MOS transistor M7 that uses a get input signal as flip flop information.
- the drain of the MOS transistor! ⁇ 7 is the shared signal ALu, the source is the ground voltage V s s, and a multi-stage input NOR circuit connection is established. That is, it is determined that the information of all the connected flip flops becomes the contact voltage V s s.
- bit line Bun is a gate signal that discharges the potential of the bit line Bun to the source line voltage. It is connected by MOS transistor power with BDu as input.
- At least the fuel of the MOS transistor to which the negative voltage is supplied to the diffusion layer of the source and drain is formed in the same memory well as the memory cell.
- the semiconductor non-volatile storage device of this embodiment not only when it is used as a flash memory in a storage device unit, but also for storage of various systems such as a computer system, a digital'still' camera system, and an automobile system. It is widely used as a device, and as an example, it is shown in Fig. 19 about a computer system.
- the semiconductor non-volatile storage device such as the flash memory of this embodiment can be widely applied as a flash file system of a computer system.
- the semiconductor non-volatile storage device of this embodiment is, for example, a flash memory composed of a plurality of memory mats composed of transistors whose value voltage can be electrically rewritten, and is a memory mat Memory Mat and a row address buffer circuit XADB.
- Line memory decoder circuit X DC R Sensor circuit shared by sense amplifier and data latch SNS and column gate array circuit YG, Column address buffer circuit YAD B, Column address decoder circuit YD CR, Input buffer circuit DIB, Output buffer circuit DOB It consists of a multiplexer circuit MP, a mode control circuit MC, a control signal buffer circuit CSB, and a built-in power supply circuit VS.
- the memory mat Memory Mat of this embodiment is connected to the sense latch circuit SNS by providing one sense latch circuit SNS for each of the bit lines B 1 to B n. For example, as shown in Fig. 58.
- control signal buffer circuit CSB is not particularly limited, but for example, the chipnable signal supplied to the external terminals ZCE, ZOE, /WE.SC, etc. Outputtable signals, write enable signals, serial clock signals, etc. are input, and timing signals for internal control signals are generated in response to these signals.
- the mode control circuit MC is connected to the external terminal RZ (/ B). A radioactivity signal is input.
- "/" such as ZCE, ZOE, / WE represents a complementary signal.
- the power supply voltage V c c and the ground voltage V s s are input from the outside, and the word line voltage during erasing (increasing the threshold voltage) operation.
- Vh its verification word line voltage Vhv
- write (lower the threshold voltage) word line voltage V 1 during operation its verify line voltage V 1 V
- read bit line voltage V rb read The reference line voltage V rr, the drain terminal voltage V 1 d during write operation, its transfer voltage V 1 t, etc. are generated.
- the voltage name subscript is the same as the supplied memory pine subscript uZd. Each of the above voltages may be supplied from the outside.
- Each voltage generated here has a word line voltage Vh, Vh v, VI, V lv and a transfer voltage V 1 t to the row address decoder circuit XDCR, and a bit line voltage V rb, V rr, VI d and transfer.
- the gate voltage V 1 t is input to the sense latch circuit SNS.
- rows and columns supplied from external terminals, rows and columns that receive column address signals AX and AY, and complementary address signals formed through column address buffer circuits XADB and YADB are rows and columns.
- column address buffer circuits XADB and YADB are activated by the chip enable selection signal / CE inside the device and take the address signals AX and AY from the external terminals.
- the internal address signal is in phase with the internal address signal supplied from the external terminal. Form a competing dress signal consisting of a dress signal.
- the rowless decoder circuit XDCR forms the selection signal of the edge line W of the memory cells according to the offset signal of the rowless buffer XADB, and the column adapter circuit YDCR is a complementary address of the column address buffer circuit YADB.
- the selection signal of the bit line B of the memory cell group according to the signal is formed.
- memory cell selection can be performed in 8-bit or 16-bit units.
- Memory cells can be written and read by the row memory decoder circuit XDCR and the column memory decoder circuit YDCR. Is 8 or 1 6 and so on. Assuming that there are m memory cells in the ed line direction (row direction) and n memory cells in the bit line direction (column direction) in one data block, there are eight memory cell groups of mxn memory cells or eight memory cells. 1 Consists of 6 pieces.
- the above memory cell is not particularly limited, but has a configuration similar to that of an EPROM memory cell, for example, a known memory cell having a control gate and a floating gate, or a control gate and a floating gate, and a selection gate. It is a known memory cell having and. For example, International Electron, published in 1987.
- the NAND type shown in Fig. 52 is a unit block in which multiple memory cells are connected in series, and both the bit line side and the source line side are connected via MOS transistors.
- FIG. 51 shows a schematic layout diagram of the present invention as opposed to the schematic layout diagram of FIG. 50 described in JP-A-7-17 6705.
- the bit line Bn is the metal wiring layer M 2
- the common source line SL is arranged by the wide metal wiring layer M 1 in the direction parallel to the ward line
- the source of the unit block is the unit block. It is a layer configuration that is connected to the common source line SL for each.
- the line width of the common source line uses a wide wiring that is about 100 times the line width of the bit line.
- Fig. 48 shows the layout of the metal wiring layer in which multiple unit blocks are arranged in the bit line direction
- Fig. 49 shows the schematic diagram of the layout of the metal wiring layer of the memory pine.
- the common source line is not arranged between the bit lines, but is parallel to the word line.
- the metal wiring layer of the common source wire is formed in the manufacturing process prior to the metal wiring layer used for the bit wire.
- a common source line in the row direction is arranged in the same metal wiring layer as the bit line.
- Figure 54 shows the equivalent circuit of the memory cell array when the common source line is wide enough and the resistance is small. Since the wiring of the common source line S L is wide enough and the resistance value is small, the value of the source resistance after the MOS transistor on the source side becomes a constant value. Therefore, the threshold voltage of the memory cell due to the substrate bias effect does not vary in word line units, that is, sector units. In addition, the size of the device can be reduced by eliminating the dummy memory cell sequence formed under the common source line in Fig. 50.
- the manufacturing method of the semiconductor non-volatile storage device of this embodiment is a method of contacting a metal wiring layer and the metal wiring layer with the manufacturing method described in Japanese Patent Application Laid-Open No. 7-1 7 6 7 0 5 of the prior art. This is a new contact hole with a new process added.
- a negative voltage of about 19 V is applied to the ed wire, and a voltage of about 4 V is selectively applied to the drain terminal of the write memory cell, so that the voltage between the floating gate and the drain is increased. A difference occurs, and the electrons in the floating gate are drawn to the drain side by the Fowler-Nordhe im tunnel phenomenon.
- the voltage difference between the floating gate and the drain is suppressed and the floating is performed. Prevents the emission of electrons in the play gate.
- the threshold voltage of the memory cell at the time of writing is the lower limit voltage V c cm in of the power supply voltage V cc, which is the selected voltage at the time of reading, and the ground voltage V ss, which is the unselected voltage. Must be between 0 V. If the threshold voltage of a non-selected memory cell drops to a negative voltage, current will flow through the non-selected memory cell, resulting in an erroneous read. Therefore, the write operation is performed by repeatedly applying the write pulse divided into several times, and the operation and verification of verifying the threshold voltage of the memory cell are performed after each write.
- the write verification voltage is set to about 1.5 V so that the threshold voltage of all the memory cells to be written does not become 0 V.
- the voltage information applied to the drain terminal of the memory cell shown above is stored in the flip flap FF in the sense latch circuit connected to the drain terminal via the bit wire.
- the verify operation is a voltage value that verifies the word line voltage. For example, set it to 4.2 V for write verification and 1.5 V for erase verification, and perform the same operation as the read operation.
- Fig. 58 shows the circuit diagram of the sense ratchet circuit SNS
- Fig. 59 shows the timing waveform diagram of the read operation.
- the connection between the memory mat Memory Mat u / d and the sense rattling circuit SNS is arranged by the open wire method.
- a sense latch circuit SNS including a flip-flop FF is connected to the bits Bn u and Bnd. It has the same (equivalent) connection configuration for the bit lines Bnu and Bnd.
- the sense latch circuit SNS is connected by dividing the control signal to the even Z odd number of the bit line. This is to prevent the influence of the parasitic line capacitance of the bit line on the sense operation.
- the memory cell connected to the even bit line side As shown in the evening iming waveform diagram of Fig. 59, for example, in the memory cell connected to the even bit line side. During the sense operation, the memory cell on the even-numbered bit line side is read out with the potential of the odd-numbered bit line as V ss and the capacitance between the parasitic lines at a constant value.
- the bit line B 1 u has the potential of the bit line pre.
- the MOS transistor M l that inputs the gate signal RP eu for charging and the MOS transistor M 5 that inputs the gate signal BD e u that charges the potential of the bit line are connected.
- the MOS transistor M2 that receives the gate signal TRe u is strongly connected between the bit line B 1 u and the flip-flop FF side distribution B 1 fu.
- the wiring B 1 fu on the flip-flop side is a MOSFET transistor M 3 that inputs the gate signal RF eu that discharges the voltage of the flip-flop to the ground voltage V s s, and the column game according to the array address.
- a MOS transistor M4 that takes the voltage signal Ya dd as an input and outputs the flip-flop FF information as data is connected.
- the read operation will be described using the timing waveform diagram shown in Fig. 59.
- the selected mat side is the Memory Mat u side
- the threshold voltage of the memory cell connected to the even side of the bit line is the write memory cell
- the memory cell on the odd side is the erase memory cell.
- the word line with t 1 selects the word line with t 1, and apply the precharge voltage to the bit line and sub bit line with t 2 before t 3 when the word line potential rises. That is, at t 2, the bit line reset signal BD eu / d is inactive, the bit line side MOS transition evening gate signal S i D uZ d is activated, and the precharge signal RP is between t 2 and t 3. Activates eu / d. To set the drain voltage of the selected memory cell to 1 V, that is, the potential of the bit line B nu to 1 V and the potential of the non-selected side bit line to 0.5 V, set the threshold voltage of the transfer MOS transistor. Considering this, the potential of RP eu is 2.0 V and the potential of RP ed is 1.5 V.
- t 3 activates the gate signal S i S u / d of the source line side MOS transistor, and t 4 deactivates the gate signal S i D u / d of the bit line side MOS transistor.
- the reset signal RF e u / d of the flip-flop FF is activated between t 2 and t 4.
- the threshold voltage information of the memory cell is taken into the flip-flop FF.
- Data can be captured by selecting TRe u / d and activating the power supply voltages VEP e and V FN e of the flip flop FF on the even side. That is, When the threshold voltage, which is the information of Morisel, is low, the potential of the bit line is discharged, and when it is below the reference voltage, the data of the flip-flop FF becomes Vs s of the ground voltage. When the threshold voltage of the memory cell is high, the precharge voltage is maintained, so the data of the flip-flop FF is Vcc of the power supply voltage.
- the even side bit line and sub bit line Sub Bit Line is discharged to the ground voltage V s s.
- the read operation on the odd side is performed between t 6 and t 7 in the same manner as the read operation on the even side.
- the threshold voltage difference V th shown in Fig. 56 can be reduced, and the reading of information on a sector-by-sector basis is stabilized, that is, the threshold voltage variation. Can be reduced, and the area of the device can be reduced.
- a PC controller that is detachably provided in the system is used, and this PC card has ROM and RAM, for example, as shown in Fig. 60.
- this PC card can send and receive data between the flash array FLASH—ARRAY, control logic circuit Control Logic, buffer circuit Buffer, and interface circuit Interface, and the PC card can be sent to the system itself. It is connected to the system bus SYSTEM—BUS via the interface circuit Interface.
- the central processing unit CPU manages the entire data in an 8-bit data format. It controls interface control, rewriting and reading operation control, and arithmetic processing.
- the flash array FLASH—ARRAY is formed by, for example, a 3 2 M bit flash device array, for example, 1 sector is 5 1 2 buys. It consists of a data area and a utility area of 16 bytes, and is a device with 8 1 9 2 sectors.
- controller controller is formed from cell-based or discrete IC, and has a sector table such as DRAM or SRAM.
- the control logic circuit Control Logi c generates timing signals and control signals, and the buffer circuit Buffer is used for temporary storage of data at the time of rewriting.
- storage devices such as flash memory can also be used for PC power, and this non-volatile semiconductor storage device can be widely used in various systems that require electrical data rewriting. can.
- the memory cell to be written By adding the operation sequence of low threshold level, select back, high threshold value verification, and reselective write to the sequence, the memory cell to be written. Since the threshold voltage of can be suppressed within the range from the low threshold verify line voltage to the high threshold verify line voltage, it is possible to improve the read operation monitor. It becomes.
- the Fowler-Nordheim tunnel phenomenon is used for rewriting, reselection, and reselective writing operations to achieve a single low-voltage power supply, and errat ic. It is possible to suppress the phenomenon, and especially in computer systems using this, it is possible to reduce the power consumption of the system and improve the reliability by lowering the voltage.
- the voltage applied to the memory cell 1 6 V required for the erase operation is 1 to the selected word line.
- the maximum voltage of the erase operation is lowered to the same level as the maximum operating voltage of the write operation, the gate insulating film is 19 nm, and the gate length is 1 ⁇ m.
- MOS transistors can be used, and the chip size of the semiconductor non-volatile storage device can be reduced.
- the size of the memory cell can be reduced by 3% by connecting the common source line of the memory cell array pine for each memory cell row of the unit block and not arranging the dummy memory cell row between the bit lines, and the semiconductor non-volatile device. It is possible to reduce the chip size of.
- the board bias applied to the memory cells connected to the same threshold line, that is, the sector becomes constant. It is possible to stabilize the reading of information on a sector-by-sector basis, that is, to reduce the variation in the threshold voltage.
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP51012597A JP4038823B2 (ja) | 1995-08-31 | 1996-08-29 | 半導体不揮発性記憶装置及びそれを用いたコンピュータシステム |
US09/029,748 US5978270A (en) | 1995-08-31 | 1996-08-29 | Semiconductor non-volatile memory device and computer system using the same |
AU68372/96A AU6837296A (en) | 1995-08-31 | 1996-08-29 | Semiconductor non-volatile memory device and computer system using the same |
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7/223016 | 1995-08-31 | ||
JP22301695 | 1995-08-31 | ||
JP22499195 | 1995-09-01 | ||
JP7/224991 | 1995-09-01 | ||
JP23102595 | 1995-09-08 | ||
JP7/231025 | 1995-09-08 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1997008707A1 true WO1997008707A1 (fr) | 1997-03-06 |
Family
ID=27330729
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP1996/002419 WO1997008707A1 (fr) | 1995-08-31 | 1996-08-29 | Dispositif de memoire non volatile a semi-conducteur et systeme informatique faisant appel a ce dispositif |
Country Status (6)
Country | Link |
---|---|
US (3) | US5978270A (ja) |
JP (2) | JP4038823B2 (ja) |
KR (1) | KR100460845B1 (ja) |
AU (1) | AU6837296A (ja) |
TW (1) | TW364115B (ja) |
WO (1) | WO1997008707A1 (ja) |
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US9318208B1 (en) * | 2014-12-17 | 2016-04-19 | Yield Microelectronics Corp. | Method for operating small-area EEPROM array |
US10467432B2 (en) | 2016-06-10 | 2019-11-05 | OneTrust, LLC | Data processing systems for use in automatically generating, populating, and submitting data subject access requests |
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- 1996-08-29 KR KR10-1998-0701461A patent/KR100460845B1/ko not_active IP Right Cessation
- 1996-08-29 US US09/029,748 patent/US5978270A/en not_active Expired - Lifetime
- 1996-08-29 JP JP51012597A patent/JP4038823B2/ja not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
---|---|
AU6837296A (en) | 1997-03-19 |
US6130841A (en) | 2000-10-10 |
KR19990044225A (ko) | 1999-06-25 |
JP2009105448A (ja) | 2009-05-14 |
TW364115B (en) | 1999-07-11 |
JP4038823B2 (ja) | 2008-01-30 |
US5978270A (en) | 1999-11-02 |
US6442070B1 (en) | 2002-08-27 |
KR100460845B1 (ko) | 2005-05-24 |
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