WO1997018588A1 - Improved charge pumps using accumulation capacitors - Google Patents

Improved charge pumps using accumulation capacitors Download PDF

Info

Publication number
WO1997018588A1
WO1997018588A1 PCT/US1996/012122 US9612122W WO9718588A1 WO 1997018588 A1 WO1997018588 A1 WO 1997018588A1 US 9612122 W US9612122 W US 9612122W WO 9718588 A1 WO9718588 A1 WO 9718588A1
Authority
WO
WIPO (PCT)
Prior art keywords
charge pump
pump circuit
capacitor
well
well region
Prior art date
Application number
PCT/US1996/012122
Other languages
French (fr)
Inventor
Lee E. Cleveland
Yong K. Kim
Chung K. Chang
Original Assignee
Advanced Micro Devices, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices, Inc. filed Critical Advanced Micro Devices, Inc.
Priority to KR1019980703211A priority Critical patent/KR19990067252A/en
Priority to JP8536018A priority patent/JPH11511904A/en
Publication of WO1997018588A1 publication Critical patent/WO1997018588A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0218—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of field effect structures
    • H01L27/0222—Charge pumping, substrate bias generation structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors with potential-jump barrier or surface barrier
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type

Definitions

  • This invention relates generally to semiconductor integrated circuit memory devices, such as flash elec ⁇ trically erasable programmable read-only memory (EEPROM) devices and more particularly, it relates to an improved charge pump utilizing an accumulation capacitor for use in EEPROM devices so as to internally pump up a power source voltage as supplied from an external or off-chip power supply on a more effective and efficient basis.
  • EEPROM electrically erasable programmable read-only memory
  • the semiconductor memory devices In the area of memory devices and other semiconductor integrated circuits there is often required a voltage to be internally generated that is greater than an external or off-chip power supply po- tential which is supplied to it. For instance, in flash electrically erasable, programmable read-only memories (EEPROM' s) high voltages such as ⁇ 12 V is needed to be produced for the programming and erasing modes of opera ⁇ tion of memory cells.
  • EEPROM' s electrically erasable, programmable read-only memories
  • the semiconductor memory devices generally also include an internal booster circuit of some type for internally boosting up the external power supply voltage.
  • charge pump One type of internal booster circuit commonly used in flash EEPROM's is referred to as a "charge pump.” While the user of such memory devices are not required to provide a high voltage source for its opera ⁇ tion, these memory devices do suffer from the disadvantage that the charge pumps often account for a significant percentage of the total power dissipation of such memory devices. Further, as the demand for higher and higher densities of the semiconductor memory devices increases, there exists a general miniaturization of all of the circuit elements forming the memory devices. Thus, there has been necessitated the use of lower power supply voltages not only as a way of reducing power dissipation, but also in order to prevent danger to the miniaturized circuit elements. There exists likewise a trend of decreasing the voltage for a battery power source for portable electronic applications to about 3 V or below. However, as the battery power source is reduced the conventional charge pumps utilizing inversion capacitors fail to provide an adequate degree of operation.
  • Figure la there is shown the electrical symbol for a capacitor-connected N-channel MOS transistor Nl.
  • Figures lb and lc show the cross-section and top plan views of the N-channel MOS transistor Nl, respectively.
  • the reference numeral 10 designates a p-type substrate.
  • An n-type drain region 12 and an n-type source region 14 are diffused in the surface of the substrate 10.
  • a thin gate oxide layer 16 is inter ⁇ posed between the top surface of the substrate and a con ⁇ ductive polysilicon gate 18.
  • the drain and source regions 12 and 14 are connected together and to a metal contact connection 20 defining one plate of the capacitor Nl.
  • the gate 18 is also joined to a metal contact connection 22 defining the other plate of the capacitor Nl.
  • FIG 2 there is illustrated a plot of the amount of capacitance value for the three operating regions (accumulation, depletion, and inversion) of the capacitor-connected MOS transistor Nl of Figure lb as a function of the voltage V g applied to the polysilicon gate.
  • the current output supplied from a charge pump becomes very small when the power source voltage is made small.
  • the output current of a charge pump is given by the following expression:
  • the output current of the charge pump can be made high by operating at higher frequencies. It is possible to increase the operating frequency of the capacitor operating in the inversion region by the adding of diffusion contacts 24 in the middle of the capacitor structure, as shown in Figure Id.
  • the diffusion contacts serve to generate a nearby supply of minority carriers and thus improves the frequency response of the capacitor. Therefore, it would be possible to further subdivide the capacitor structure so as to add more diffusion contacts 24 and further improve the frequency response.
  • this approach suffers from the draw- back that it also adds parasitic capacitance which re ⁇ Jerusalems the efficiency of the charge pump.
  • the amount of area occupied by the capacitor on a semiconductor chip is significantly increased.
  • FIG. 3a shows the electrical symbol for a capacitor-connected P-channel MOS transistor Pl.
  • Figure 3b shows the cross-sectional view of the P-channel MOS transistor Pl.
  • the capacitor is formed of a p-type substrate 26.
  • An n-well region 28 is formed in the substrate 26.
  • a p-type source region 30 and a p-type drain region 32 are diffused in the surface of the n-well region 28.
  • a thin gate oxide layer 34 is interposed between the top surface of the n-well region 28 and a conductive polysilicon gate 36.
  • an n-well contact region 38 is formed in the n-well region 28.
  • the contact region 38, source region 30, and drain region 32 are all connected together and to a metal contact connection 40 defining one plate of the capacitor Pl.
  • the gate 36 is also connected to a metal contact connection 42 defining the other plate of the capacitor Pl.
  • FIG 4 there is illustrated a plot of the capacitance value for the three operating regions (accumulation, depletion, and inversion) of the capacitor-connected MOS transistor Pl of Figure 3b as a function of the voltage V g applied to the polysilicon gate. It will be noted again that when the capacitor Pl is being operated in the inversion region there is the disadvantage of having the capacitance value fall off at the higher frequencies.
  • Figure 7 there is depicted a schematic circuit diagram of a single stage positive voltage charge pump 44 of the prior art.
  • the charge pump 44 includes a pair of N-channel MOS transistors Tl, T2 and the inversion capa ⁇ citor Nl (similar to Figure lb) .
  • the drain and gate of the transistor Tl are connected together and to an input voltage terminal 46 for receiving a power supply voltage source VCC.
  • the gate and drain of the transistor T2 are also connected together and to the source of the transis ⁇ tor Tl and to one plate of the capacitor Nl at node A.
  • the other plate of the capacitor Nl is connected to an input node 48 for receiving a clock signal ⁇ .
  • the source of the transistor T2 is connected to the output terminal OUT of the charge pump 44.
  • the initial condition of the node A must be greater than the threshold voltage of the capacitor- connected MOS transistor Nl, which is approximately 1 volt.
  • the operating voltage of the inversion capacitor cannot be reduced or lowered below 1 volt.
  • the accumulation capacitor can be initialized at 0 volts as depicted in Figure 2.
  • Another disadvantage of the inversion capacitor is that its effective threshold is increased due to the "body effect,” which is caused by the differential potential applied between the source and the substrate of the transistor Nl.
  • the present invention provides an improved charge pump by utilizing accumulation capacitors which is able to operate at lower voltages and with higher efficiency.
  • the present invention is concerned with the provision of a charge pump circuit utilizing accumulation capacitors for use in EEPROM devices so as to internally pump up an ex ⁇ ternal power supply voltage.
  • the charge pump circuit includes a plurality of MOS transistors connected in series between a first input voltage terminal and a higher voltage output terminal. The first input voltage terminal receives an external power supply voltage.
  • An accumulation capacitor has a first plate and a second plate.
  • the first plate of the accumulation capacitor is connected between adjacent ones of the plurality of MOS transistors.
  • the second plate of the accumulation capacitor is connected to a second input terminal for receiving a clock signal.
  • N-channel MOS transistor Nl connected so as to form an inversion capacitor for use in positive charge pumps
  • Figure lb is a cross-sectional view of the capacitor-connected N-channel MOS transistor Nl of Figure la;
  • Figure lc is top plan view of the capacitor- connected N-channel MOS transistor Nl of Figure lb;
  • Figure Id is a top plan view of a capacitor- connected N-channel MOS transistor, similar to Figure lc, which has an improved frequency response;
  • Figure 2 is a graph illustrating the capacitance value for the three operating regions of the capacitor- connected N-channel MOS transistor Nl of Figure lb as a function of the gate voltage V g ;
  • Figure 3a shows the electrical symbol for a P- channel MOS transistor Pl connected so as to form an inversion capacitor for use in negative charge pumps;
  • Figure 3b is a cross-sectional view of the capacitor-connected P-channel MOS transistor Pl of Figure 3a;
  • Figure 4 is a graph illustrating the capacitance value for the three operating regions of the capacitor- connected P-channel MOS transistor Pl of Figure 3b as a function of the gate voltage V g ;
  • Figure 5a shows the electric symbol for an n-well capacitor for use as an accumulation capacitor in posi- tive charge pumps
  • Figure 5b is a cross-sectional view of the n-well capacitor of Figure 5a, constructed in accordance with the principles of the present invention
  • Figure 6a shows the electrical symbol for a p-well capacitor for use as an accumulation capacitor in nega ⁇ tive charge pumps
  • Figures 6b is a cross-sectional view of the p-well capacitor of Figure 6a, constructed in accordance with the principles of the present invention
  • Figure 7 is a schematic circuit diagram of a single stage positive voltage charge pump of the prior art, utilizing an inversion capacitor similar to Figure lb;
  • Figure 8 is a schematic circuit diagram of a single stage positive voltage charge pump of the present invention, utilizing an accumulation capacitor similar to Figure 5b;
  • Figure 9 is a schematic circuit diagram of a single stage negative voltage charge pump of the present inven ⁇ tion, utilizing an accumulation capacitor similar to Figure 6b. DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • FIG. 5a there is shown an electrical symbol for an n-well capacitor N2 for use as an accumulation capacitor in positive voltage charge pumps.
  • Figure 5b a cross- sectional view of the n-well capacitor of Figure 5a, which is constructed with the principles of the present invention.
  • the reference numeral 110 denotes an N-well region.
  • n-type well electrode regions 112 and 114 there are formed n-type well electrode regions 112 and 114 in the n-well region 110.
  • a thin gate oxide layer 116 is interposed between the top surface of the n-well region and a conductive polysilicon gate 118.
  • the n-type well electrode regions 112 and 114 are connected together and to a metal contact connection 120 defining one plate of the n-well capacitor N2.
  • the gate 118 is also joined to a metal contact connection 122 defining the other plate of n-well capacitor N2.
  • FIG 8 there is illustrated a schematic circuit diagram of a single stage positive charge voltage pump 144 utilizing an accumulation capacitor, constructed in accordance with the principles of the present invention.
  • the charge pump 144 includes a pair of N-channel MOS transistor T101, T102 and the accumulation capacitor N2 (similar to Figure 5b) .
  • the gate and drain of the transistor T101 are connected together and to an input voltage terminal 146 for receiving a power supply voltage source VCC.
  • the gate and drain of the transistor T102 are also connected together and to the source of the transistor T101 and to one plate 122 of the n-well capa ⁇ citor N2 at an internal node B.
  • the other plate 120 of the capacitor N2 is connected to an input terminal 148 for receiving a clock signal ⁇ .
  • the source of the transistor T102 is connected to the output node OUT of the charge pump 144.
  • the power supply voltage source VCC which is typically at +3.0 volts, can be reduced to approxi ⁇ mately 2 volts so as to operate adequately in battery powered applications, thereby reducing significantly the power dissipation.
  • the efficiency of the charge pump 144 can be increased by about 20% over the prior art charge pump 44 using the inversion capacitor.
  • the present charge pump 144 can be operated at a higher frequency of the switching voltage supply since the capacitance value in the accumulation region, unlike the inversion region, does not fall off at higher fre- quencies.
  • the accumulation capacitors do not suffer from the "body effect" since there is no source-substrate voltage differential.
  • FIG. 6b a cross-sectional structural view of the p-well capacitor of Figure 6a, which is constructed in accordance with the principles of the present invention.
  • the reference numeral 210 designates a p-type substrate which has formed therein an n-well region 212.
  • a p-well region 214 is, in turn, formed in the n-well region 212.
  • a thin gate oxide region 220 is interposed between the top surface of the p-well region and a conductive polysilicon gate 222.
  • the p-well region 214 is electrically insulated from the p-type substrate 210.
  • the p-type well electrode regions 216 and 218 are connected together and to a metal contact connection 224 defining one plate of the p-well capacitor P2.
  • the gate 222 is also joined to a metal contact con ⁇ nection 226 defining the other plate of the capacitor P2.
  • FIG 9 there is illustrated a schematic circuit diagram of a single stage negative voltage charge pump 244 utilizing an accumulation capacitor, constructed in accordance with the principles of the present invention.
  • the charge pump 244 includes a pair of P- channel MOS transistors T201, T202 and the accumulation capacitor P2 (similar to Figure 6b) .
  • the gate and source of the transistor T201 are connected together and to an input voltage terminal 246 for receiving a power supply voltage source VSS, which is typically at ground potential.
  • the gate and source of the transistor T202 are connected together and to the drain of the transistor T201 and to one plate 226 of the p-well capacitor P2 at an internal node C.
  • the other plate 224 of the capacitor P2 is connected to an input node 248 for receiving a clock signal ⁇ .
  • the drain of the transistor T202 is also connected to the output terminal OUT of the charge pump.
  • the p-well capacitor P2 since the p-well capacitor P2 is being operated in the accumulation region, it can be likewise initialized at zero volts and has all the advantages similar to that described with respect the n-well capacitor N2.
  • Figures 8 and 9 show only single stage charge pumps, it should be apparent to those skilled in the art that they could be formed as multi-stage charge pumps.
  • a plurality of MOS transistors would be cascade-connected between the input voltage terminal and the output voltage terminal.
  • a corresponding plurality of capacitors would have their one end connected to respective internal nodes between adjacent transistors. Further, the other ends of the adjacent capacitors would be driven by non-overlapping two-phase clock signals ⁇ l and ⁇ 2.
  • the present invention provides improved charge pumps utilizing accumulation capacitors for use in EEPROM devices so as to internally pump up a power supply voltage.
  • the present charge pump overcomes the disad ⁇ vantages of the prior art so as to be capable of operating reliably and effectively at lower power supply voltage.
  • the charge pump of the present invention has improved efficiency since there is achieved a significant reduction in power consumption.

Abstract

A charge pump circuit utilizing accumulation capacitors for use in EEPROM devices so as to internally pump up an external power source voltage includes a plurality of MOS transistors (T101, T102; T201, T202) and accumulation capacitors (N2, P2). The plurality of MOS transistors are connected in series between a first input voltage terminal and a higher voltage output terminal. The first input voltage terminal receives the external power source voltage. The accumulation capacitor has a first plate and a second plate. Each of the first plates of the accumulation capacitors is connected between adjacent ones of the plurality of MOS transistors. Each of the second plates of the accumulation capacitors is connected to a second input terminal for receiving a clock signal. As a result, the pump circuit can be operated effectively so as to produce a significant reduction in power consumption.

Description

DESCRIPTION
IMPROVED CHARGE PUMPS USING ACCUMULATION CAPACITORS
BACKGROUND OF THE INVENTION
1. Field of the Invention:
This invention relates generally to semiconductor integrated circuit memory devices, such as flash elec¬ trically erasable programmable read-only memory (EEPROM) devices and more particularly, it relates to an improved charge pump utilizing an accumulation capacitor for use in EEPROM devices so as to internally pump up a power source voltage as supplied from an external or off-chip power supply on a more effective and efficient basis. 2. Description of the Prior Art:
As is generally known, in the area of memory devices and other semiconductor integrated circuits there is often required a voltage to be internally generated that is greater than an external or off-chip power supply po- tential which is supplied to it. For instance, in flash electrically erasable, programmable read-only memories (EEPROM' s) high voltages such as ±12 V is needed to be produced for the programming and erasing modes of opera¬ tion of memory cells. As a result, the semiconductor memory devices generally also include an internal booster circuit of some type for internally boosting up the external power supply voltage. One type of internal booster circuit commonly used in flash EEPROM's is referred to as a "charge pump." While the user of such memory devices are not required to provide a high voltage source for its opera¬ tion, these memory devices do suffer from the disadvantage that the charge pumps often account for a significant percentage of the total power dissipation of such memory devices. Further, as the demand for higher and higher densities of the semiconductor memory devices increases, there exists a general miniaturization of all of the circuit elements forming the memory devices. Thus, there has been necessitated the use of lower power supply voltages not only as a way of reducing power dissipation, but also in order to prevent danger to the miniaturized circuit elements. There exists likewise a trend of decreasing the voltage for a battery power source for portable electronic applications to about 3 V or below. However, as the battery power source is reduced the conventional charge pumps utilizing inversion capacitors fail to provide an adequate degree of operation.
In Figure la, there is shown the electrical symbol for a capacitor-connected N-channel MOS transistor Nl. Figures lb and lc show the cross-section and top plan views of the N-channel MOS transistor Nl, respectively. As can be seen, the reference numeral 10 designates a p-type substrate. An n-type drain region 12 and an n-type source region 14 are diffused in the surface of the substrate 10. A thin gate oxide layer 16 is inter¬ posed between the top surface of the substrate and a con¬ ductive polysilicon gate 18. The drain and source regions 12 and 14 are connected together and to a metal contact connection 20 defining one plate of the capacitor Nl. The gate 18 is also joined to a metal contact connection 22 defining the other plate of the capacitor Nl.
In Figure 2, there is illustrated a plot of the amount of capacitance value for the three operating regions (accumulation, depletion, and inversion) of the capacitor-connected MOS transistor Nl of Figure lb as a function of the voltage Vg applied to the polysilicon gate. As will be noted, when the capacitor is being operated in the inversion region there is the disad- vantage of having the capacitance value drop off at the higher frequencies. The current output supplied from a charge pump becomes very small when the power source voltage is made small. The output current of a charge pump is given by the following expression:
J ot c * V * F
where:
C = value of pump capacitance V = magnitude of switching power supply
F = frequency at which the voltage V is being switched
Thus, the output current of the charge pump can be made high by operating at higher frequencies. It is possible to increase the operating frequency of the capacitor operating in the inversion region by the adding of diffusion contacts 24 in the middle of the capacitor structure, as shown in Figure Id. The diffusion contacts serve to generate a nearby supply of minority carriers and thus improves the frequency response of the capacitor. Therefore, it would be possible to further subdivide the capacitor structure so as to add more diffusion contacts 24 and further improve the frequency response. However, this approach suffers from the draw- back that it also adds parasitic capacitance which re¬ duces the efficiency of the charge pump. Moreover, there is another disadvantage that the amount of area occupied by the capacitor on a semiconductor chip is significantly increased. Similarly, there is shown in Figure 3a the electrical symbol for a capacitor-connected P-channel MOS transistor Pl. Figure 3b shows the cross-sectional view of the P-channel MOS transistor Pl. The capacitor is formed of a p-type substrate 26. An n-well region 28 is formed in the substrate 26. A p-type source region 30 and a p-type drain region 32 are diffused in the surface of the n-well region 28. A thin gate oxide layer 34 is interposed between the top surface of the n-well region 28 and a conductive polysilicon gate 36. Further, an n-well contact region 38 is formed in the n-well region 28. The contact region 38, source region 30, and drain region 32 are all connected together and to a metal contact connection 40 defining one plate of the capacitor Pl. The gate 36 is also connected to a metal contact connection 42 defining the other plate of the capacitor Pl.
In Figure 4, there is illustrated a plot of the capacitance value for the three operating regions (accumulation, depletion, and inversion) of the capacitor-connected MOS transistor Pl of Figure 3b as a function of the voltage Vg applied to the polysilicon gate. It will be noted again that when the capacitor Pl is being operated in the inversion region there is the disadvantage of having the capacitance value fall off at the higher frequencies. In Figure 7, there is depicted a schematic circuit diagram of a single stage positive voltage charge pump 44 of the prior art. The charge pump 44 includes a pair of N-channel MOS transistors Tl, T2 and the inversion capa¬ citor Nl (similar to Figure lb) . The drain and gate of the transistor Tl are connected together and to an input voltage terminal 46 for receiving a power supply voltage source VCC. The gate and drain of the transistor T2 are also connected together and to the source of the transis¬ tor Tl and to one plate of the capacitor Nl at node A. The other plate of the capacitor Nl is connected to an input node 48 for receiving a clock signal φ. The source of the transistor T2 is connected to the output terminal OUT of the charge pump 44.
Referring again to the graph of Figure 2, it will be noted that for a full capacitance value in the inversion region the initial condition of the node A must be greater than the threshold voltage of the capacitor- connected MOS transistor Nl, which is approximately 1 volt. Thus, the operating voltage of the inversion capacitor cannot be reduced or lowered below 1 volt. On the other hand, the accumulation capacitor can be initialized at 0 volts as depicted in Figure 2. Another disadvantage of the inversion capacitor is that its effective threshold is increased due to the "body effect," which is caused by the differential potential applied between the source and the substrate of the transistor Nl.
Accordingly, it would be desirable to provide an improved charge pump which overcomes the disadvantages of the prior art so as to be capable of operating reliably and effectively at lower power supply voltages (i.e., at 3 V or lower) . It would be expedient that the charge pump be operated effectively so as to produce a significant reduction in power consumption. The present invention provides an improved charge pump by utilizing accumulation capacitors which is able to operate at lower voltages and with higher efficiency.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide an improved charge pump which overcomes all of the disadvantages of the prior art charge pumps.
It is an object of the present invention to provide an improved charge pump circuit utilizing accumulation capacitors for use in EEPROM devices so as to internally pump up a power source voltage on a more efficient and effective basis.
It is another object of the present invention to provide an improved charge pump circuit which is capable of operating reliably and effectively at lower power supply voltages. It is still another object of the present invention to provide an improved charge pump which can be operated efficiently so as to produce a significant reduction in power consumption.
In accordance with these aims and objectives, the present invention is concerned with the provision of a charge pump circuit utilizing accumulation capacitors for use in EEPROM devices so as to internally pump up an ex¬ ternal power supply voltage. The charge pump circuit includes a plurality of MOS transistors connected in series between a first input voltage terminal and a higher voltage output terminal. The first input voltage terminal receives an external power supply voltage.
An accumulation capacitor has a first plate and a second plate. The first plate of the accumulation capacitor is connected between adjacent ones of the plurality of MOS transistors. The second plate of the accumulation capacitor is connected to a second input terminal for receiving a clock signal.
BRIEF DESCRIPTION OF THE DRAWINGS These and other objects and advantages of the present invention will become more fully apparent from the following detailed description when read in con¬ junction with the accompanying drawings with like reference numerals indicating corresponding parts throughout, wherein: Figure la shows the electrical symbol for an
N-channel MOS transistor Nl connected so as to form an inversion capacitor for use in positive charge pumps;
Figure lb is a cross-sectional view of the capacitor-connected N-channel MOS transistor Nl of Figure la;
Figure lc is top plan view of the capacitor- connected N-channel MOS transistor Nl of Figure lb;
Figure Id is a top plan view of a capacitor- connected N-channel MOS transistor, similar to Figure lc, which has an improved frequency response;
Figure 2 is a graph illustrating the capacitance value for the three operating regions of the capacitor- connected N-channel MOS transistor Nl of Figure lb as a function of the gate voltage Vg;
Figure 3a shows the electrical symbol for a P- channel MOS transistor Pl connected so as to form an inversion capacitor for use in negative charge pumps;
Figure 3b is a cross-sectional view of the capacitor-connected P-channel MOS transistor Pl of Figure 3a;
Figure 4 is a graph illustrating the capacitance value for the three operating regions of the capacitor- connected P-channel MOS transistor Pl of Figure 3b as a function of the gate voltage Vg;
Figure 5a shows the electric symbol for an n-well capacitor for use as an accumulation capacitor in posi- tive charge pumps;
Figure 5b is a cross-sectional view of the n-well capacitor of Figure 5a, constructed in accordance with the principles of the present invention;
Figure 6a shows the electrical symbol for a p-well capacitor for use as an accumulation capacitor in nega¬ tive charge pumps;
Figures 6b is a cross-sectional view of the p-well capacitor of Figure 6a, constructed in accordance with the principles of the present invention; Figure 7 is a schematic circuit diagram of a single stage positive voltage charge pump of the prior art, utilizing an inversion capacitor similar to Figure lb;
Figure 8 is a schematic circuit diagram of a single stage positive voltage charge pump of the present invention, utilizing an accumulation capacitor similar to Figure 5b; and
Figure 9 is a schematic circuit diagram of a single stage negative voltage charge pump of the present inven¬ tion, utilizing an accumulation capacitor similar to Figure 6b. DESCRIPTION OF THE PREFERRED EMBODIMENTS
In the following, there will be described the preferred embodiments of the present invention with reference to the drawings. In Figure 5a, there is shown an electrical symbol for an n-well capacitor N2 for use as an accumulation capacitor in positive voltage charge pumps. There is illustrated in Figure 5b a cross- sectional view of the n-well capacitor of Figure 5a, which is constructed with the principles of the present invention. As can be seen, the reference numeral 110 denotes an N-well region. There are formed n-type well electrode regions 112 and 114 in the n-well region 110. A thin gate oxide layer 116 is interposed between the top surface of the n-well region and a conductive polysilicon gate 118. The n-type well electrode regions 112 and 114 are connected together and to a metal contact connection 120 defining one plate of the n-well capacitor N2. The gate 118 is also joined to a metal contact connection 122 defining the other plate of n-well capacitor N2. In Figure 8, there is illustrated a schematic circuit diagram of a single stage positive charge voltage pump 144 utilizing an accumulation capacitor, constructed in accordance with the principles of the present invention. The charge pump 144 includes a pair of N-channel MOS transistor T101, T102 and the accumulation capacitor N2 (similar to Figure 5b) . The gate and drain of the transistor T101 are connected together and to an input voltage terminal 146 for receiving a power supply voltage source VCC. The gate and drain of the transistor T102 are also connected together and to the source of the transistor T101 and to one plate 122 of the n-well capa¬ citor N2 at an internal node B. The other plate 120 of the capacitor N2 is connected to an input terminal 148 for receiving a clock signal φ. The source of the transistor T102 is connected to the output node OUT of the charge pump 144. With reference to the graph of Figure 2, it should be clear, as previously pointed out, that since the n-well capacitor N2 is operating in the accumulation region it can be initialized at zero volts. Further, the power supply voltage source VCC, which is typically at +3.0 volts, can be reduced to approxi¬ mately 2 volts so as to operate adequately in battery powered applications, thereby reducing significantly the power dissipation. As a result, the efficiency of the charge pump 144 can be increased by about 20% over the prior art charge pump 44 using the inversion capacitor. Moreover, the present charge pump 144 can be operated at a higher frequency of the switching voltage supply since the capacitance value in the accumulation region, unlike the inversion region, does not fall off at higher fre- quencies. In addition, the accumulation capacitors do not suffer from the "body effect" since there is no source-substrate voltage differential.
With reference to Figure 6a of the drawings, there is depicted an electrical symbol for a p-well capacitor P2 for use as an accumulation capacitor in negative voltage charge pumps. There is shown in Figure 6b a cross-sectional structural view of the p-well capacitor of Figure 6a, which is constructed in accordance with the principles of the present invention. As can be seen, the reference numeral 210 designates a p-type substrate which has formed therein an n-well region 212. A p-well region 214 is, in turn, formed in the n-well region 212. There are formed a pair of p-well electrode regions 216 and 218 in the p-well region 214. A thin gate oxide region 220 is interposed between the top surface of the p-well region and a conductive polysilicon gate 222. Thus, the p-well region 214 is electrically insulated from the p-type substrate 210. The p-type well electrode regions 216 and 218 are connected together and to a metal contact connection 224 defining one plate of the p-well capacitor P2. The gate 222 is also joined to a metal contact con¬ nection 226 defining the other plate of the capacitor P2.
In Figure 9, there is illustrated a schematic circuit diagram of a single stage negative voltage charge pump 244 utilizing an accumulation capacitor, constructed in accordance with the principles of the present invention. The charge pump 244 includes a pair of P- channel MOS transistors T201, T202 and the accumulation capacitor P2 (similar to Figure 6b) . The gate and source of the transistor T201 are connected together and to an input voltage terminal 246 for receiving a power supply voltage source VSS, which is typically at ground potential. The gate and source of the transistor T202 are connected together and to the drain of the transistor T201 and to one plate 226 of the p-well capacitor P2 at an internal node C. The other plate 224 of the capacitor P2 is connected to an input node 248 for receiving a clock signal φ. The drain of the transistor T202 is also connected to the output terminal OUT of the charge pump. With reference to the graph of Figure 4, it will again be noted that since the p-well capacitor P2 is being operated in the accumulation region, it can be likewise initialized at zero volts and has all the advantages similar to that described with respect the n-well capacitor N2.
While Figures 8 and 9 show only single stage charge pumps, it should be apparent to those skilled in the art that they could be formed as multi-stage charge pumps. In this case, a plurality of MOS transistors would be cascade-connected between the input voltage terminal and the output voltage terminal. A corresponding plurality of capacitors would have their one end connected to respective internal nodes between adjacent transistors. Further, the other ends of the adjacent capacitors would be driven by non-overlapping two-phase clock signals φl and φ2.
From the foregoing detailed description, it can thus be seen that the present invention provides improved charge pumps utilizing accumulation capacitors for use in EEPROM devices so as to internally pump up a power supply voltage. The present charge pump overcomes the disad¬ vantages of the prior art so as to be capable of operating reliably and effectively at lower power supply voltage. As a result, the charge pump of the present invention has improved efficiency since there is achieved a significant reduction in power consumption.
While there has been illustrated and described what are at present considered to be preferred embodiments of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made, and equivalents may be substituted for elements thereof without departing from the true scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the central scope thereof. Therefore, it is intended that this invention not be limited to the particular embodi¬ ments disclosed as the best modes contemplated for carrying out the invention, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims

CLAIMSWHAT IS CLAIMED IS;
1. A charge pump circuit utilizing accumulation capacitors for use in EEPROM devices so as to internally pump up an external power supply voltage, comprising: a plurality of MOS transistors (TIOI, T102; T201, T202) connected in series between a first input voltage terminal, and a higher voltage output terminal, said first input voltage terminal receiving the external power source voltage; accumulation capacitors (N2, P2) each having a first plate and a second plate; each of said first plates of said accumulation capacitors being connected between adjacent ones of said plurality of MOS transistors; and each of said second plates of said accumulation capacitors being connected to a second input terminal for receiving a clock signal.
2. A charge pump circuit as claimed in Claim 1, wherein said plurality of MOS transistors is comprised of N-channel transistors (T101, T102) .
3. A charge pump circuit as claimed in Claim 1, wherein said plurality of MOS transistors is comprised of P-channel transistors (T201, T202) .
4. A charge pump circuit as claimed in Claim 2, wherein said external power source voltage is comprised of a positive potential (VCC) , which is typically at +3.0 volts or lower.
5. A charge pump circuit as claimed in Claim 3, wherein said external power source voltage is comprised of a ground potential (VSS) , which is typically at zero volts.
6. A charge pump circuit as claimed in Claim 4, wherein each of said accumulation capacitors is comprised of an n-well capacitor (N2) .
7. A charge pump circuit as claimed in Claim 5, wherein each of said accumulation capacitors is comprised of a p-well capacitor (P2) .
8. A charge pump circuit as claimed in Claim 6, wherein said n-well capacitor includes a pair of n+ electrode regions (112, 114) formed in an n-well region
(110) and a gate oxide layer (116) disposed between the top surface of said n-well region and a polysilicon gate (118) .
9. A charge pump circuit as claimed in Claim 7, wherein said p-well capacitor includes a pair of p+ electrode regions (216, 218) formed in a p-well region
(214) within an n-well region (212) and a gate oxide layer (220) disposed between the top surface of said p- well region and a polysilicon gate (222) , said n-well region being disposed in a p-type substrate (210).
10. A positive voltage charge pump circuit for use in semiconductor memory devices, comprising: a pair of N-channel MOS transistors
(T101, T102) connected in series between a first input voltage terminal and a higher voltage output terminal, each of said pair of
N-channel MOS transistors having its gate and drain connected together, said first input voltage terminal receiving an external power source voltage; an n-well capacitor (N2) functioning as an accumulation capacitor having a first plate and a second plate; said first plate of said n-well capacitor being connected between junction of said pair of MOS transistors; and said second plate of said n-well capaci- tor being connected to a second input terminal for receiving a clock signal.
11. A charge pump circuit as claimed in Claim 10, wherein said external power source voltage is comprised of a positive potential (VCC) , which is typically at +3.0 volts or lower.
12. A charge pump circuit as claimed in Claim 11, wherein said n-well capacitor includes a pair of n+ electrode regions (112, 114) formed in an n-well region
(110) and a gate oxide layer (116) disposed between the top surface of said n-well region and a polysilicon gate (118) .
13. A charge pump circuit for use in a semicon¬ ductor integrated circuit device for generating at an output terminal a voltage which is pumped higher than an external power source voltage, comprising: transistor charging means connected between the external power source voltage and said output terminal for generating the higher voltage at said output terminal; and accumulation capacitor means connected to said transistor charging means and being responsive to clock signals for generating the higher voltage at said output terminal.
14. A charge pump circuit as claimed in Claim 13, wherein said transistor charging means is comprised of a plurality of N-channel transistors (T101, T102) .
15. A charge pump circuit as claimed in Claim 13, wherein said transistor charging means is comprised of a plurality of P-channel MOS transistors (T201, T202) .
16. A charge pump circuit as claimed in Claim 14, wherein said accumulation capacitor means is comprised of an n-well capacitor (N2) .
17. A charge pump circuit as claimed in Claim 15, wherein said accumulation capacitor means is comprised of a p-well capacitor (P2) .
18. A charge pump circuit as claimed in Claim 16, wherein said n-well capacitor includes a pair of n+ electrode regions (112, 114) formed in an n-well region
(110) and a gate oxide layer (116) disposed between the
110 top surface of said n-well region and a polysilicon gate (118) .
19. A charge pump circuit as claimed in Claim 17, wherein said p-well capacitor includes a pair of p+ electrode regions (216, 218) formed in a p-well region
115 (214) within an n-well region (212) and a gate oxide layer (220) disposed between the top surface of said p- well region and a polysilicon gate (222) , said n-well region being disposed in a p-type substrate (210).
PCT/US1996/012122 1995-11-13 1996-07-23 Improved charge pumps using accumulation capacitors WO1997018588A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019980703211A KR19990067252A (en) 1995-11-13 1996-07-23 Improved Charge Pump with Accumulated Capacitor
JP8536018A JPH11511904A (en) 1995-11-13 1996-07-23 Improved charge pump using storage capacitors

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US55811995A 1995-11-13 1995-11-13
US08/558,119 1995-11-13

Publications (1)

Publication Number Publication Date
WO1997018588A1 true WO1997018588A1 (en) 1997-05-22

Family

ID=24228287

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1996/012122 WO1997018588A1 (en) 1995-11-13 1996-07-23 Improved charge pumps using accumulation capacitors

Country Status (4)

Country Link
JP (1) JPH11511904A (en)
KR (1) KR19990067252A (en)
TW (1) TW283239B (en)
WO (1) WO1997018588A1 (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6074775A (en) * 1998-04-02 2000-06-13 The Procter & Gamble Company Battery having a built-in controller
US6118248A (en) * 1998-04-02 2000-09-12 The Procter & Gamble Company Battery having a built-in controller to extend battery service run time
US6163131A (en) * 1998-04-02 2000-12-19 The Procter & Gamble Company Battery having a built-in controller
US6198250B1 (en) 1998-04-02 2001-03-06 The Procter & Gamble Company Primary battery having a built-in controller to extend battery run time
EP1326284A2 (en) * 2001-12-27 2003-07-09 Broadcom Corporation A thick oxide P-gate NMOS capacitor for use in a phase-locked loop circuit and method of making same
US6835491B2 (en) 1998-04-02 2004-12-28 The Board Of Trustees Of The University Of Illinois Battery having a built-in controller
US7671384B2 (en) 2003-06-10 2010-03-02 Fujitsu Microelectronics Limited Semiconductor integrated circuit device having improved punch-through resistance and production method thereof, semiconductor integrated circuit device including a low-voltage transistor and a high-voltage transistor
US9397370B2 (en) 1999-06-25 2016-07-19 The Board Of Trustees Of The University Of Illinois Single and multiple cell battery with built-in controller
US9397234B2 (en) 2014-09-17 2016-07-19 Samsung Electronics Co., Ltd. Pumping capacitor

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8878118B2 (en) * 2012-08-15 2014-11-04 Omnivision Technologies, Inc. Capacitance selectable charge pump

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0062894A2 (en) * 1981-04-07 1982-10-20 Kabushiki Kaisha Toshiba Semiconductor device
EP0581702A1 (en) * 1992-07-30 1994-02-02 STMicroelectronics S.A. CMOS technology capacitor
EP0638984A1 (en) * 1993-08-11 1995-02-15 Advanced Micro Devices, Inc. Low voltage charge pumps

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0062894A2 (en) * 1981-04-07 1982-10-20 Kabushiki Kaisha Toshiba Semiconductor device
EP0581702A1 (en) * 1992-07-30 1994-02-02 STMicroelectronics S.A. CMOS technology capacitor
EP0638984A1 (en) * 1993-08-11 1995-02-15 Advanced Micro Devices, Inc. Low voltage charge pumps

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6074775A (en) * 1998-04-02 2000-06-13 The Procter & Gamble Company Battery having a built-in controller
US6118248A (en) * 1998-04-02 2000-09-12 The Procter & Gamble Company Battery having a built-in controller to extend battery service run time
US6163131A (en) * 1998-04-02 2000-12-19 The Procter & Gamble Company Battery having a built-in controller
US6198250B1 (en) 1998-04-02 2001-03-06 The Procter & Gamble Company Primary battery having a built-in controller to extend battery run time
US6835491B2 (en) 1998-04-02 2004-12-28 The Board Of Trustees Of The University Of Illinois Battery having a built-in controller
US9397370B2 (en) 1999-06-25 2016-07-19 The Board Of Trustees Of The University Of Illinois Single and multiple cell battery with built-in controller
EP1326284A3 (en) * 2001-12-27 2008-11-26 Broadcom Corporation A thick oxide P-gate NMOS capacitor for use in a phase-locked loop circuit and method of making same
US7547956B2 (en) 2001-12-27 2009-06-16 Broadcom Corporation Thick oxide P-gate NMOS capacitor for use in a low-pass filter of a circuit and method of making same
US8148219B2 (en) 2001-12-27 2012-04-03 Broadcom Corporation Thick oxide P-gate NMOS capacitor for use in a low-pass filter of a circuit and method of making same
EP1326284A2 (en) * 2001-12-27 2003-07-09 Broadcom Corporation A thick oxide P-gate NMOS capacitor for use in a phase-locked loop circuit and method of making same
US7671384B2 (en) 2003-06-10 2010-03-02 Fujitsu Microelectronics Limited Semiconductor integrated circuit device having improved punch-through resistance and production method thereof, semiconductor integrated circuit device including a low-voltage transistor and a high-voltage transistor
US8530308B2 (en) 2003-06-10 2013-09-10 Fujitsu Semiconductor Limited Semiconductor integrated circuit device having improved punch-through resistance and production method thereof, semiconductor integrated circuit device including a low-voltage transistor and a high-voltage transistor
US9397234B2 (en) 2014-09-17 2016-07-19 Samsung Electronics Co., Ltd. Pumping capacitor

Also Published As

Publication number Publication date
KR19990067252A (en) 1999-08-16
TW283239B (en) 1996-08-11
JPH11511904A (en) 1999-10-12

Similar Documents

Publication Publication Date Title
US6603346B2 (en) Semiconductor booster circuit having cascaded MOS transistors
US5892267A (en) Multi-stage voltage-boosting circuit with boosted back-gate bias
JP3159749B2 (en) Integrated circuit
US6130572A (en) NMOS negative charge pump
US6100557A (en) Triple well charge pump
JP2718375B2 (en) Charge pump circuit
US7956397B2 (en) Semiconductor device, charge pumping circuit, and semiconductor memory circuit
EP0836268A1 (en) Improved positive charge pump
US20070122964A1 (en) Semiconductor Device Equipped with a Voltage Step-Up Circuit
US7586361B2 (en) Semiconductor device comprising a charge pump operated by clock signals
US6026003A (en) Charge pump circuit and method for generating a bias voltage
US7439795B2 (en) Charge pump circuit with reduced parasitic capacitance
US5994949A (en) Negative voltage charge pump particularly for flash EEPROM memories
US20030057469A1 (en) Semiconductor charge pump circuit and nonvolatile semiconductor memory device
JPS60107857A (en) Voltage generating circuit in integrated circuit chip
JPH0462868A (en) Substrate bias generation circuit
US6037622A (en) Charge pump circuits for low supply voltages
JPH07154964A (en) Low-voltage charge pump
WO1997018588A1 (en) Improved charge pumps using accumulation capacitors
US6232826B1 (en) Charge pump avoiding gain degradation due to the body effect
US7808303B2 (en) Booster circuit
EP0931379B1 (en) Triple well charge pump
JPH07298607A (en) Semiconductor boosting circuit
JP2000503840A (en) Triple well charge pump
JP2000057790A (en) Voltage-generating circuit

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): JP KR

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 1019980703211

Country of ref document: KR

ENP Entry into the national phase

Ref country code: JP

Ref document number: 1996 536018

Kind code of ref document: A

Format of ref document f/p: F

122 Ep: pct application non-entry in european phase
WWP Wipo information: published in national office

Ref document number: 1019980703211

Country of ref document: KR

WWG Wipo information: grant in national office

Ref document number: 1019980703211

Country of ref document: KR