WO1997022138A2 - Flip-chip process for producing a multi-chip module - Google Patents

Flip-chip process for producing a multi-chip module Download PDF

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Publication number
WO1997022138A2
WO1997022138A2 PCT/DE1996/002218 DE9602218W WO9722138A2 WO 1997022138 A2 WO1997022138 A2 WO 1997022138A2 DE 9602218 W DE9602218 W DE 9602218W WO 9722138 A2 WO9722138 A2 WO 9722138A2
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WO
WIPO (PCT)
Prior art keywords
heat sink
component
multilayer circuit
substrate
chip
Prior art date
Application number
PCT/DE1996/002218
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German (de)
French (fr)
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WO1997022138A3 (en
Inventor
Ralf Haug
Original Assignee
Robert Bosch Gmbh
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Publication date
Application filed by Robert Bosch Gmbh filed Critical Robert Bosch Gmbh
Priority to JP09521598A priority Critical patent/JP2000501885A/en
Priority to EP96945743A priority patent/EP0865668A2/en
Publication of WO1997022138A2 publication Critical patent/WO1997022138A2/en
Publication of WO1997022138A3 publication Critical patent/WO1997022138A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The proposal is for a flip-chip process for producing a multi-chip module, in which a substrate (20), a multi-layer circuit (50, 60, 70), a component (15) and a heat sink (85) are combined according to the invention in such a way that solder or conductive adhesive is applied to the surface of the multi-layer circuit, e.g. by screen printing. It is now possible, as desired, to apply first a component (15) or a heat sink (85) thereon, whereupon the component and the heat sink are coated with a heat conducting adhesive and brought into thermal contact. This arrangement is covered by a plastic cap before being soldered or adhesively secured to a substrate with printed circuit tracks.

Description

Flip-Chip-Verfahren zur Herstellung eines Multichip-ModulsFlip-chip method for producing a multichip module
Stand der TechnikState of the art
Die Erfindung betrifft ein Flip-Chip-Verfahren zur Herstellung eines Multi-Chip-Moduls gemäß den Verfahrensschritten des Hauptanspruchs.The invention relates to a flip-chip method for producing a multi-chip module according to the method steps of the main claim.
Multi-Chip-Module sind grundsätzlich bekannt. Sie eignen sich als besonders wirtschaftliche Ausführungsform eines Bauelemente-Moduls . Dabei werden die Außenkontakte der Chips mit weiteren Chips und gegebenenfalls zusätzlichen elektrischen Bauelementen zu einer elektrischen Schaltung verbunden.Multi-chip modules are generally known. They are suitable as a particularly economical embodiment of a component module. The external contacts of the chips are connected to further chips and possibly additional electrical components to form an electrical circuit.
Vorteile der ErfindungAdvantages of the invention
Mit dem erfindungsgemäßen Verfahren nach dem Hauptanspruch gelingt es, kürzeste Chip- zu Chip-Verbindungen bei hoher Packungsdichte der einzelnen Bauelemente herzustellen. Kleine Leiterbahn-Kapazitäten und Leiterbahn-Induktivitäten verbessern die Hochfrequenzeigenschaften der Module bei gleichzeitig sehr guter thermischer Belastbarkeit der Schaltungsteile des Moduls. Die elektromagnetische Verträglichkeit und der mechanische Schutz der Bauelemente werden deutlich verbessert. Die Kosten werden gesenkt, wenn das Substrat als Gehäuseteil verwendbar ist. Es ist auch möglich, einzelne, mehrere oder alle Verfahrensschritte durch ein gemeinsames Verfahren zu automatisieren.With the inventive method according to the main claim, it is possible to produce the shortest chip to chip connections with a high packing density of the individual components. Small conductor capacitance and conductor inductance improve the high-frequency properties of the modules while at the same time having a very good thermal load capacity of the circuit parts of the module. The electromagnetic Compatibility and mechanical protection of the components are significantly improved. The costs are reduced if the substrate can be used as a housing part. It is also possible to automate individual, several or all process steps by a common process.
Durch die in den Unteransprüchen offenbarten Maßnahmen sind weitere Verbesserungen und Vorteile erhältlich. Zur Erhöhung der thermischen Belastbarkeit ist es zweckmäßig, thermische Durchkontaktierungen vom Substrat zu den Bauelementen vorzusehen. In speziellen Fällen kann der Wärmeleitkleber nach der Aushärtung die Funktion des Gehäuses eines oder mehrerer Bauelemente haben.The measures disclosed in the subclaims provide further improvements and advantages. To increase the thermal load capacity, it is expedient to provide thermal plated-through holes from the substrate to the components. In special cases, the thermal adhesive can function as the housing of one or more components after curing.
Das erfindungsgemäße Verfahren wird anhand der Figur und der darauf folgenden Herstellungsbeispiele näher erläutert.The method according to the invention is explained in more detail with reference to the figure and the subsequent production examples.
Die Figur zeigt einen Ausschnitt eines Multichip-Moduls 10, das nach dem erfindungsgemäßen Verfahren mit einem Bauelement (Chip) 15 hergestellt wurde. Natürlich kann das Modul 10 auch mehr als einen Chip IL aufweisen.The figure shows a section of a multichip module 10 which was produced with a component (chip) 15 using the method according to the invention. Of course, the module 10 can also have more than one chip IL.
Auf ein Substrat 20 sind Leiterbahnen 25 aufgebracht. Die Leiterbahnoberflächen 30 werden mit den Kontaktoberflächen 40 der Durchkontaktierungen 55, die in die Grundschicht 50 der mehrlagigen Schaltung 50, 60 ,70 eingebaut sind, durch Kontaktierungen 35 aus Lot oder Leitkleber verbunden. In die Deckschicht 70 der Mehrlageschaltung 50,60,70 sind Durchkontaktierungen 75, in die Mittelschicht 60 sind Leiterbahnen 65 eingebaut. Die Durchkontaktierungen 75 in der Deckschicht 70 sind mittels der Leiterbahnen 65 in der Mittelschicht 60 der Mehrlageschaltung 50,60,70 elektrisch leitend mit den Durchkontaktierungen 55 in der Grundschicht 50 verbunden. Das Bauteil 15 sitzt unter Zwischenlage einer dünnen Lot- oder Leitkleberschicht 76 mit Fußkontakten 80 auf den Oberflächen der Durchkontaktierungen 75 der Deckschicht 70 der Mehrlageschaltung 50,60,70 und ist in eine Aussparung 100 der Wärmesenke 85 eingebaut. Die Wärmesenke 85 ist auf der Deckschicht 70 der mehrlagigen Schaltung 50,60,70 unter Einfügung der Leitkleberschicht 76 angeordnet und wärmeleitend mit dem Bauteil 15 verbunden, indem eine Wärmeleitkleber-Masse 90 in den zwischen Bauteil 15 und Wärmesenke 85 verbleibenden freien Raum 95 der Aussparung 100 der Wärmesenke 85 vergossen ist. Zusätzlich wird die Wärmesenke 85 über wärmeleitende Durchkontaktierungen 130, 125 und 120 und die wärmeleitende Kontaktierung 135 mit einer Leiterbahn 25 auf dem Substrat 20 wärmeleitend verbunden.Conductor tracks 25 are applied to a substrate 20. The conductor track surfaces 30 are connected to the contact surfaces 40 of the plated-through holes 55, which are built into the base layer 50 of the multilayer circuit 50, 60, 70, by contacts 35 made of solder or conductive adhesive. Vias 75 are built into the top layer 70 of the multilayer circuit 50, 60, 70, and conductor tracks 65 are built into the middle layer 60. The plated-through holes 75 in the cover layer 70 are electrically conductively connected to the plated-through holes 55 in the base layer 50 by means of the conductor tracks 65 in the middle layer 60 of the multilayer circuit 50, 60, 70. The component 15 sits with the interposition of a thin solder or conductive adhesive layer 76 with foot contacts 80 on the surfaces of the plated-through holes 75 of the cover layer 70 of the multilayer circuit 50, 60, 70 and is installed in a recess 100 in the heat sink 85. The heat sink 85 is arranged on the cover layer 70 of the multi-layer circuit 50, 60, 70 with the insertion of the conductive adhesive layer 76 and is connected in a heat-conducting manner to the component 15 by a heat-conducting adhesive composition 90 in the free space 95 of the recess remaining between the component 15 and the heat sink 85 100 of the heat sink 85 is shed. In addition, the heat sink 85 is connected in a heat-conducting manner to a conductor track 25 on the substrate 20 via heat-conducting through-contacts 130, 125 and 120 and the heat-conducting contact 135.
Über dem Bauteil 15 ist auf der Wärmesenke 85 und der Wärmeleitklebermasse 90 ein Gehäuse 105 angeordnet. Die freiliegende Oberfläche der Durchkontaktierungen 55 bzw. 120 ist jeweils mit dem Bezugszeichen 40 versehen.A housing 105 is arranged above the component 15 on the heat sink 85 and the heat-conducting adhesive composition 90. The exposed surface of the plated-through holes 55 and 120 is provided with the reference symbol 40.
Die Grundschicht 50 und die Deckschicht 70 der Mehrlagenschaltung bestehen vorzugsweise aus Polyimid. Die nicht von Leiterbahnen 65 besetzten Teile der Mittelschicht 60 sind mit Klebstoff ausgefüllt.The base layer 50 and the cover layer 70 of the multilayer circuit are preferably made of polyimide. The parts of the middle layer 60 not occupied by conductor tracks 65 are filled with adhesive.
Es sind auch Module 10 mit mehrlagigen Schaltungen mit mehr als drei Schichten 50, 60 und 70 mit dem erfindungsgemäßen Verfahren herstellbar. Das Gehäuse 105 kann auch zur Kapselung von mehr als einem Bauteil 15 dienen.Modules 10 with multilayer circuits with more than three layers 50, 60 and 70 can also be produced using the method according to the invention. The housing 105 can also serve to encapsulate more than one component 15.
Ausfuhrungsbeispiel 1Example 1
Die Herstellung eines Multichip-Moduls nach dem erfindungsgemäßen Verfahren umfaßt folgende aufeinanderfolgenden Schritte: 1. Es wird eine mehrlagige Schaltung aus festen Polyimidschichten mit Durchkontaktierungen nach dem bekannten Verfahren der vakuumunterstützten Dickschichttechnik hergestellt, wobei die Grund- und Deckschicht außerhalb der Leiterbahnbereiche durch Klebstoff miteinander verbunden sind.The production of a multichip module by the method according to the invention comprises the following successive steps: 1. A multilayer circuit is produced from solid polyimide layers with plated-through holes according to the known method of vacuum-assisted thick-film technology, the base and top layers being connected to one another outside of the conductor track areas by adhesive.
2. Aus einer Aluminium-Platte wird eine Aussparung (100) herausgestanzt, in die das Bauelement (15) hineinpaßt.2. A recess (100) is punched out of an aluminum plate into which the component (15) fits.
3. Die Wärmesenke (85) wird mittels Lot oder Leitkleber (76) , welcher vorzugsweise durch Siebdruck aufgebracht ist, auf die mehrlagige Schaltung (50, 60, 70) geklebt.3. The heat sink (85) is glued to the multilayer circuit (50, 60, 70) by means of solder or conductive adhesive (76), which is preferably applied by screen printing.
4. Die mehrlagige Schaltung wird mit Einfügung von Lot oder Leitkleber (76) mit dem Bauelement bestückt.4. The multilayer circuit is fitted with the component by inserting solder or conductive adhesive (76).
Die Schritte 3. und 4. können auch vertauscht werden. 5. Das Bauelement (15) und die Wärmesenke (85) werden mit einem Wärmeleitkleber (90) vergossen.Steps 3 and 4 can also be interchanged. 5. The component (15) and the heat sink (85) are cast with a thermal adhesive (90).
6. Über dem Wärmeleitkleberverguß (90) wird eine Kappe (105), vorzugsweise aus Kunststoff, angebracht zum mechanischen Schutz der Anordnung und zur besseren Handhabung bei automatischen Folgeprozessen.6. A cap (105), preferably made of plastic, is attached over the heat-conducting adhesive casting (90) for mechanical protection of the arrangement and for better handling in automatic subsequent processes.
7. Auf dem Substrat (20) sind Kupferleiterbahnen (25) mit bekannter Ätztechnik hergestellt. Das Substrat (20) besteht aus einer FR4-Leiterplatte aus mit Glasfasergewebe verstärktem Epoxidharz. 8. Die Leiterbahnen (25) des Substrates (20) werden durch Lot- oder Leitkleber (35) mit den Durchkontaktierungen (55) der Grundschicht (50) der Mehrlageschaltung elektrisch verbunden.7. Copper conductor tracks (25) are produced on the substrate (20) using known etching technology. The substrate (20) consists of an FR4 circuit board made of epoxy resin reinforced with glass fiber fabric. 8. The conductor tracks (25) of the substrate (20) are electrically connected by solder or conductive adhesive (35) to the plated-through holes (55) of the base layer (50) of the multilayer circuit.
Ausführungsbeispiel 2Embodiment 2
Es wird, wie im Ausfuhrungsbeispiel 1 gearbeitet, wobei jedoch eine thermische Durchkontaktierung (VIAS) (120, 125, 130) zwischen Substrat (20) und Wärmesenke (85) eingebaut wird. Ausfuhrungsbeispiel 2The procedure is as in exemplary embodiment 1, but a thermal plated-through hole (VIAS) (120, 125, 130) is installed between the substrate (20) and the heat sink (85). Example 2
Es wird analog Ausführungsbeispiel 1 vorgegangen, jedoch eine flexible biegsame Folie aus Polyimid für das Substrat (20) eingesetzt.The procedure is analogous to that of embodiment 1, but a flexible, flexible polyimide film is used for the substrate (20).
Ausfuhrungsbeispiel 4Exemplary embodiment 4
Ein Multichip-Modul wird in Epoxidharz eingegossen, nachdem es gemäß Ausführungsbeispiel 1 hergestellt wurde.A multichip module is cast in epoxy resin after it has been produced in accordance with exemplary embodiment 1.
Ausführungsbeispiel 5Embodiment 5
Der Wärmeleitkleber wird spritzvergossen, wobei eine Form mit Kühlrippen entsteht, die das Gehäuse des Moduls bildet.The thermal adhesive is injection molded, creating a shape with cooling fins that form the housing of the module.
Ausführungsbeispiel 6 Zwischen Schritt 3 und 4 des Ausführungsbeispiels 1 wird oder werden auf die Unterseite der Grundschicht (50) der Mehrlageschaltung Widerstände oder Kondensatoren gedruckt.Embodiment 6 Between steps 3 and 4 of embodiment 1, resistors or capacitors are or are printed on the underside of the base layer (50) of the multilayer circuit.
Ausführungsbeispiel 7 Die Mehrlageschaltung wird mit mehr als drei Schichten hergestellt. Es ist möglich, verschieden dicke Lagen aus Basismaterial einzusetzen. In seltenen Fällen kann es geboten sein, verschiedene Basismaterialien zu verwenden.Embodiment 7 The multilayer circuit is manufactured with more than three layers. It is possible to use layers of base material of different thicknesses. In rare cases, it may be necessary to use different base materials.
Es wurden Multi-Chip-Module mit den in der nachfolgenden Tabelle aufgeführten Materialien und Eigenschaften hergestellt . Multi-chip modules were manufactured with the materials and properties listed in the table below.
Figure imgf000008_0001
Figure imgf000008_0001

Claims

Ansprüche Expectations
1. Flip-Chip-Verfahren zur Herstellung eines Multichip- Modules durch Vereinigung eines Substrates (20) , einer Mehrlagenschaltung (50, 60, 70) , eines Bauelementes (15) und einer Wärmesenke (85) , wobei das Substrat (20) mit Leiterbahn(en) (25) und/oder Anschlüssen, die Mehrlagenschaltung mit Durchkontaktierungen (55, 75), das Bauelement (15) und die Wärmesenke (85) zuerst getrennt herstellt werden, danach die Mehrlagenschaltung auf ihrer dem Bauelement (15) und der Wärmesenke (85) zugewandten1. flip-chip method for producing a multichip module by combining a substrate (20), a multilayer circuit (50, 60, 70), a component (15) and a heat sink (85), the substrate (20) with Conductor (s) (25) and / or connections, the multilayer circuit with vias (55, 75), the component (15) and the heat sink (85) are first produced separately, then the multilayer circuit on the component (15) and the Heat sink (85) facing
Oberfläche mit Lot (76) oder Leitkleber versehen und hierauf zunächst wahlweise das unverpackte mehrpolige Bauelement (15) oder die Wärmesenke (85) aufgebracht werden, wobei das Bauelement (15) mit seinen Kontakten (80) an die Durchkontaktierung(en) (75) der Mehrlagenschaltung angeschlossen ist, anschließend das Bauelement (15) und die Wärmesenke (85) durch einen Wärmeleitkleber thermisch kontaktiert und mit einer Abdeckung (105) versehen werden, und zuletzt die so erhaltene Anordnung mit den Leiterbahnen (25) und/oder Anschlüssen auf der Oberfläche des Substrates (20) mit Hilfe der zugehörigen Kontakte (55) der Grundschicht (50) der Mehrlagenschaltung elektrisch und mechanisch durch Lot (35) oder Leitkleber verbunden wird.Provide the surface with solder (76) or conductive adhesive and then either the unpacked multipole component (15) or the heat sink (85) are applied, the component (15) with its contacts (80) to the through-plating (s) (75) the multilayer circuit is connected, then the component (15) and the heat sink (85) are thermally contacted by a heat-conducting adhesive and provided with a cover (105), and finally the arrangement thus obtained with the conductor tracks (25) and / or connections on the Surface of the substrate (20) with the help of the associated contacts (55) of the base layer (50) of the multilayer circuit is electrically and mechanically connected by solder (35) or conductive adhesive.
2. Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß das Bauelement (15) in einer Aussparung (100) der Wärmesenke (50) angeordnet wird. 2. The method according to claim 1, characterized in that the component (15) in a recess (100) of the heat sink (50) is arranged.
3. Verfahren nach Anspruch 1 oder 2, dadurch gekennzeichnet, daß die vergossene Anordnung aus Bauelement (15) und Wärmesenke (85) durch eine sich an der Wärmesenke (85) abstützende Kunststoff-Kappe (10) geschützt ist.3. The method according to claim 1 or 2, characterized in that the encapsulated arrangement of component (15) and heat sink (85) is protected by a plastic cap (10) supported on the heat sink (85).
4. Verfahren nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß die Mehrlagenschaltung (50, 60, 70) aus Polyimidfolien mit Durchkontaktierungen unter Verwendung vakuumunterstützter Dickschichttechnik hergestellt wird.4. The method according to any one of the preceding claims, characterized in that the multilayer circuit (50, 60, 70) is made of polyimide films with plated-through holes using vacuum-assisted thick-film technology.
5. Verfahren nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß als Wärmesenke (85) eine Aluminiumplatte vorgesehen wird.5. The method according to any one of the preceding claims, characterized in that an aluminum plate is provided as a heat sink (85).
6. Verfahren nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß die Wärmesenke (85) über eine thermische Durchkontaktierung (120, 125, 130) in der Mehrlagenschaltung (50, 60, 70) mit einer Leiterbahn (25) des Substrats (20) verbunden wird. 6. The method according to any one of the preceding claims, characterized in that the heat sink (85) via a thermal via (120, 125, 130) in the multilayer circuit (50, 60, 70) with a conductor track (25) of the substrate (20) is connected.
PCT/DE1996/002218 1995-12-09 1996-11-21 Flip-chip process for producing a multi-chip module WO1997022138A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP09521598A JP2000501885A (en) 1995-12-09 1996-11-21 Flip chip method for manufacturing multi-chip module
EP96945743A EP0865668A2 (en) 1995-12-09 1996-11-21 Flip-chip process for producing a multi-chip module

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DE19546045.6 1995-12-09
DE1995146045 DE19546045C1 (en) 1995-12-09 1995-12-09 Flip-chip method for producing a multichip module

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EP1684341A3 (en) 2005-01-21 2007-01-10 Robert Bosch Gmbh Electric circuit and method of manufacturing an electric circuit

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WO1997022138A3 (en) 1997-07-31
EP0865668A2 (en) 1998-09-23
DE19546045C1 (en) 1997-05-22

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