WO1997022138A3 - Flip-chip process for producing a multi-chip module - Google Patents

Flip-chip process for producing a multi-chip module Download PDF

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Publication number
WO1997022138A3
WO1997022138A3 PCT/DE1996/002218 DE9602218W WO9722138A3 WO 1997022138 A3 WO1997022138 A3 WO 1997022138A3 DE 9602218 W DE9602218 W DE 9602218W WO 9722138 A3 WO9722138 A3 WO 9722138A3
Authority
WO
WIPO (PCT)
Prior art keywords
chip
flip
component
producing
heat sink
Prior art date
Application number
PCT/DE1996/002218
Other languages
German (de)
French (fr)
Other versions
WO1997022138A2 (en
Inventor
Ralf Haug
Original Assignee
Bosch Gmbh Robert
Ralf Haug
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bosch Gmbh Robert, Ralf Haug filed Critical Bosch Gmbh Robert
Priority to JP09521598A priority Critical patent/JP2000501885A/en
Priority to EP96945743A priority patent/EP0865668A2/en
Publication of WO1997022138A2 publication Critical patent/WO1997022138A2/en
Publication of WO1997022138A3 publication Critical patent/WO1997022138A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Abstract

The proposal is for a flip-chip process for producing a multi-chip module, in which a substrate (20), a multi-layer circuit (50, 60, 70), a component (15) and a heat sink (85) are combined according to the invention in such a way that solder or conductive adhesive is applied to the surface of the multi-layer circuit, e.g. by screen printing. It is now possible, as desired, to apply first a component (15) or a heat sink (85) thereon, whereupon the component and the heat sink are coated with a heat conducting adhesive and brought into thermal contact. This arrangement is covered by a plastic cap before being soldered or adhesively secured to a substrate with printed circuit tracks.
PCT/DE1996/002218 1995-12-09 1996-11-21 Flip-chip process for producing a multi-chip module WO1997022138A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP09521598A JP2000501885A (en) 1995-12-09 1996-11-21 Flip chip method for manufacturing multi-chip module
EP96945743A EP0865668A2 (en) 1995-12-09 1996-11-21 Flip-chip process for producing a multi-chip module

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE1995146045 DE19546045C1 (en) 1995-12-09 1995-12-09 Flip-chip method for producing a multichip module
DE19546045.6 1995-12-09

Publications (2)

Publication Number Publication Date
WO1997022138A2 WO1997022138A2 (en) 1997-06-19
WO1997022138A3 true WO1997022138A3 (en) 1997-07-31

Family

ID=7779701

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1996/002218 WO1997022138A2 (en) 1995-12-09 1996-11-21 Flip-chip process for producing a multi-chip module

Country Status (4)

Country Link
EP (1) EP0865668A2 (en)
JP (1) JP2000501885A (en)
DE (1) DE19546045C1 (en)
WO (1) WO1997022138A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19912441A1 (en) * 1999-03-19 2000-09-21 Elfo Ag Sachseln Sachseln Multi-chip module
EP1684341A3 (en) 2005-01-21 2007-01-10 Robert Bosch Gmbh Electric circuit and method of manufacturing an electric circuit

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5090609A (en) * 1989-04-28 1992-02-25 Hitachi, Ltd. Method of bonding metals, and method and apparatus for producing semiconductor integrated circuit device using said method of bonding metals
WO1994027318A1 (en) * 1993-05-11 1994-11-24 Micromodule Systems Packaging and interconnect system for integrated circuits
US5375042A (en) * 1990-11-30 1994-12-20 Hitachi, Ltd. Semiconductor package employing substrate assembly having a pair of thin film circuits disposed one on each of oppositely facing surfaces of a thick film circuit
US5397921A (en) * 1993-09-03 1995-03-14 Advanced Semiconductor Assembly Technology Tab grid array
EP0685878A2 (en) * 1994-04-28 1995-12-06 Fujitsu Limited Semiconductor package and method of forming the same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5155661A (en) * 1991-05-15 1992-10-13 Hewlett-Packard Company Aluminum nitride multi-chip module
JPH0758254A (en) * 1993-08-19 1995-03-03 Fujitsu Ltd Multichip module and manufacture thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5090609A (en) * 1989-04-28 1992-02-25 Hitachi, Ltd. Method of bonding metals, and method and apparatus for producing semiconductor integrated circuit device using said method of bonding metals
US5375042A (en) * 1990-11-30 1994-12-20 Hitachi, Ltd. Semiconductor package employing substrate assembly having a pair of thin film circuits disposed one on each of oppositely facing surfaces of a thick film circuit
WO1994027318A1 (en) * 1993-05-11 1994-11-24 Micromodule Systems Packaging and interconnect system for integrated circuits
US5397921A (en) * 1993-09-03 1995-03-14 Advanced Semiconductor Assembly Technology Tab grid array
EP0685878A2 (en) * 1994-04-28 1995-12-06 Fujitsu Limited Semiconductor package and method of forming the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
NICOLAS G ET AL: "EVOLUTION DES TECHNOLOGIES D'ONTERCONNEXION ET D'ENCAPSULATION DES COMPOSANTS ELECTRONIQUES EVOLUTION OF INTERCONNECT AND PACKAGING TECHNOLOGIES IN ELECTRONIC COMPONENTS", L'ONDE ELECTRIQUE, vol. 73, no. 6, 1 November 1993 (1993-11-01), pages 48 - 54, XP000412768 *

Also Published As

Publication number Publication date
EP0865668A2 (en) 1998-09-23
JP2000501885A (en) 2000-02-15
DE19546045C1 (en) 1997-05-22
WO1997022138A2 (en) 1997-06-19

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