WO1997029432A1

WO1997029432A1 - Apparatus for programmably defining the access latency

Info

Publication number: WO1997029432A1
Application number: PCT/US1997/001410
Authority: WO
Inventors: Zohar Bogin; David C. Smyth; Kuljit S. Bains; Nilesh V. Shah
Original assignee: Intel Corporation
Priority date: 1996-02-09
Filing date: 1997-02-07
Publication date: 1997-08-14
Also published as: AU1845597A; TW445414B

Abstract

An arbitration (15) unit is coupled to the plurality of components that accepts and grants requests for the control of the shared memory (14). A latency unit (27) coupled to the arbitration unit is programmable to set a latency that determines when the arbitration unit grants a request relative to when the arbitration unit received the request.

Description

APPARATUS FOR PROGRAMMABLY DEFINING THE ACCESS LATENCY

HELD OF THE INVENTION

The invention generally relates to computer systems and more particularly to a computer system that employs a memory controller and a graphics controller.

RELATED APPLICATIONS

The present application is related to commonly-owned U.S. Patent Application Serial No. 08/516,495, entitled "Method and Apparatus for Arbitrating Access Requests to a Shared Computer System Memory by a Graphics Controller and a Memory Controller, " filed August 17, 1995, which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

Many computer systems include a microprocessor, a memory controller, and a graphics controller wherein the memory controller controls access by the microprocessor to system memory, and the graphics controller controls display of data provided by the microprocessor onto a display screen using a frame buffer. Both the system memory and the frame buffer are typically implemented using arrays of dynamic random access memory (DRAM). In such systems, the memory controller cannot directly access the frame buffer, and the graphics controller cannot directly access the system memory.

Certain disadvantages arise from providing a frame buffer which is separate from system memory. For example, if all or a portion of a frame buffer is not in use, it would be desirable to allow unused portions of the frame buffer memory to be employed as system memory. Such efficiency cannot easily be achieved with a separate frame buffer controlled by a graphics controller.

One sύiUtϊcn to tne lOreg ing prouiem is to provide n array of DRAM accessible to both the memory controller and the graphics controller wherein the associated memory space of the DRAM array is partitioned between system memory and frame buffer memory. In such a system, the memory controller has access to all of the shared memory including that portion used as a frame buffer. Accordingly, if a frame buffer is not required, the memory controller may access the frame buffer portion of memory for use as system memory.

As the DRAM array is shared by the memory controller and the graphics controller, an arbitration mechanism is required to ensure fair and efficient access to the DRAM array by both the memory controller and the graphics controller. To improve system efficiency and to enable the concurrent operation of system components while the graphics controller accesses the DRAM array, it is important for the arbitration protocol to be sensitive to the respective latency and bandwidth requirements of the memory controller and the graphics controller, as well as to the speed of the DRAM array. In other words, the arbitration mechanism should be designed to allow sufficient time for the memory controller or graphics controller to complete memory operations prior to transferring control of the DRAM array to the other component.

For example, the graphics controller may be performing a screen refresh operation when the memory controller requests access to the DRAM array to perform a read operation, and the arbitration mechanism should be designed to ensure sufficient time for the screen refresh operation to complete before transferring control of the DRAM array to the memory controller. Similarly, the memory controller may include a set of prefetch buffers that provide a burst read capability. To ensure that a burst read may be performed, the transfer from memory to the memory controller should not be terminated before the prefetch buffers are completely filled. SUMMARY AND OBTECTS OF THE INVENTION

Therefore, it is an object of the invention to provide a mechanism that improves system efficiency for a system wherein a graphics controller and a memory controller share a single memory space, and for any other system that includes a shared resource alternately controlled by a plurality of components.

This and other objects of the invention are provided in a system that comprises a plurality of components and a shared resource coupled to the plurality of components. An arbitration unit is coupled to the plurality of components that accepts and grants requests for control of the shared resource received from the plurality of components. A latency unit coupled to the arbitration unit is programmable to set a latency that determines when the arbitration unit grants a request relative to when the arbitration unit received the request. According to one embodiment, the system is a shared memory system wherein a memory is used as system memory by a memory controller and as a frame buffer by a graphics controller. The latency unit is programmable to set a different latency for granting requests depending on the memory operation that is being performed when a request is received. In this manner, memory operations are provided sufficient time to complete, and system efficiency is improved.

Other objects, features, and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which:

FIGURE 1 shows a computer system that includes a latency unit that operates according to one embodiment.

FIGURE 2 shows a latency unit of one embodiment.

FIGURE 3 shows a computer system that operates according to an alternative embodiment.

FIGURE 4 is a flow chart showing operation of the computer system FIGURE 3 when the memory controller is performing a read operation.

FIGURE 5 is a flow chart showing operation of the computer system FIGURE 3 when the memory controller is performing a write operation.

DETAILED DESCRIPTION

A method and mechanism for tuning the access latency of a shared memory system is described wherein the efficiency of the shared memory system is increased and concurrency of operation is provided. More specifically, a programmable latency unit is provided to allow the user or manufacturer to define the maximum allowable amount of latency or delay time (hereafter "access latency") when transferring control of the shared memory from the memory controller to the graphics controller, and vice versa. The latency unit may be used to set the access latency in view of 1) the speed of the shared memory, 2) the respective bandwidth requirements of the memory controller and the graphics controller, and 3) the operation being performed by the controlling component when an access request is received. Latency units may be used in any system wherein a common resource is shared by a plurality of system components.

According to one embodiment, the latency unit comprises one or more programmable latency timers, the output of which is used by an arbi Ira lion unit or drbtter to determine a maximum amount of time for which transfer of control of the shared memory may be delayed once requested. A separate latency timer may be provided for each type of operation performed by the memory controller and the graphics controller such that the maximum latency for transferring control between components is determined by the operation being performed by the controlling component when a request is received.

Additional efficiency is gained by providing the components of the shared memory system with a mechanism for transferring control to the requesting component before the maximum amount of delay time has expired should the controlling component complete its operation early or other predetermined conditions occur. For example, according to one embodiment, the memory controller includes read buffers that store multiple units of data retrieved (or ^"preferched") from system memory for rapid transfer to components of a peripheral bus. The access latency for a prefetch operation is selected to allow the memory controller sufficient time to fill the read buffers if the read buffers are empty. If the read buffers are not empty, the maximum amount of access latency allowed is not required to fill the buffers, and the memory would be idle for the excess amount of time allowed if a mechanism for transferring control early were not provided.

Accordingly, the memory controller of one embodiment is provided with a mechanism for indicating early completion of the prefetch operation such that control of the shared memory may be granted to the graphics controller early. Data may then be transferred from the read buffers to the system component while the graphics controller concurrently accesses the shared memory. Similar functionality may be provided for performing the transfer of accumulated or "posted" write data stored in write buffers to the memory.

System Overview

Figure 1 shows a computer system 10 having, as its principal components, a processor 12, shared memory 14, a memory controller 16, and a graphics controller 18. The memory controller 16 and the graphics controller 18 are shown as being coupled to receive a common clock signal CLK. A portion of shared memory 14 is dedicated as a frame buffer 20. Remaining portions of shared memory 14 are dedicated as system memory 21. The memory controller 16 accesses memory 14 based upon commands received from the processor 12 via host bus 13 and from one or more peripheral devices, such as peripheral device 22 connected to the memory controller through a peripheral bus 24. The peripheral bus 24 may operate according to the Peripheral Components Interconnect (PCI) Local Bus Specification, revision 2.1 published June 1, 1995.

The memory controller 16 may read data from, and write data to, shared memory 14. For some operations, such as a DRAM refresh, the memory controller requires access to all portions of memory 14. For other operations the memory controller 16 accesses only the system memory portion 21 of shared memory 14. For still other operations, the memory controller 16 accesses the frame buffer portion 20 of shared memory 14. According to the present embodiment, memory controller 16 is part of a bus bridge (not shown) that also provides a data path between host bus 13 and peripheral bus 24.

The graphics controller 18 accesses the frame buffer portion 20 of shared memory 14 to store graphics data therein for ultimate display on a display device 23 which is coupled to peripheral bus 24. Graphics data, or commands relevant thereto, are received through the peripheral bus 24. The graphics commands may originate from, for example, the processor 12 or from "clients" on the peripheral bus 24. Both the memory controller 16 and the graphics controller 18 access shared memory 14 through a memory bus 25, which is shown as a common interconnect to simpiity discussion. The memory controller 16 and the graphics controller 18 may, in fact, access the shared memory 14 using different data paths. For example, according to one embodiment, the host bus 13 and the graphics controller 18 are coupled to the memory bus 25, and memory controller 16 accesses shared memory 14 by way of the host bus 13 and the memory bus 25 wherein graphics controller 18 accesses shared memory 14 directly through the memory bus 25.

The Arbitration Unit

An arbitration unit 26 is provided for coordinating access to the memory by the memory controller 16 and the graphics controller 18. More specifically, the arbitration unit 26 receives access requests from both the memory controller 16 and the graphics controller 18, determines the relative priority of the access requests, and then grants access to one device or the other depending upon the relative priorities. According to the present embodiment, the memory controller 16 is granted default control of the memory bus 25 to access the shared memory 14.

In Figure 1, the arbitration unit 26 is shown as a separate component from the memory controller-! 6 and the graphics controller 18. The arbitration unit 26 is coupled to the graphics controller 18 by a GC request line 28 and a GC grant line 30 and to the memory controller 16 by an MC request line 29 and an MC grant line 31. The arbitration unit receives access request information along the respective request lines and transmits grant information along the respective grant lines in accordance with any reasonable signaling protocol. The arbitration unit 26 is also shown as being coupled to the CLK signal. The arbitration unit 26 may alternatively be included in one or the other of the memory controller 16 and the graphics controller 18.

According to the present embodiment, the respective request lines are used to signal the type of operation being requested, and the access requests are prioritized based on the type of access requested. For example, the arbitration unit may prioritize usage requests as follows, with number (1) being highest priority: 1. High priority graphics controller request, such as a request specifying a screen refresh operation when a screen refresh FIFO 34 is starved.

2. A high priority memory controller request specifying a DRAM refresh operation to be performed by a DRAM refresh unit 36.

3. Memory controller request specifying non-DRAM refresh operations, such as memory operation requests received from either the processor 12 or peripheral devices.

4. Low priority graphics controller request specifying any graphics controller operation other than a screen refresh when the refresh FIFO is starved. Examples include a draw operation performed by a draw engine 38 or a screen refresh operation when the screen refresh FIFO is not starved.

5. A low priority memory controller operations specifying a low priority DRAM refresh operation.

The arbitration unit 26 grants access to the shared memory 14 based upon the relative priority of competing requests received from the memory controller and the graphics controller. By granting access to the shared memory 14, it is meant that the arbitration unit 26 grants control of the common memory bus 25.

The Latency Unit

A programmable latency unit 27 is provided to specify the maximum allowable amount of time, which may be expressed in terms of periods of the CLK signal (i.e. "clock cycles"), between when a high priority access request is received from the graphics controller 18 and when the control of the shared memory by the memory controller 16 may be revoked by the arbitration unit 26. When an access request is received the arbitration unit 26 causes latency unit 27 to track the amount of time that has ela e and to indicate when the maximum allowable amount of time has expired, whereupon the arbitration unit 26 revokes control of the memory controller 16 and grants access to the graphics controller. The time elapsed may be tracked, for example, by incrementing or decrementing a counter. For alternative embodiments, the latency unit 27 may be used to specify the maximum access latency regardless of which component is controlling the shared memory, which component is requesting access to the shared memory, and the priority of the request.

According to the present embodiment, the latency is determined in part by the operation being performed by the component that controls the shared memory when an access request is received. Information regarding the operation that is being performed by a component may be maintained by the arbitration unit 26 wherein the components deliver such information by encoding the information using the respective request lines or by way of additional signal lines that are not shown in Figure 1. Alternatively, additional signal lines (not shown) may be routed from the components to the latency unit 27 to select the appropriate latency in view of the operation being performed by the controlling component.

Defining the maximum access latency in view of the operation being performed by the controlling component helps to ensure that the operation being performed when a request is received progresses sufficiently before granting the request to the requesting component. For example, memory controller 16 includes read buffers 40 for storing data prefetched from the system memory 21 and write buffers 42 for posting data for transfer to the system memory 21. To ensure that the read buffers 40 may be filled to a predetermined threshold (i.e., "full") during a prefetch operation, the maximum access latency for a prefetch operation is determined in view of the number of clock cycles it would take to fill read buffers 40 with data if read buffers 40 were empty. Similarly, the maximum access latency for a posted write operation to memory is determined in view of the number of clock cycles it would take to empty the write buffers 42 to a first threshold (i.e., ^" empty ) if the write Duffers 42 were filled to a second higher threshold (i.e., "full"). It is possible that an access request will be received after an operation of the controlling component is already underway. Therefore, the maximum amount of time allowed to complete an operation may not be required. To use the resources of shared memory 14 more efficiently, the components are provided with mechanisms for indicating early completion of operations such that the arbitration unit 26 may grant access to the requesting component before the maximum allowable time has elapsed.

For example, memory controller 16 is shown as including a flag 43 that may be set when read buffers 40 are full and memory controller 16 is performing a prefetch operation, when write buffers 42 are empty and memory controller 16 is performing a posted write operation, or when refresh unit 36 completes a refresh operation of shared memory 14. The flag 43 may also be set whenever a single cycle write or read operation is performed successfully. If the flag 43 is set, the arbitration unit 26 transfers access to the shared memory to the graphics controller 18. The flag 43 is reset when memory controller 16 is again granted ^c es o the shareσr memory 14. The flag 43 may be set and reset using logic circuitry (not shown) that monitors the state of the functional units of the memory controller 16, and alternative mechanisms for indicating early transfer may be used.

Providing the early transfer of access to shared memory 14 between components increases the efficiency of the system because shared memory 14 will typically be idle for fewer clock cycles. Additionally, for the case of prefetch operations, the data stored in read buffers 40 may be transferred to the appropriate system component before the end of the maximum allowed time and concurrently with the graphics controller 18 accessing the shared memory 14. For the case of posted write operations, emptying the write buffers 42 better ensures that components on the peripheral bus 24 and the processor 12 may post a maximum amount of data for future write operations while the grap ics controller 18 concurrently accesses the shared memory 14. Figure 2 shows the latency unit 27 of one embodiment as including a plurality of distinct programmable latency timers for each possible operation that may be performed. Each latency timer outputs a pulse having a programmable duration, and a latency timer is started in response to receiving a trigger signal 75. According to the present embodiment, trigger signals are asserted by the arbitration unit 26 in response to receiving an access request to start the selected latency timer. A latency timer may alternatively comprise a counter that is incremented or decremented and that asserts a signal when a predetermined value in the count is reached. Depending on the specific implementation, a trigger signal may specify the start of only the desired latency timer, or a trigger signal may specify the start of all latency timers, whereupon the arbitration unit 26 only monitors the output of the desired latency timer.

According to an alternative embodiment, a single latency timer is provided, and the duration of the output pulse is adjusted in response to the operation being performed using user programmed values. According to another alternative eιτrbσdiment, a cycle counting scheme may be used wherein the arbitration unit counts the number of clock cycles (clock periods) that have elapsed since receiving the request, and the maximum number of clock cycles is programmable and varied based on the operation being performed when the request is received. Regardless of the specific embodiment, a configuration circuit 65 is provided to program the latency unit 27 using information received from a user interface 70. The configuration circuit 65 may include a configuration register (not shown) that is addressable and accessible via the host bus 13 when coupled to user interface 70.

As shown, read latency timer 50 is provided to specify the latency for transferring control to the graphics controller 18 when the memory controller 16 is performing a read operation. The read latency timer 50 outputs a pulse having a duration of TMCGCR that is specified in terms of the number of periods of the CLK signal required to complete a memory read operation. The user specifies the number of clock periods by writing a value to configuration circuit 65 via user interface 70. For the system of Figure 1, wherein the memory controller 16 includes prefetch buffers 40 to store prefetched data, the user may select TMCGCR to be a number of clock cycles sufficient to ensure adequate filling of prefetch buffers 40.

Similarly, write latency timer 55 is provided to specify the latency for transferring control to the graphics controller 18 when the memory controller 16 is performing a write operation, and the write latency timer 55 outputs a pulse having a duration of TMCGCW that is specified in terms of the number of periods of the CLK signal required to complete a memory write operation. The user specifies the number of clock periods by writing a value to configuration circuit 65 via user interface 70. For the system of Figure 1, wherein the memory controller 16 includes write buffers for posting (accumulating) data for memory write operations, the user may select TMCGCW ^to t>^{e a} number of clock cycles sufficient to allow the emptying of write buffers 42.

The embodiments discusses thus^~far have assumed that the latency timer is triggered in response to receiving a request. Alternatively, a latency timer may be triggered when the controlling components begins performing an operation. When the allowable time has expired, the controlling component determines whether there is an outstanding request. If there is an outstanding request, the controlling component transfers control to the requesting component or indicates to the arbitration unit that access may be transferred. If there is no outstanding request, the controlling component resets the latency timer. According to another alternative embodiment, the maximum allowable time set by the latency timer is based on the needs of the requesting component and specifies when the requesting component can forcibly take control of the shared resource, and the latency timer is triggered when the request is made. If the controlling component does not relinquish control before the maximum allowable time has elapsed, the requesting component is provided with a mechanism for taking control of the shared resource. Specific Exemplary Embodiment

Figure 3 shows a specific exemplary embodiment wherein the memory controller includes an arbitration unit. Specifically, computer system 100 is shown as comprising a bus bridge 105 that includes a data path unit 110 and a memory controller 115. The data path unit 110 of bus bridge 105 provides for the bridging of data between a host bus 120 and a peripheral bus 125. Memory controller 115, which includes write buffers 140, read buffers 145, refresh unit 150, and an MC arbiter 155, is shown as being coupled to memory bus 130 to perform memory operations on a shared memory (not shown). MC arbiter 155 is shown as including latency timers 160. The operation of the data path unit 110 and the memory controller 115 is determined by data stored in configuration registers 135, which are programmed via either the host bus 120 or the peripheral bus 125 using any reasonable method.

The computer system 100 further includes a graphics controller 175 coupled to the peripheral bus 125, to the memory bus 130, and to the MC arbiter 155 of the memory controiier 115 via a request line 165 and a grant line 170. Graphics controller 175 includes a GC arbiter 180 having a programmable latency timer 185 that is programmed by data stored in the configuration registers 190. The graphics controller 175 may include an alternative mechanism for tuning the access latency.

According to the present embodiment, the data path between the memory controller and the shared memory is provided by way of host bus 120 and a data path circuit (not shown) that interfaces the host bus 120 and the data path portion of memory bus 130. The graphics controller 175 is coupled directly to the data path of memory bus 130, and both the memory controller 115 and the graphics controller are coupled to the address and control portions of memory bus 130.

As shown, only two signal lines are provided between the memory controiier 115 and the graphics controller 175, and the MC arbiter 155 and the GC arbiter 190 implement a two-line signaling protocol such as that described in commonly-owned U.S. Patent Application Serial No. 08/516,495, entitled "Method and Apparatus for Arbitrating Access Requests to a Shared Computer System Memory By A Graphics Controller and a Memory Controller," filed August 17, 1995. Alternative signaling protocols may be used.

According to the embodiment of Figure 3, memory controller 115 is the default "owner" or controller of the shared memory, and MC arbiter 155 performs essentially all of the functions previously described with respect to arbitration unit 26 of Figure 1. As MC arbiter 155 and the programmable latency timers 160 are located on the same semiconductor die or within the same multi-chip module as memory controller 115, MC arbiter 155 may be informed of the states of the write buffers 140, the read buffers 145, and the refresh unit 150 by using internal signal paths, and no external pins need to be provided to perform such a function.

Figure 4 is a flow chart showing the operation of computer system 100 when memory controller performs a read operation to fill read buffers 145 with data from the system memory portion of the shared memory. At process block 405, which may occur when computer system 100 is initialized, the read latency is set to a value TR, which is equal to a number of cycles of the CLK signal. At process block 410, the memory controller 115 begins a read access to fill read buffers 1405. At process block 415, the graphics controller 175 asserts a high priority request which is received by MC arbiter 155. The receipt of the high priority request causes MC arbiter 155 to trigger latency timer 160 at process block 420. According to the present embodiment, latency timer 160 is a counter that is incremented each clock cycle, and latency timer is initialized to a value of zero (T = 0). The latency timer is incremented once each clock cycle at process block 425. If the read operation has completed or read buffers 145 are full at process block 430, the MC arbiter 155 grants access to the shared memory to the graphics controller at process block 440. Otherwise, the MC arbiter 155 determines at process block 435 whether the maximum allowable time has elapsed (T = TR). If the maximum allowable time has elapsed, process block 440 is performed. Otherwise, process blocks 430 and 435 are repeated until a condition occurs that cause process block 440 to be performed. At process block 445, the memory controller 115 may transfer data from the read buffers while the graphics controller concurrently transfers data from the memory.

Figure 5 is a flow chart showing the operation of computer system 100 when memory controller performs a write operation to empty the data stored in write buffers 140 to the system memory portion of the shared memory. At process block 505, which may occur when computer system 100 is initialized, the write latency is set to a value TW which is equal to a number of cycles of the CLK signal. At process block 510, the memory controller 115 begins a write access to empty write buffers 140. At process block 515, the graphics controller 175 asserts a high priority request which is received by MC arbiter 155. The receipt of the high priority request causes MC arbiter 155 to trigger latency timer 160 at process block 520. According to the present embodiment, latency timer 160 is a counter that is incremented each clock cycle, and latency timer is initialized to a value of zero (T = 0). The latency timer is incremented once each clock cycle at process block 525. If the write operation has completed or write buffers 140 are empty at process block 530, the MC arbiter 155 grants access to the shared memory to the graphics controller at process block 540. Otherwise, the MC arbiter 155 determines at process block 535 whether the maximum allowable time has elapsed (T = Ty/)- If the maximum allowable time has elapsed, process block 540 is performed. Otherwise, process blocks 530 and 535 are repeated until a condition occurs that cause process block 540 to be performed.

In the foregoing specification the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than restrictive sense.

Claims

CLAIMSWhat is claimed is:

1. A system comprising: a plurality of components; a shared resource coupled to the plurality of components; an arbitration unit coupled to the plurality of components that accepts and grants requests for control of the shared resource received from the plurality of components; and a latency unit coupled to the arbitration unit that is programmable to set a latency that determines when the arbitration unit grants a request relative to when the arbitration unit receives the request.

2. The system of claim 1 wherein the latency unit provides a different latency for each of the plurality of components.

3. The system of claim 1 wherein at least one of the plurality of components is capable of making requests for a plurality of different operations using the shared resource, the latency unit providing a different latency for each of the plurality of different operations that may be requested by the first component.

4. The system of claim 1 wherein the latency defines a maximum allowable time between receiving the request and granting the request, at least one of the plurality of components including a mechanism for indicating to the arbitration unit that the arbitration unit may grant a request before the maximum allowable time has elapsed.

5. A computer system comprising: a memory controller; a graphics controller; a memory coupled to the memory controller and the graphics controller, the memory being partitioned into a frame buffer portion for use by the graphics controller and a system memory portion for use by the memory controller; an arbitration unit coupled to the memory controller and the graphics controller; and a latency unit coupled to the arbitration unit that is programmable to set a latency that determines when the arbitration unit grants a request relative to when the arbitration unit receives the request.

6. The computer system of claim 5 wherein the latency unit provides different maximum times for the memory controller and the graphics controller.

7. The computer system of claim 5 wherein the latency unit provides a first latency for when the graphics controller requests access to the memory and the memory controller is performing a read operation and a second latency for when the graphics controller requests access to the memory and the memory controller is performing a write operation.

8. The computer system of claim 5 wherein the memory controller includes the arbitration unit and the latency unit.

9. The computer system of claim 5 wherein the latency defines a maximum allowable time between receiving the request and granting the request, the memory controller including a mechanism for indicating to the arbitration unit that the arbitration unit may grant a request before the maximum allowable time has elapsed.

10. A memory controller that shares control of a memory with a graphics controller, the memory controller comprising: an arbiter for coupling to the graphics controller to receive requests for control of the memory from the graphics controller; and a latency unit coupled to the arbiter that is programmable to set a latency that determines when the arbiter grants a request relative to when the arbiter receives the request.

11. The memory controller of claim 10 wherein the latency unit is programmable to set a first latency that is used when the memory controller is performing a read operation and a second latency that is used when the memory controller is performing a write operation.

12. The memory controller of claim 11 wherein the latency unit comprises a first latency timer that is programmable to set the first latency and a second latency timer that is programmable to set the second latency.

13. The computer system of claim 10 wherein the latency defines a maximum allowable time between receiving the request and granting the request, the memory controller including a mechanism that indicates to the arbiter that the arbiter may grant a request before the maximum allowable time has elapsed if the memory controller completes a pending operation before the maximum allowable time has elapsed.

14. A method for efficiently controlling access to a shared memory by a memory controller and a graphics controller, comprising: setting an access latency that defines a maximum allowable time between when an request to access the shared memory is received and when the request will be granted; the memory controller being granted access to the shared memory to perform an operation; initializing an access timer in response to the graphics controller requesting to access the shared memory; and granting access to the graphics controller if the timer detects that the maximum allowable time has elapsed.

15. The method of claim 14, further comprising: granting access to the graphics controller before the maximum allowable time has elapsed if the memory controller indicates that the operation has completed.

16. The mthod of claim 14 wherein the operation is a read operation that has filled read buffers of the memory controller, the memory controller transferring data from the read buffers while the graphics controller concurrently accesses the shared memory.