WO1997030453A1 - Auto refresh to specified bank - Google Patents
Auto refresh to specified bank Download PDFInfo
- Publication number
- WO1997030453A1 WO1997030453A1 PCT/US1997/002652 US9702652W WO9730453A1 WO 1997030453 A1 WO1997030453 A1 WO 1997030453A1 US 9702652 W US9702652 W US 9702652W WO 9730453 A1 WO9730453 A1 WO 9730453A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- bank
- specified
- command
- bank memory
- ofthe
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
Definitions
- the present invention relates to semiconductor memory integrated circuits and, more particularly to synchronous random access memories such as synchronous dynamic random access memories and synchronous graphic random access memories.
- Synchronous random access memories such as a synchronous dynamic random access memories (SDRAMs) and a synchronous graphic random access memories (SGRAMs) are designed to operate in a synchronous memory system.
- SDRAMs synchronous dynamic random access memories
- SGRAMs synchronous graphic random access memories
- SDRAMs offer substantial advances in dynamic memory operating performance. For example, some SDRAMs are capable of synchronously providing burst data in a burst mode at a high-speed data rate by automatically generating a column address to address a memory array of storage cells organized in rows and columns for storing data within the SDRAM. In addition, if the SDRAM includes two or more banks of memory arrays, the SDRAM preferably permits interleaving between the two or more banks to hide precharging time. SGRAMs differ from SDRAMs by providing certain column block write functions and masked write or write-per-bit functions to accommodate high-performance graphics applications
- asynchronous DRAM In an asynchronous DRAM, once row and column addresses are issued to the DRAM and a row address strobe signal and column address strobe signal are deactivated, the DRAM's memory is precharged and available for another access. Another row cannot be accessed in the DRAM array, however, until the previous row access is completed.
- a SDRAM requires separate commands for accessing and precharging a row of storage cells in the SDRAM memory array.
- a transfer operation involves performing a PRECHARGE command operation to deactivate and precharge a previously accessed bank memory array, performing an ACTIVE command operation to register the row address and activate the bank memory array to be accessed in the transfer operation, and performing the transfer READ or WRITE command to register the column address and initiate a burst cycle.
- an AUTO REFRESH command is needed each time a refresh is required.
- all bank memory arrays in multi- bank memory devices are idle. Furthermore, the user of the SDRAM or SGRAM device does not know which bank is being refreshed.
- Prior ait SDRAM or SGRAMs typically perform auto refresh operations by toggling between the two banks during each count ofthe row address. For example, the auto refresh operation is performed by refreshing row 0 of bank 0, then prior to incrementing the row address, the banks are switched to refresh row 0 of bank 1.
- the row address that is internally generated during the auto refresh operation is then incremented to row 1 and the banks are switched so that row 1 of bank 0 is refreshed, then the banks are switched to refresh row 1 of bank 1. This alternating between banks is continued until all rows in all banks ofthe memory device are refreshed.
- the present invention provides a memory device responsive to command signals and operating in synchronization with active edges of a system clock.
- the memory device includes multiple bank memory arrays. Each bank memory array includes storage cells.
- a command decoder/controller responds to selected command signals to initiate, at a first active edge ofthe system clock, an auto refresh command controlling an auto refresh operation to a specified one of the multiple bank memory arrays.
- the memory device is also responsive to a bank address signal.
- the memory device further comprises a refresh controller circuit specifying the specified one of the multiple bank memory arrays based on the bank address signal received at the first active edge of the system clock.
- the specified one ofthe multiple bank memory arrays is predetermined prior to performing the auto refresh command initiated at the first active edge ofthe system clock.
- the one ofthe multiple bank memory arrays is predetermined in one embodiment ofthe present invention based on which bank memory array is initially refreshed and a subsequent known order of refreshing the bank memory arrays.
- the command decoder/controller is preferably responsive to selected command signals to initiate during the auto refresh operation to the specified bank memory array a second command controlling a second operation, which is not an auto refresh operation, to a second bank memory array ofthe multiple bank memory arrays, which is not the specified bank memory array.
- One embodiment ofthe memory device ofthe present invention includes a refresh counter having a separate counter portion for each ofthe multiple bank memory arrays for incrementing an address of a row to be refreshed.
- the memory device is a synchronous dynamic random access memory (SDRAM). In another preferred embodiment of the present invention, the memory device is a synchronous graphic random access memory (SGRAM). Because the bank memory array in which the auto refresh operation is performed is specified, the user ofthe memory device according to the present invention can perform commands to the bank memory array which is not being refreshed during the auto refresh operation. For example, a transfer operation such as a read from or a write to one bank memory array can be performed when another bank memory array is being auto refreshed.
- SDRAM synchronous dynamic random access memory
- SGRAM synchronous graphic random access memory
- Figure 1 is a block diagram of a SDRAM according to the present invention.
- Figure 2 is a timing diagram illustrating an auto refresh operation performed in a bank specified by an incoming bank address signal in the SDRAM of Figure 1 during auto refresh mode.
- FIG. 3 is a block diagram of a refresh counter employed in one embodiment ofthe SDRAM of Figure 1.
- Figure 4 is a timing diagram illustrating an auto refresh operation performed in a predetermined specified bank in the SDRAM of Figure 1 during auto refresh mode.
- Figure 5 is a timing diagram illustrating an auto refresh operation starting at a predetermined specified bank in the SDRAM of Figure 1 during initialization and loading of a mode register.
- Figure 6 is a timing diagram illustrating an auto refresh operation performed in a bank 0 as specified by an incoming bank address signal and an active operation followed by a read operation in a bank 1 ofthe SDRAM of Figure 1.
- SDRAM synchronous dynamic random access memory
- FIG. 1 A synchronous dynamic random access memory (SDRAM) according to the present invention is illustrated generally at 20 in Figure 1 in block diagram form.
- SDRAM 20 Much of the circuitry of SDRAM 20 is similar to circuitry in known SDRAMs, such as the Micron Technology, Inc. MT48LC4M4R1 S 4 MEG X 4 SDRAM, which is described in detail in the corresponding Micron Technology, Inc. Functional Specification.
- the present invention is not limited to SDRAMs, as the present invention is equally applied to other synchronous random access memories devices such as a synchronous graphics random access memory (SGRAM).
- SGRAM synchronous graphics random access memory
- the operation of a SGRAM according to the present invention is similar to the operation of a SDRAM.
- a SGRAM is not illustrated in the drawings.
- SGRAMs differ from SDRAMs by providing certain column block write functions and masked write or write-per-bit functions to accommodate high- performance graphics applications
- Much ofthe circuitry of a SGRAM according to the present invention is similar to circuitry in known SGRAMs, such as the Micron Technology, Inc. MT41LC256K32D4(S) 256K X 32 SGRAM, which is described in detail in the corresponding Micron Technology, Inc. 1995 DRAM Data Book.
- SDRAM 20 includes a bank 0 memory array 22 and a bank 1 memory array 24 which both comprise storage cells organized in rows and columns for storing data.
- each bank memory array comprises four separate arrays of 2048 rows x 1024 columns.
- a typical SDRAM 20 provides optimum memory performance in a low voltage environment such as a 3.3 V environment.
- a system clock (CLK) signal is provided through a CLK input pin and a clock enable signal (CKE) is provided through a CKE input pin to SDRAM 20.
- CLK system clock
- CKE clock enable signal
- the CLK signal is activated and deactivated based on the state ofthe CKE signal. All the input and output signals of SDRAM 20, with the exception ofthe CKE input signal during power down and self refresh modes, are synchronized to the active going edge (the positive going edge in the embodiment illustrated in Figure 1) of the CLK signal.
- a chip select (CS*) input pin inputs a CS* signal which enables, when low, and disables, when high a command decode 26.
- Command decode 26 is included in a command controller 28.
- Command decoder 26 receives control signals including a row address strobe (RAS*) signal on a RAS* pin, column address strobe (CAS*) signal on a CAS* pin, and a write enable (WE*) signal on a WE* pin.
- RAS* row address strobe
- CAS* column address strobe
- WE* write enable
- Command controller 28 controls the various circuitry of SDRAM 20 based on decoded commands such as during controlled reads or writes from or to bank 0 memory array 22 and bank 1 memory array 24.
- a bank address (BA) signal is provided on a BA input pin to define which bank memory array should be operated on by certain commands issued by command controller 28.
- Address inputs bits are provided on input pins A0-A10. As described below, both the row and column address input bits are provided on the address input pins.
- data is supplied to SDRAM 20 via input/output pins (DQ1 -DQ4).
- DQ1-DQ4 input/output pins
- DQ1-DQ4 input/output pins
- An input/output mask signal is provided on a DQM input pin to provide non-persistent buffer control for a data-in buffer 30 and a data-out buffer 32.
- SDRAM 20 must be powered-up and initialized in a predefined manner.
- both bank 0 and bank 1 memory arrays 22 and 24 must be precharged and placed in an idle state. The precharging ofthe bank memory arrays is preformed with a precharge command operation which is described in more detail below.
- a precharge command operation which is described in more detail below.
- two AUTO-REFRESH operations must be performed. Once the two AUTO-REFRESH operations are performed, SDRAM 20 is available for programming of a mode register 40. Mode register 40 is assumed to have an unknown state when SDRAM 20 is powered up. Consequently, before performing any operational command, mode register 40 must be set or programmed.
- Mode register 40 is typically a persistent register wherein once programmed, the mode register retains the program op-code until the mode register is reprogrammed or SDRAM 20 loses power. Most ofthe possible programmable options of SDRAM 20 are defined in the op-codes stored in mode register 40.
- mode register 40 is programmed by providing a desired op-code via the BA input pins and the A0-A10 address inputs, in conjunction with a SET MODE REGISTER command determined by CS*, RAS*, CAS*, and WE* being registered low.
- a no operation (NOP) command can be provided to SDRAM 20 to prevent other unwanted commands from being registered during idle or wait states.
- Two refresh commands are typically available in SDRAM 20 which are an AUTO-REFRESH command and a SELF-REFRESH command.
- the AUTO-REFRESH command is performed with refresh controller 34 and refresh counter 38 in a manner described in detail below to refresh the memory arrays.
- the SELF-REFRESH command is performed with refresh controller 34, self-refresh oscillator and timer 36, and refresh counter 38 in a manner described below.
- Self-refresh oscillator and timer 96 internally generates a clock signal to provide internal timing for when auto refreshes commands occur in self-refresh mode.
- An AUTO REFRESH command is initiated by registering CS*, RAS* and CAS* low with WE* high.
- the AUTO REFRESH command is preferably employed while operating SDRAM 20.
- the AUTO REFRESH command is non-persistent, and therefore must be issued each time a refresh is required.
- Addressing ofthe rows is generated by internal refresh controller 34 and refresh counter 38.
- the A0-A10 address inputs are treated as "don't care" conditions during an AUTO REFRESH command.
- all 4,096 rows need to be refreshed every 64 ms. Therefore, providing a distributed AUTO REFRESH command every
- a non-preferred. alternative form of refreshing is accomplished by issuing all 4,096 AUTO REFRESH commands in a burst at a minimum cycle rate every 64 ms.
- a SELF-REFRESH command is initiated by registering CKE, CS*, RAS*, and CAS* low with WE* high. Note that the command input signals are identical to an AUTO REFRESH command except that CKE is disabled. Once the SELF-REFRESH command is registered, all the inputs to SDRAM 20 become "don't cares" with the exception of CKE, as CKE must remain low. Once SELF-REFRESH mode is engaged with the SELF-
- SDRAM 20 provides its own internal clocking to cause it to perform its own AUTO REFRESH operations.
- the internal clocking is performed by self refresh oscillator and timer 36. In this way SDRAM 20 can remain in SELF-REFRESH mode for an indefinite period.
- the addressing during SELF-REFRESH mode is performed with refresh controller 34 and refresh counter 38.
- each auto refresh operation in this embodiment of SDRAM 20 is to a bank memory array specified by the state ofthe BA signal provided on the BA pin.
- the AUTO REFRESH commands are not alternated between banks, instead more than one row in the specified bank is auto refreshed before switching banks.
- refresh counter 38 provides row 0 ofthe specified bank, then row 1 of the specified bank, then row 2 ofthe specified bank, ... , and finally row 2,048 ofthe specified bank of SDRAM 20.
- refresh counter 38 counts partially or entirely through the rows of the specified bank than switches to another bank. In this embodiment, refresh counter 38 preferably counts through any number of rows from 1 to 2048 prior to switching banks.
- a refresh counter 38 employed in one preferred embodiment of SDRAM 20 is illustrated in block diagram form in Figure 3.
- This preferred embodiment of SDRAM 20 includes a separate refresh counter portion for each bank memory array in the SDRAM.
- refresh counter 38 includes a refresh counter bank 0 portion 38A and a refresh counter bank 1 portion 38B. If each bank memory array has 2048 row, each refresh counter bank portion includes 1 1 bits to hold the existing row address currently being refreshed. This is in contrast to a single portion counter 38 which has one counter portion with 1 1 bits to address the 2048 rows of every bank memory array.
- the auto refresh operation can stop partially through the refreshing of rows in a given specified bank.
- an auto refresh operation can be performed for row 0 through row 8 in bank 0, then switch to bank 1 to perform auto refreshes on addressed rows.
- the count held in refresh counter bank 0 portion 38A indicates that the refreshing was last performed on row 8 of bank 0, so that refreshing then begins in row 9 or whatever row was due to be refreshed prior to switching banks.
- An auto refresh operation performed in a predetermined specified bank memory array of an alternative embodiment of SDRAM 20 during auto refresh mode is illustrated in timing diagram form in Figure 4.
- the BA signal is a don't care during the initiation ofthe auto refresh operation. Nevertheless, prior to issuing the AUTO REFRESH command, one ofthe banks is predetermined as the bank to be auto refreshed.
- the AUTO REFRESH commands are not alternated between banks, rather all 2048 rows of the specified predetermined bank memory array are refreshed in the predetermined bank before switching banks. In this way, other command can be performed in the bank memory array not being refreshed.
- the BA signal is not used to specify the bank, the user ofthe memory device must keep track of which bank the AUTO REFRESH command is being performed in.
- a timing diagram illustrates an auto refresh operation starting at a predetermined specified bank in SDRAM 20 during initialization and loading of mode register 40. As described above for the two bank SDRAM 20, after both bank memory arrays have been precharged and placed in an idle state, two auto refresh operations are performed prior to the programming of mode register 40.
- the initial AUTO REFRESH command is started in the bank 0 memory array. Since, the AUTO REFRESH commands complete the refreshing of all 2048 rows prior to switching banks, the user can keep track of which bank an auto refresh operation is being performed in based on the knowledge of where the initial auto refresh is performed in SDRAM 20 and thereafter, the order of refreshing the banks. In a two bank system, the knowledge ofthe current bank can be maintained simply by toggling a bit each time the bank is switched.
- the user ofthe memory device does not need to start tracking which bank the AUTO REFRESH command is being performed in during initialization, instead the user of the memory device issues a special AUTO REFRESH command or some other special command to indicate that the next auto refresh operation is to be performed in a preset bank, such as bank 0, or in a user determined bank. After issuing the special command, the user then must track which bank the current auto refresh operation is being performed in as described above.
- All the embodiments ofthe SDRAM or SGRAM according to the present invention permit the user ofthe memory device to know which bank memory array in a multi-bank system is being refreshed.
- the user specifies the bank to be refreshed at the initiation of an AUTO REFRESH command with the BA signal on the BA pin in a two bank memory device or on multiple BA pins in a memory device with more than two banks.
- the first refresh is to a known bank and the order ofthe banks to be subsequently refreshed is known. In either case, with the present invention, only one bank (the bank specified to be refreshed) needs to be idle at a given time. Thus, other commands can be performed on other banks not being refreshed during an auto refresh operation on a specified bank.
- the t RC time shown in Figures 2, 4, and 5, representing the command period from a refresh to a refresh or from a refresh to an ACTIVE command can be utilized to perform commands in banks not being refreshed.
- the auto refreshing of the bank 0 memory array while an active and a read operation are performed in the bank 1 memory array is illustrated in timing diagram form in Figure 6.
- an auto refresh command is started by specifying bank 0 as the specified bank memory array to be refreshed.
- an ACTIVE command is started in bank 1 to activate the rows of the bank 1 memory array.
- a read command with a read latency of two is then performed to read data out from column m ofthe activated row. This transfer operation is performed between two AUTO REFRESH commands to bank 0.
- the ACTIVE command is shown after the AUTO REFRESH command, the ACTIVE command to bank 1 could be performed before the first AUTO REFRESH command illustrated in Figure 6.
- Figure 6 shows an ACTIVE command and a READ command, but it will be understood by those skilled in the art of memory devices, that a write operation which writes data into SDRAM 20 or other operation could also be performed between the two AUTO REFRESH commands during the t RC time.
- the read operation is shown for one column of data, but could easily be extended to apply to a burst of length two, four, eight, or full page if the operation could be performed in between the two AUTO REFRESH commands in the time represented by t RC .
- the embodiments of SDRAM 20 described above refer to a two bank memory device, but the present invention applies to any multi-bank synchronous memory device such as a four or eight bank memory device.
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU21324/97A AU2132497A (en) | 1996-02-16 | 1997-02-14 | Auto refresh to specified bank |
KR1019980706383A KR100297086B1 (en) | 1996-02-16 | 1997-02-14 | Auto refresh to specified bank |
JP52959797A JP3616834B2 (en) | 1996-02-16 | 1997-02-14 | Auto refresh for specified bank |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/602,593 US5627791A (en) | 1996-02-16 | 1996-02-16 | Multiple bank memory with auto refresh to specified bank |
US08/602,593 | 1996-02-16 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1997030453A1 true WO1997030453A1 (en) | 1997-08-21 |
Family
ID=24411984
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1997/002652 WO1997030453A1 (en) | 1996-02-16 | 1997-02-14 | Auto refresh to specified bank |
Country Status (5)
Country | Link |
---|---|
US (1) | US5627791A (en) |
JP (1) | JP3616834B2 (en) |
KR (1) | KR100297086B1 (en) |
AU (1) | AU2132497A (en) |
WO (1) | WO1997030453A1 (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2005114672A1 (en) | 2004-05-21 | 2005-12-01 | Qualcomm Incorporated | Method and system for controlling refresh in volatile memories |
WO2005119690A1 (en) | 2004-05-27 | 2005-12-15 | Qualcomm Incorporated | Method and system for providing independent bank refresh for volatile memories |
WO2005119691A1 (en) | 2004-05-27 | 2005-12-15 | Qualcomm Incorporated | Method and system for providing directed bank refresh for volatile memories |
US7093067B2 (en) | 2001-03-30 | 2006-08-15 | International Business Machines Corporation | DRAM architecture enabling refresh and access operations in the same bank |
US7953921B2 (en) | 2004-12-28 | 2011-05-31 | Qualcomm Incorporated | Directed auto-refresh synchronization |
US7995415B2 (en) | 2004-12-03 | 2011-08-09 | Micron Technology, Inc. | System and method for reducing power consumption during extended refresh periods of dynamic random access memory devices |
US8072829B2 (en) | 2006-02-23 | 2011-12-06 | Hynix Semiconductor Inc. | Dynamic semiconductor memory with improved refresh mechanism |
Families Citing this family (132)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69324508T2 (en) | 1992-01-22 | 1999-12-23 | Enhanced Memory Systems Inc | DRAM with integrated registers |
US5838631A (en) | 1996-04-19 | 1998-11-17 | Integrated Device Technology, Inc. | Fully synchronous pipelined ram |
KR100203137B1 (en) * | 1996-06-27 | 1999-06-15 | 김영환 | Synchronous graphic ram controllable block write |
US6392948B1 (en) * | 1996-08-29 | 2002-05-21 | Micron Technology, Inc. | Semiconductor device with self refresh test mode |
US5835437A (en) * | 1996-08-30 | 1998-11-10 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device having memory cell array divided into a plurality of memory blocks |
US5872736A (en) * | 1996-10-28 | 1999-02-16 | Micron Technology, Inc. | High speed input buffer |
US5917758A (en) | 1996-11-04 | 1999-06-29 | Micron Technology, Inc. | Adjustable output driver circuit |
US5949254A (en) * | 1996-11-26 | 1999-09-07 | Micron Technology, Inc. | Adjustable output driver circuit |
US6115318A (en) | 1996-12-03 | 2000-09-05 | Micron Technology, Inc. | Clock vernier adjustment |
US5838177A (en) * | 1997-01-06 | 1998-11-17 | Micron Technology, Inc. | Adjustable output driver circuit having parallel pull-up and pull-down elements |
US5940608A (en) * | 1997-02-11 | 1999-08-17 | Micron Technology, Inc. | Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal |
US5920518A (en) * | 1997-02-11 | 1999-07-06 | Micron Technology, Inc. | Synchronous clock generator including delay-locked loop |
US5946244A (en) | 1997-03-05 | 1999-08-31 | Micron Technology, Inc. | Delay-locked loop with binary-coupled capacitor |
US5956502A (en) * | 1997-03-05 | 1999-09-21 | Micron Technology, Inc. | Method and circuit for producing high-speed counts |
US5818777A (en) * | 1997-03-07 | 1998-10-06 | Micron Technology, Inc. | Circuit for implementing and method for initiating a self-refresh mode |
US5870347A (en) | 1997-03-11 | 1999-02-09 | Micron Technology, Inc. | Multi-bank memory input/output line selection |
US6014759A (en) * | 1997-06-13 | 2000-01-11 | Micron Technology, Inc. | Method and apparatus for transferring test data from a memory array |
US6173432B1 (en) * | 1997-06-20 | 2001-01-09 | Micron Technology, Inc. | Method and apparatus for generating a sequence of clock signals |
US5883849A (en) * | 1997-06-30 | 1999-03-16 | Micron Technology, Inc. | Method and apparatus for simultaneous memory subarray testing |
US5953284A (en) | 1997-07-09 | 1999-09-14 | Micron Technology, Inc. | Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same |
US6044429A (en) | 1997-07-10 | 2000-03-28 | Micron Technology, Inc. | Method and apparatus for collision-free data transfers in a memory device with selectable data or address paths |
US6011732A (en) | 1997-08-20 | 2000-01-04 | Micron Technology, Inc. | Synchronous clock generator including a compound delay-locked loop |
US5835441A (en) | 1997-08-21 | 1998-11-10 | Micron Technology, Inc. | Column select latch for SDRAM |
US5999481A (en) * | 1997-08-22 | 1999-12-07 | Micron Technology, Inc. | Method and apparatus for controlling the operation of an integrated circuit responsive to out-of-synchronism control signals |
US5856947A (en) * | 1997-08-27 | 1999-01-05 | S3 Incorporated | Integrated DRAM with high speed interleaving |
US5926047A (en) | 1997-08-29 | 1999-07-20 | Micron Technology, Inc. | Synchronous clock generator including a delay-locked loop signal loss detector |
US6101197A (en) * | 1997-09-18 | 2000-08-08 | Micron Technology, Inc. | Method and apparatus for adjusting the timing of signals over fine and coarse ranges |
US6178130B1 (en) * | 1997-10-10 | 2001-01-23 | Rambus Inc. | Apparatus and method for refreshing subsets of memory devices in a memory system |
US6075744A (en) * | 1997-10-10 | 2000-06-13 | Rambus Inc. | Dram core refresh with reduced spike current |
KR100492795B1 (en) * | 1997-12-31 | 2005-08-12 | 주식회사 하이닉스반도체 | Bank Selection Circuit |
JPH11203866A (en) * | 1998-01-16 | 1999-07-30 | Mitsubishi Electric Corp | Semiconductor storage device |
US5923594A (en) * | 1998-02-17 | 1999-07-13 | Micron Technology, Inc. | Method and apparatus for coupling data from a memory device using a single ended read data path |
US6115320A (en) | 1998-02-23 | 2000-09-05 | Integrated Device Technology, Inc. | Separate byte control on fully synchronous pipelined SRAM |
US6269451B1 (en) | 1998-02-27 | 2001-07-31 | Micron Technology, Inc. | Method and apparatus for adjusting data timing by delaying clock signal |
WO1999046775A2 (en) | 1998-03-10 | 1999-09-16 | Rambus, Inc. | Performing concurrent refresh and current control operations in a memory subsystem |
JPH11312386A (en) * | 1998-03-30 | 1999-11-09 | Siemens Ag | Dram chip |
US6016282A (en) | 1998-05-28 | 2000-01-18 | Micron Technology, Inc. | Clock vernier adjustment |
US6405280B1 (en) | 1998-06-05 | 2002-06-11 | Micron Technology, Inc. | Packet-oriented synchronous DRAM interface supporting a plurality of orderings for data block transfers within a burst sequence |
US5963481A (en) * | 1998-06-30 | 1999-10-05 | Enhanced Memory Systems, Inc. | Embedded enhanced DRAM, and associated method |
JP2000030441A (en) * | 1998-07-15 | 2000-01-28 | Mitsubishi Electric Corp | Semiconductor storage and its refresh method |
US6317657B1 (en) * | 1998-08-18 | 2001-11-13 | International Business Machines Corporation | Method to battery back up SDRAM data on power failure |
US6338127B1 (en) | 1998-08-28 | 2002-01-08 | Micron Technology, Inc. | Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same |
US6349399B1 (en) | 1998-09-03 | 2002-02-19 | Micron Technology, Inc. | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same |
US6279090B1 (en) | 1998-09-03 | 2001-08-21 | Micron Technology, Inc. | Method and apparatus for resynchronizing a plurality of clock signals used in latching respective digital signals applied to a packetized memory device |
US6029250A (en) | 1998-09-09 | 2000-02-22 | Micron Technology, Inc. | Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same |
US6587918B1 (en) * | 1998-11-19 | 2003-07-01 | Micron Technology, Inc. | Method for controlling refresh of a multibank memory device |
JP3311305B2 (en) * | 1998-11-19 | 2002-08-05 | 沖電気工業株式会社 | Synchronous burst nonvolatile semiconductor memory device |
US6298413B1 (en) * | 1998-11-19 | 2001-10-02 | Micron Technology, Inc. | Apparatus for controlling refresh of a multibank memory device |
US6430696B1 (en) | 1998-11-30 | 2002-08-06 | Micron Technology, Inc. | Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same |
US6374360B1 (en) | 1998-12-11 | 2002-04-16 | Micron Technology, Inc. | Method and apparatus for bit-to-bit timing correction of a high speed memory bus |
US6330636B1 (en) | 1999-01-29 | 2001-12-11 | Enhanced Memory Systems, Inc. | Double data rate synchronous dynamic random access memory device incorporating a static RAM cache per memory bank |
US6233199B1 (en) * | 1999-02-26 | 2001-05-15 | Micron Technology, Inc. | Full page increment/decrement burst for DDR SDRAM/SGRAM |
US6470060B1 (en) | 1999-03-01 | 2002-10-22 | Micron Technology, Inc. | Method and apparatus for generating a phase dependent control signal |
US6282606B1 (en) * | 1999-04-02 | 2001-08-28 | Silicon Aquarius, Inc. | Dynamic random access memories with hidden refresh and utilizing one-transistor, one-capacitor cells, systems and methods |
US7069406B2 (en) * | 1999-07-02 | 2006-06-27 | Integrated Device Technology, Inc. | Double data rate synchronous SRAM with 100% bus utilization |
US6195303B1 (en) | 1999-10-25 | 2001-02-27 | Winbond Electronics Corporation | Clock-based transparent refresh mechanisms for DRAMS |
JP4201490B2 (en) * | 2000-04-28 | 2008-12-24 | 富士通マイクロエレクトロニクス株式会社 | Memory circuit having automatic precharge function and integrated circuit device having automatic internal command function |
US6327209B1 (en) | 2000-08-30 | 2001-12-04 | Micron Technology, Inc. | Multi stage refresh control of a memory device |
US6529433B2 (en) * | 2001-04-03 | 2003-03-04 | Hynix Semiconductor, Inc. | Refresh mechanism in dynamic memories |
US6590822B2 (en) * | 2001-05-07 | 2003-07-08 | Samsung Electronics Co., Ltd. | System and method for performing partial array self-refresh operation in a semiconductor memory device |
JP2003006041A (en) * | 2001-06-20 | 2003-01-10 | Hitachi Ltd | Semiconductor device |
KR100429872B1 (en) * | 2001-06-27 | 2004-05-04 | 삼성전자주식회사 | Memory system for promoting efficiency of use of semiconductor memory and refresh method of the semiconductor memory |
US6801989B2 (en) * | 2001-06-28 | 2004-10-05 | Micron Technology, Inc. | Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same |
KR100680942B1 (en) * | 2001-06-28 | 2007-02-08 | 주식회사 하이닉스반도체 | Self-refresh device of semiconductor memory |
KR100437610B1 (en) * | 2001-09-20 | 2004-06-30 | 주식회사 하이닉스반도체 | A low power semiconductor memory device with normal mode and partial array self refresh mode |
US6771553B2 (en) * | 2001-10-18 | 2004-08-03 | Micron Technology, Inc. | Low power auto-refresh circuit and method for dynamic random access memories |
US20060239098A1 (en) * | 2002-03-06 | 2006-10-26 | International Business Machines Corporation | Dram architecture enabling refresh and access operations in the same bank |
US6693837B2 (en) * | 2002-04-23 | 2004-02-17 | Micron Technology, Inc. | System and method for quick self-refresh exit with transitional refresh |
US6731548B2 (en) * | 2002-06-07 | 2004-05-04 | Micron Technology, Inc. | Reduced power registered memory module and method |
US6711093B1 (en) * | 2002-08-29 | 2004-03-23 | Micron Technology, Inc. | Reducing digit equilibrate current during self-refresh mode |
JP2004103081A (en) * | 2002-09-06 | 2004-04-02 | Renesas Technology Corp | Semiconductor storage device |
US7035155B2 (en) * | 2002-09-26 | 2006-04-25 | Xware Technology, Inc. | Dynamic memory management |
US7617356B2 (en) * | 2002-12-31 | 2009-11-10 | Intel Corporation | Refresh port for a dynamic memory |
US7168027B2 (en) | 2003-06-12 | 2007-01-23 | Micron Technology, Inc. | Dynamic synchronization of data capture on an optical or other high speed communications link |
KR100532456B1 (en) * | 2003-07-30 | 2005-11-30 | 삼성전자주식회사 | Memory controller and semiconductor having the same |
US20050078538A1 (en) * | 2003-09-30 | 2005-04-14 | Rainer Hoehler | Selective address-range refresh |
US20050088894A1 (en) * | 2003-10-23 | 2005-04-28 | Brucke Paul E. | Auto-refresh multiple row activation |
US7392339B2 (en) * | 2003-12-10 | 2008-06-24 | Intel Corporation | Partial bank DRAM precharge |
US6859407B1 (en) | 2004-01-14 | 2005-02-22 | Infineon Technologies Ag | Memory with auto refresh to designated banks |
KR100653688B1 (en) * | 2004-04-29 | 2006-12-04 | 삼성전자주식회사 | Semiconductor memory device and refresh method of the same, and memory system for the same |
JP4559318B2 (en) * | 2004-07-21 | 2010-10-06 | 三星電子株式会社 | Synchronous memory device, operation method thereof, and memory system |
US7164615B2 (en) * | 2004-07-21 | 2007-01-16 | Samsung Electronics Co., Ltd. | Semiconductor memory device performing auto refresh in the self refresh mode |
KR100752639B1 (en) * | 2004-08-31 | 2007-08-29 | 삼성전자주식회사 | Memory device having external refresh pin and external refresh bank address pin and refresh method thereof |
KR100564640B1 (en) * | 2005-02-16 | 2006-03-28 | 삼성전자주식회사 | A temperature sensor operation indicating signal generator and a semiconductor memory device using the generator |
US8386722B1 (en) | 2008-06-23 | 2013-02-26 | Google Inc. | Stacked DIMM memory interface |
US8130560B1 (en) | 2006-11-13 | 2012-03-06 | Google Inc. | Multi-rank partial width memory modules |
US8397013B1 (en) | 2006-10-05 | 2013-03-12 | Google Inc. | Hybrid memory module |
US8081474B1 (en) | 2007-12-18 | 2011-12-20 | Google Inc. | Embossed heat spreader |
US8090897B2 (en) | 2006-07-31 | 2012-01-03 | Google Inc. | System and method for simulating an aspect of a memory circuit |
US8055833B2 (en) | 2006-10-05 | 2011-11-08 | Google Inc. | System and method for increasing capacity, performance, and flexibility of flash storage |
US20080082763A1 (en) | 2006-10-02 | 2008-04-03 | Metaram, Inc. | Apparatus and method for power management of memory circuits by a system or component thereof |
WO2007002324A2 (en) | 2005-06-24 | 2007-01-04 | Metaram, Inc. | An integrated memory core and memory interface circuit |
US8041881B2 (en) | 2006-07-31 | 2011-10-18 | Google Inc. | Memory device with emulated characteristics |
US9542352B2 (en) | 2006-02-09 | 2017-01-10 | Google Inc. | System and method for reducing command scheduling constraints of memory circuits |
US7609567B2 (en) | 2005-06-24 | 2009-10-27 | Metaram, Inc. | System and method for simulating an aspect of a memory circuit |
US8335894B1 (en) | 2008-07-25 | 2012-12-18 | Google Inc. | Configurable memory system with interface circuit |
US8359187B2 (en) | 2005-06-24 | 2013-01-22 | Google Inc. | Simulating a different number of memory circuit devices |
US8244971B2 (en) | 2006-07-31 | 2012-08-14 | Google Inc. | Memory circuit system and method |
US7590796B2 (en) | 2006-07-31 | 2009-09-15 | Metaram, Inc. | System and method for power management in memory systems |
US8077535B2 (en) | 2006-07-31 | 2011-12-13 | Google Inc. | Memory refresh apparatus and method |
US7392338B2 (en) | 2006-07-31 | 2008-06-24 | Metaram, Inc. | Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits |
US7386656B2 (en) | 2006-07-31 | 2008-06-10 | Metaram, Inc. | Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit |
US20080028136A1 (en) | 2006-07-31 | 2008-01-31 | Schakel Keith R | Method and apparatus for refresh management of memory modules |
US8111566B1 (en) | 2007-11-16 | 2012-02-07 | Google, Inc. | Optimal channel design for memory devices for providing a high-speed memory interface |
US9507739B2 (en) | 2005-06-24 | 2016-11-29 | Google Inc. | Configurable memory circuit system and method |
US7580312B2 (en) | 2006-07-31 | 2009-08-25 | Metaram, Inc. | Power saving system and method for use with a plurality of memory circuits |
US8089795B2 (en) | 2006-02-09 | 2012-01-03 | Google Inc. | Memory module with memory stack and interface with enhanced capabilities |
US8796830B1 (en) | 2006-09-01 | 2014-08-05 | Google Inc. | Stackable low-profile lead frame package |
US9171585B2 (en) | 2005-06-24 | 2015-10-27 | Google Inc. | Configurable memory circuit system and method |
US10013371B2 (en) | 2005-06-24 | 2018-07-03 | Google Llc | Configurable memory circuit system and method |
US8327104B2 (en) | 2006-07-31 | 2012-12-04 | Google Inc. | Adjusting the timing of signals associated with a memory system |
US8438328B2 (en) | 2008-02-21 | 2013-05-07 | Google Inc. | Emulation of abstracted DIMMs using abstracted DRAMs |
US8060774B2 (en) | 2005-06-24 | 2011-11-15 | Google Inc. | Memory systems and memory modules |
GB2444663B (en) | 2005-09-02 | 2011-12-07 | Metaram Inc | Methods and apparatus of stacking drams |
US7330391B2 (en) | 2005-10-17 | 2008-02-12 | Infineon Technologies Ag | Memory having directed auto-refresh |
US9632929B2 (en) | 2006-02-09 | 2017-04-25 | Google Inc. | Translating an address associated with a command communicated between a system and memory circuits |
JP4894306B2 (en) * | 2006-03-09 | 2012-03-14 | 富士通セミコンダクター株式会社 | Semiconductor memory, memory system, and semiconductor memory operating method |
JP4912718B2 (en) | 2006-03-30 | 2012-04-11 | 富士通セミコンダクター株式会社 | Dynamic semiconductor memory |
US7724589B2 (en) | 2006-07-31 | 2010-05-25 | Google Inc. | System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits |
US8209479B2 (en) | 2007-07-18 | 2012-06-26 | Google Inc. | Memory circuit system and method |
US8080874B1 (en) | 2007-09-14 | 2011-12-20 | Google Inc. | Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween |
US8045416B2 (en) * | 2008-03-05 | 2011-10-25 | Micron Technology, Inc. | Method and memory device providing reduced quantity of interconnections |
EP2441007A1 (en) | 2009-06-09 | 2012-04-18 | Google, Inc. | Programming of dimm termination resistance values |
KR101796116B1 (en) | 2010-10-20 | 2017-11-10 | 삼성전자 주식회사 | Semiconductor device, memory module and memory system having the same and operating method thereof |
KR20130090633A (en) | 2012-02-06 | 2013-08-14 | 삼성전자주식회사 | Refresh circuit of a semiconductor memory device and method of refreshing the semiconductor memory device |
JP5454618B2 (en) * | 2012-05-28 | 2014-03-26 | 富士通セミコンダクター株式会社 | Memory device, memory controller and memory system |
KR101993794B1 (en) | 2012-06-14 | 2019-06-27 | 삼성전자주식회사 | Memory device, operation method thereof and memory system having the same |
US9236110B2 (en) | 2012-06-30 | 2016-01-12 | Intel Corporation | Row hammer refresh command |
KR102023487B1 (en) * | 2012-09-17 | 2019-09-20 | 삼성전자주식회사 | Semiconductor memory device capable of performing refresh operation without auto refresh command and memory system including the same |
US9384821B2 (en) | 2012-11-30 | 2016-07-05 | Intel Corporation | Row hammer monitoring based on stored row hammer threshold value |
KR20150128087A (en) * | 2014-05-08 | 2015-11-18 | 에스케이하이닉스 주식회사 | Semeconductor apparatus with preventing refresh error and memory system using the same |
US10622052B2 (en) | 2018-09-04 | 2020-04-14 | Micron Technology, Inc. | Reduced peak self-refresh current in a memory device |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2284692A (en) * | 1993-11-08 | 1995-06-14 | Hyundai Electronics Ind | Hidden self-refresh method and apparatus for dynamic random access memory (DRAM) |
JPH07201172A (en) * | 1993-12-28 | 1995-08-04 | Fujitsu Ltd | Semiconductor storage |
JPH07245737A (en) * | 1994-01-12 | 1995-09-19 | Matsushita Electric Ind Co Ltd | Moving picture storage memory, moving picture storage device, moving picture display device and still picture storage memory and electronic notebook |
US5555527A (en) * | 1993-12-15 | 1996-09-10 | Matsushita Electric Industrial Co., Ltd. | Semiconductor memory, moving-picture storing memory, moving-picture storing apparatus, moving-picture displaying apparatus, static-picture storing memory, and electronic notebook |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5208779A (en) * | 1991-04-15 | 1993-05-04 | Micron Technology, Inc. | Circuit for providing synchronous refresh cycles in self-refreshing interruptable DRAMs |
US5335201A (en) * | 1991-04-15 | 1994-08-02 | Micron Technology, Inc. | Method for providing synchronous refresh cycles in self-refreshing interruptable DRAMs |
US5291443A (en) * | 1991-06-26 | 1994-03-01 | Micron Technology, Inc. | Simultaneous read and refresh of different rows in a dram |
AU6988494A (en) * | 1993-05-28 | 1994-12-20 | Rambus Inc. | Method and apparatus for implementing refresh in a synchronous dram system |
US5335202A (en) * | 1993-06-29 | 1994-08-02 | Micron Semiconductor, Inc. | Verifying dynamic memory refresh |
US5455801A (en) * | 1994-07-15 | 1995-10-03 | Micron Semiconductor, Inc. | Circuit having a control array of memory cells and a current source and a method for generating a self-refresh timing signal |
-
1996
- 1996-02-16 US US08/602,593 patent/US5627791A/en not_active Expired - Lifetime
-
1997
- 1997-02-14 AU AU21324/97A patent/AU2132497A/en not_active Abandoned
- 1997-02-14 KR KR1019980706383A patent/KR100297086B1/en not_active IP Right Cessation
- 1997-02-14 JP JP52959797A patent/JP3616834B2/en not_active Expired - Fee Related
- 1997-02-14 WO PCT/US1997/002652 patent/WO1997030453A1/en active IP Right Grant
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2284692A (en) * | 1993-11-08 | 1995-06-14 | Hyundai Electronics Ind | Hidden self-refresh method and apparatus for dynamic random access memory (DRAM) |
US5555527A (en) * | 1993-12-15 | 1996-09-10 | Matsushita Electric Industrial Co., Ltd. | Semiconductor memory, moving-picture storing memory, moving-picture storing apparatus, moving-picture displaying apparatus, static-picture storing memory, and electronic notebook |
JPH07201172A (en) * | 1993-12-28 | 1995-08-04 | Fujitsu Ltd | Semiconductor storage |
US5535169A (en) * | 1993-12-28 | 1996-07-09 | Fujitsu Limited | Semiconductor memory device |
JPH07245737A (en) * | 1994-01-12 | 1995-09-19 | Matsushita Electric Ind Co Ltd | Moving picture storage memory, moving picture storage device, moving picture display device and still picture storage memory and electronic notebook |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7093067B2 (en) | 2001-03-30 | 2006-08-15 | International Business Machines Corporation | DRAM architecture enabling refresh and access operations in the same bank |
WO2005114672A1 (en) | 2004-05-21 | 2005-12-01 | Qualcomm Incorporated | Method and system for controlling refresh in volatile memories |
KR100844300B1 (en) * | 2004-05-21 | 2008-07-07 | 퀄컴 인코포레이티드 | Memory system, method of refreshing memory, memory, and memory controller |
WO2005119690A1 (en) | 2004-05-27 | 2005-12-15 | Qualcomm Incorporated | Method and system for providing independent bank refresh for volatile memories |
WO2005119691A1 (en) | 2004-05-27 | 2005-12-15 | Qualcomm Incorporated | Method and system for providing directed bank refresh for volatile memories |
KR100870478B1 (en) * | 2004-05-27 | 2008-11-27 | 콸콤 인코포레이티드 | Method and system for providing independent bank refresh for volatile memories |
KR100871080B1 (en) * | 2004-05-27 | 2008-11-28 | 콸콤 인코포레이티드 | Method and system for providing directed bank refresh for volatile memories |
US7583552B2 (en) * | 2004-05-27 | 2009-09-01 | Qualcomm Incorporated | Method and system for providing independent bank refresh for volatile memories |
US7586805B2 (en) | 2004-05-27 | 2009-09-08 | Qualcomm Incorporated | Method and system for providing directed bank refresh for volatile memories |
US7995415B2 (en) | 2004-12-03 | 2011-08-09 | Micron Technology, Inc. | System and method for reducing power consumption during extended refresh periods of dynamic random access memory devices |
US7953921B2 (en) | 2004-12-28 | 2011-05-31 | Qualcomm Incorporated | Directed auto-refresh synchronization |
US8072829B2 (en) | 2006-02-23 | 2011-12-06 | Hynix Semiconductor Inc. | Dynamic semiconductor memory with improved refresh mechanism |
Also Published As
Publication number | Publication date |
---|---|
KR100297086B1 (en) | 2001-08-07 |
KR19990082643A (en) | 1999-11-25 |
JPH11505056A (en) | 1999-05-11 |
US5627791A (en) | 1997-05-06 |
JP3616834B2 (en) | 2005-02-02 |
AU2132497A (en) | 1997-09-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5627791A (en) | Multiple bank memory with auto refresh to specified bank | |
US5587961A (en) | Synchronous memory allowing early read command in write to read transitions | |
US5600605A (en) | Auto-activate on synchronous dynamic random access memory | |
US5636173A (en) | Auto-precharge during bank selection | |
US7869301B2 (en) | Apparatus for writing to multiple banks of a memory device | |
KR100257430B1 (en) | Cached synchronous dram architecture allowing concurrent dram operations | |
EP1168358B1 (en) | Refresh-type memory with zero write recovery time and no maximum cycle time | |
KR100260683B1 (en) | Cache sdram device | |
JP4734580B2 (en) | Enhanced bus turnaround integrated circuit dynamic random access memory device | |
KR20030038450A (en) | Memory device and internal control method therefor | |
US6219292B1 (en) | Semiconductor memory device having reduced power requirements during refresh operation by performing refresh operation in a burst method | |
US6026041A (en) | Semiconductor memory device | |
US6055289A (en) | Shared counter | |
US7263021B2 (en) | Refresh circuit for use in semiconductor memory device and operation method thereof | |
JPH10208468A (en) | Semiconductor memory and synchronous semiconductor memory | |
KR19980080771A (en) | Method and apparatus for increasing data bandwidth of dynamic memory device | |
JP3979950B2 (en) | Method and integrated circuit device for initiating precharge operation | |
KR20020078187A (en) | Synchronous dynamic random access memory device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GE HU IL IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK TJ TM TR TT UA UG UZ VN YU AM AZ BY KG KZ MD RU TJ TM |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): KE LS MW SD SZ UG AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG |
|
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
REG | Reference to national code |
Ref country code: DE Ref legal event code: 8642 |
|
ENP | Entry into the national phase |
Ref country code: JP Ref document number: 1997 529597 Kind code of ref document: A Format of ref document f/p: F |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1019980706383 Country of ref document: KR |
|
122 | Ep: pct application non-entry in european phase | ||
WWP | Wipo information: published in national office |
Ref document number: 1019980706383 Country of ref document: KR |
|
WWG | Wipo information: grant in national office |
Ref document number: 1019980706383 Country of ref document: KR |