WO1997032248A1 - Processeur d'images et procede de traitement d'images - Google Patents
Processeur d'images et procede de traitement d'images Download PDFInfo
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- WO1997032248A1 WO1997032248A1 PCT/JP1997/000535 JP9700535W WO9732248A1 WO 1997032248 A1 WO1997032248 A1 WO 1997032248A1 JP 9700535 W JP9700535 W JP 9700535W WO 9732248 A1 WO9732248 A1 WO 9732248A1
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- WIPO (PCT)
- Prior art keywords
- image processing
- packet
- procedure
- data
- engine
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
- G06F3/153—Digital output to display device ; Cooperation and interconnection of the display device with other functional units using cathode-ray tubes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/60—Memory management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
Definitions
- the present invention relates to an image processing device and an image processing method used for a graphic device, a special effect device, a video game machine, or the like, which is a video device using a preview.
- Background technology Images that are output to and displayed on a television receiver, monitor receiver, or cathode ray tube (CRT) display device at a home video game console, personal computer, or graphic computer.
- the image processing device that generates the image data is composed of a combination of a general-purpose memory chip, a central processing unit (CPU), and other arithmetic chips. High-speed processing is possible by providing a dedicated drawing device between the buffers.
- the CPU side does not directly access the frame buffer when generating an image, but performs geometry processing such as coordinate conversion, clipping, and light source calculation.
- geometry processing such as coordinate conversion, clipping, and light source calculation.
- Combination of basic unit figures (polygons) such as polygons and squares
- polygons such as polygons and squares
- the object is decomposed into a plurality of polygons, and a drawing command corresponding to each polygon is transferred from the CPU to the drawing device.
- the drawing device interprets the drawing command sent from the CPU via the external path, and calculates the colors and Z values of all pixels constituting the polygon from the vertex color data and the Z value indicating the depth. Calculates and renders the pixel data to the frame buffer, and draws a figure in the frame buffer.
- the Z value is information indicating the distance in the depth direction from the viewpoint.
- the object when displaying a three-dimensional object in the above image generating apparatus, the object is decomposed into a plurality of polygons, and a drawing command corresponding to each polygon is transferred from the CPU to the drawing apparatus.
- a method called texture matching / mib matching is adopted.
- a method of changing a display color by converting color data of an image through a color look-up table (CLUT) storing color conversion data is widely known. .
- texture matting is a technique of attaching a two-dimensional image (picture), that is, a texture pattern, prepared separately as a texture source image, to the surface of a polygon constituting an object.
- picture a two-dimensional image
- Mip matching is one of the texture matching methods in which pixel data is interpolated so that the pattern attached by the borrigone does not become unnatural when approaching or moving away from the 3D model. .
- arithmetic processing system composed of a combination of general-purpose memory chips such as home video game consoles and personal computers, CPUs and other arithmetic chips, the performance of the arithmetic chips, such as the operating frequency and circuit scale, has improved.
- memory path systems with large data transfer rates generally have high latencies and high performance in large-capacity burst transfers, but can perform well in small-capacity random transfers such as ordinary CPU access. Not.
- DMAC direct memory access controller
- an object of the present invention is to reduce the above-described bottleneck in an image processing device configured by combining a general-purpose memory chip, a CPU, and other arithmetic chips.
- Another object of the present invention is to provide an image processing apparatus and an image processing method for improving the efficiency of unpacking and packing of packet data.
- the present invention relates to an image processing apparatus having a plurality of image processing units and a memory connected via an external bus, and includes a data input unit for at least one image processing unit.
- a first bucket engine is provided in which the procedure for unpacketizing can be changed.
- the image processing apparatus may have a second bucket engine for converting the data into a bucket at a data output stage of another image processing unit.
- the second bucket engine corresponds to a bucket-making procedure at the time of packetization of data. Additional information indicating the procedure of unbucketing is added to the bucket, and
- the packet engine of (1) can perform unpacketization at the time of unpacketization according to the procedure indicated by the additional information. Thereby, each packet engine in the image processing apparatus according to the present invention has a degree of freedom in the packet format, and can efficiently perform the unpacking and packing of the packet data.
- the first and second bucket engines include a procedure selecting means for selecting a procedure of packetizing / unpacketizing the data in the second step.
- the bucket engine attaches the tag information indicating the unpacking procedure selected by the procedure selecting means at the time of packetizing to the bucket, and the second packet engine performs the unpacketizing.
- the procedure specified by the tag information can be selected by the procedure selecting means.
- the bucket engine in the image processing apparatus according to the present invention has a degree of freedom in the packet format, and can efficiently expand and pack the packet data.
- the image processing apparatus has, for example, a geometry processing function for performing a geometry processing for defining a three-dimensional model as a combination of unit figures and creating a drawing instruction for drawing a three-dimensional image.
- a first image processing unit that converts the created drawing instruction into a packet by the second packet engine and sends it as a command packet to an external bus, and a transmission from the first image processing unit. Renders the command packet to be unpacketized by the first bucket engine, interprets the drawing command sent as the command packet, and writes the pixel data into the frame buffer.
- the second image processing unit having the image processing function can be provided as the plurality of image processing units. Thereby, the image processing apparatus according to the present invention can perform the drawing processing efficiently.
- the present invention relates to an image processing method in an image processing apparatus having a plurality of image processing units and a memory connected via an external path, wherein at least one image processing unit has a data input It is characterized in that unpackaging is performed by the first packet engine provided in the first stage, which can change the procedure of unpacking data.
- the bucket format can be given a degree of freedom, and the efficiency of data transfer can be increased, and the efficiency of data in the memory can be increased.
- the data can be bucketed by the second bucket engine provided at the data output stage of another image processing unit.
- the second packet engine provides additional information indicating an unpacketizing procedure corresponding to the packetizing procedure at the time of packetization in a packet.
- the first packet engine can perform the unpacketing according to the procedure indicated by the additional information at the time of unpacking.
- the packet format of each packet engine has a degree of freedom, and the packet data can be efficiently packaged.
- the second packet engine selects a packetization / unpacketization procedure at the time of data packetization, and selects the selected packet. Evening showing the procedure of conversion The packet information is added to the packet, and the first packet engine performs the unpacketing by selecting the unpacketizing procedure specified by the evening information at the time of unpacking. be able to.
- the bucket format of each packet engine is given a degree of freedom, and the packet data can be efficiently planned and packed.
- the created drawing command is packetized by the second packet engine and sent to an external bus as a command packet, and sent from the first image processing unit in the second image processing unit.
- the first packet engine unpackets the incoming command packet, interprets the drawing command sent as the above command packet, and writes the pixel data to the frame buffer. Can be done.
- the image processing device can perform the drawing process efficiently.
- FIG. 1 is a program showing a configuration of a video game device to which the present invention is applied.
- FIG. 1 is a program showing a configuration of a video game device to which the present invention is applied.
- FIG. 2 is a diagram schematically showing an installation state of a programmable bucket engine PPE in the video game device.
- FIG. 3 is a block diagram showing a configuration of the PPE.
- FIG. 4 is a diagram showing an operation example of the PPE.
- FIG. 5 is a diagram showing another operation example of the PPE.
- FIG. 6 is a diagram showing another operation example of the PPE.
- FIG. 7 is a diagram showing an operation example of the variable length read / write buffer VLBF in the video game device.
- FIG. 8 is a plan view of a video game device to which the present invention is applied.
- FIG. 9 is a rear view of the video game device.
- FIG. 10 is a side view of the video game device.
- FIG. 11 is a plan view of a CD-ROM mounted on the video game device.
- the present invention is applied to, for example, a video game device having a configuration as shown in FIG.
- This video game device plays a game in accordance with an instruction from a user by reading and executing a game program stored in, for example, an optical disk or the like, and has a configuration as shown in FIG. Have. That is, the video game device includes two types of paths, namely, a main bus 1 and a sub bus 2. The main bus 1 and the sub-bus 2 are connected via a bus controller 10.
- the main bus 1 has a main central processing unit (CPU) 11 composed of a microprocessor and the like, and a main memory (main memory) composed of a random access memory (RAM). 12, Main direct memory access controller (main DMAC: Direct Memory Access Controller) 13, MPEG decoder (MDEC: MPEG Decoder) 14, and image processing unit (GPU: Graphic Processing Unit) 15 It is connected.
- main central processing unit CPU
- main memory main memory
- RAM random access memory
- main DMAC Direct Memory Access Controller
- MDEC MPEG Decoder
- GPU Graphic Processing Unit
- the sub-path 2 includes a sub-central processing unit (sub-CPU) 21 composed of a microprocessor or the like, a sub-storage device (sub-memory) 22 composed of a random access memory (RAM), Sub direct memory access controller (sub DMAC: Direct Memory Access Controller) 23, read-only memory (R0M: Read Only Memory) 24 storing programs such as operating system, audio processing unit (SPU : Sound Processing Unit) 25, communication control unit (ATM: Asynchronous Transmission module) 26, auxiliary storage device 27, input device 28, and CD-ROM drive 30.
- sub-CPU sub-central processing unit
- sub-memory 22 composed of a random access memory (RAM)
- Sub direct memory access controller sub DMAC: Direct Memory Access Controller
- R0M Read Only Memory
- programs such as operating system
- audio processing unit SPU : Sound Processing Unit
- ATM Asynchronous Transmission module
- auxiliary storage device input device 28, and CD-ROM drive 30.
- the path controller 10 is a device on the main path 1 for performing switching between the main bus 1 and the sub bus 2, and is open in an initial state.
- the main CPU 11 is a device on the main bus 1 that operates by a program on the main memory 12. This May The CPU 11 reads the boot program from the ROM 24 on the sub-bus 2 and executes the boot program because the path controller 10 is open at the time of startup, and the CD-ROM driver 30 The application program and necessary data are reproduced from the CD-ROM and loaded into the main memory 12 or the device on the sub bus 2.
- the main CPU 11 is equipped with a Geometry Transfer Engine (GTE) 17 that performs processing such as coordinate conversion, and its input / output unit is used to convert packets into data packets.
- GTE Geometry Transfer Engine
- PPE Programmable Packet Engine
- VLBF variable length read / write buffer
- the GTE 17 has, for example, a parallel operation mechanism that executes a plurality of operations in parallel, and performs high-speed operations such as coordinate conversion, light source calculation, matrix or vector in response to an operation request from the main CPU 11. Do. Then, the main CPU 11 defines a three-dimensional model as a combination of basic unit figures (polygons) such as a triangle and a quadrangle based on the calculation result by the GTE 17 and performs three-dimensional modeling. Create drawing instructions corresponding to each polygon for drawing an image. Then, the PPE 112 converts the drawing instruction into a packet and transfers it to the GPU 15 via the main path 1 as a command bucket.
- a parallel operation mechanism that executes a plurality of operations in parallel, and performs high-speed operations such as coordinate conversion, light source calculation, matrix or vector in response to an operation request from the main CPU 11.
- the main CPU 11 defines a three-dimensional model as a combination of basic unit figures (polygons) such as a triangle and a quadrangle based
- the main DMAC 13 is a device on the main bus 1 that controls DMA transfer for devices on the main bus 1 and the like. This main DMAC 13 also targets devices on subpath 2 when the bus controller 10 is open. I do.
- the GPU 15 is a device on the main bus 1 that functions as a rendering processor.
- This GPU 15 is provided with a programmable bucket engine (PPE) 152 whose input / output part is capable of changing the procedure of data bucketing and Z unbucketing.
- PPE programmable bucket engine
- the main CPU 1 1 or the command bucket and the object data sent from the main DMAC 13 are unpacketized by the PPE 152 described above.
- the GPU 15 interprets the drawing command sent as the above command packet, and calculates the colors of all pixels constituting the polygon from the color data of the vertices and the Z value indicating the depth. Calculate.
- a rendering process for writing the pixel data into the frame buffer 18 according to the Z value is performed.
- the GPU 15 also performs a coordinate conversion, a light source calculation, and the like on the three-dimensional image data sent as the object data by a preprocessor (not shown), and internally draws a drawing instruction corresponding to each polygon. It can also be created. Then, rendering processing is performed in the same manner as described above.
- the MDEC 14 is an IZO connection device that can operate in parallel with the CPU, and is a device on the main bus 1 that functions as an image decompression engine.
- the MDEC 14 decodes image data compressed and encoded by orthogonal transform such as discrete cosine transform.
- the sub CPU 21 is a device on the sub bus 2 that operates by a program on the sub memory 22.
- the above sub The DMAC 23 is a device on the sub-path 2 that controls DMA transfer for devices on the sub-bus 2 and the like. This sub-DMAC 23 can acquire the pass right only when the pass controller 10 is closed.
- the SPU 25 is a device on the sub bus 2 that functions as a sound processor. The SPU 25 reads out the sound source data from the sound memory 29 and outputs it in response to a sound command sent as a command bucket from the sub CPU 21 or the sub DMAC 23.
- the ATM 26 is a communication device on the sub-bus 2.
- the auxiliary storage device 27 is a data input / output device on the sub bus 2 and is composed of a nonvolatile memory such as a flash memory.
- the auxiliary storage device 27 temporarily stores data such as the progress of the game and the score.
- the input device 28 is a device for input from a man-machine interface such as a control pad and a mouse on the sub-bus 2 and other devices such as an image input and a voice input.
- the CD-ROM driver 30 reproduces an application program and necessary data from the CD-: ROM, which is a data input device on the sub path 2.
- this video game device performs geometric processing such as coordinate transformation, clipping, and light source calculation, and defines a three-dimensional model as a combination of basic unit figures (polygons) such as triangles and rectangles.
- a drawing command for drawing a 3D image is created, and a drawing command corresponding to each polygon is sent to the main path 1 as a command bucket.
- the geometry processing means is a main CPU 11 on the main bus 1.
- the GPU 15 forms rendering processing means for generating pixel data of each polygon based on the image command and performing a rendering process of writing the pixel data in the frame buffer 18 and drawing a graphic in the frame buffer 18.
- the PPE 112 of the main CPU 11 constituting the geometry processing means and the PPE 152 of the GPU 15 constituting the rendering processing means are shown in FIG. In addition, they are located between the input / output buffers 11 1, 15 1 and the internal registers 1 13, 153 by FIF 0 (First In First Out) memory in each arithmetic unit.
- the input / output buffer 111, 151 has a bit length suitable for the data transfer algorithm, and the internal registers 113, 153 have a bit length suitable for the operation. You.
- each PPE 112, 152 has an address section 112A, 152 A which designates input / output ports, buffers 111, 151, and internal registers 113, 153.
- the mask sections 1 12 B and 152 B, the shift sections 112 C and 152 C, the sign extension sections 112 D and 152 D, and various procedures for packetizing and unpacking data Based on the list of the program sections 1 12 E and 152 E in which the described list is written and the above program sections 1 12 E and 152 E, each section is controlled and read / write is controlled.
- control units 112 F and 152 F that operate in parallel and independent of arithmetic control, and follows the procedure shown in the above list of program units 112 E and 152 E to packet data. It is designed to convert data into packets / unpackets.
- the PPE 112 on the main CPU 11 buckets the drawing instruction created based on the operation result of GTE 17
- a packetization procedure suitable for the drawing instruction is specified by selecting a list in the above program section 112E, and the drawing instruction is formatted according to the procedure indicated by the specified list.
- tag information indicating the unpacking procedure corresponding to the bucketing procedure shown in the above list is added to the packet.
- the above command packet is reformatted and opened or unpacketized.
- three types of packing lists PLO, PL1 and PL2 are recorded.
- the vertex information (VX0, VY0, VZ0) generated as object data is stored in the internal register 113 of the main CPU 11 as shown in FIG. 4 (A).
- a procedure for packetizing the three-dimensional triangle information represented by 2) into the input / output buffer 111 and writing the packet information as a packet command is described.
- each vertex information VXO, VY0, VZ0, VX1, VY1, VZ1, VX1, VX2, VY2, VZ2 is calculated in 32 bits.
- NX 0, ⁇ , ⁇ ⁇ 0, ⁇ XI, NY1, NZ1, NX2, NY2, NZ2 are packed into 16 bits for packing, and the color information R0, GO, BO, Rl, G 1, B l, R 2, G 2, and B 2 are 16 bits for each vertex, ie, 5 bits each for R, G, and B, and a total of control bits used for processing used for translucency.
- the knocking list PL1 includes the vertex data (VX0, VY0, VZ0), the difference data ( ⁇ 1, ⁇ 1, ⁇ ⁇ 1), ( ⁇ ⁇ VX 2, ⁇ 2, ⁇ 2), ( ⁇ X3, ⁇ 3, ⁇ 3) .
- each vertex information VX0, V ⁇ 0, VZ0 calculated in 32 bits is packed into 16 bits, and packed in 32 bits.
- each vertex coordinate X0, Y0, XI, Y1, X2, Y2, X3, Y3 calculated in 32 bits is converted into 16 bits.
- each texture coordinate U0, V0, Ul, VI, U2, V2, U3, V3 calculated with 16 bits and each color information R0, GO, BO, Rl, G1, Bl, R2, G2, B2, R3, G3, B3 are packed into 8 bits for packing, and the unpacking list corresponding to the corresponding packing list PL2 Tag information TAG specifying UL 2 is added.
- the program section 152 E in the PPE 152 on the GPU 15 side includes three types of unpacking lists PU 0, PU 1, and PU 2 corresponding to the packing lists PL 0, PL 1, and PL 2. Is recorded.
- a packet command transferred to the input / output buffer 151 is a 32-bit vertex based on the tag information TAG in the unpacking list UL0.
- Information VX0, VY0, VZ0), (VX1, VY1, VZ1), (VX2, VY2, VZ2), normal (NX0, NY0, NZ0), (NX1, NY) 1, NZ l), (NX2, NY2, NZ2), 16-bit color information (R0, G0, B0), (R1, G1, B1), R2, G2, B
- the unpacking list UL1 includes a packet command transmitted to the input / output buffer 151 as a 32-bit vertex based on its tag information TAG.
- Data VX 0, VY 0, VZ 0
- differential data ⁇ 1, ⁇ 1, ⁇ 1), ( ⁇ VX2, ⁇ 2, ⁇ 2), ( ⁇ 3, ⁇ 3, ⁇ 3) It describes the procedure for developing triangle information and writing it to the internal register 153.
- the bucket list transmitted to the input / output buffer 151 has 32 bits based on the tag information TAG, as shown in ( ⁇ ) of FIG. Vertex coordinates (X0, Y0), (XI, Y1), (X2, Y2), (X3, Y3) and 16-bit texture coordinates (U0, V) corresponding to each vertex 0), (Ul, VI), (U2, V2), (U3, V3) and color information (R0, GO, BO), (R1, G1, B1), (R It describes the procedure for expanding into square information composed of (2, G 2, B 2) and (R 3, G 3, B 3) and writing it to the internal register 153.
- the VLB F 117 provided in the input / output section of the main CPU 11 has a buffer corresponding to the longest burst transfer as shown in FIGS. 7A and 7B. It consists of a Donor software 117R, a writer, a * 117W, and a burst length setting register 117RL, 117WL for setting each burst length.
- the burst length setting register 1117RL, 117WL is set to a length suitable for reading and creating the bucket to be processed in the routine at the beginning of the specific routine to be cached on. As a result, it is possible to perform a burst transfer suitable for the packet format and improve the transfer efficiency.
- Such a video game device to which the present invention is applied has, for example, a configuration as shown in a plan view of FIG. 8, a front view of FIG. 9, and a side view of FIG. That is, as shown in FIG. 8, the video game device 201 basically has a device main body 202 and an operation connected to the device main body 202 via a cable 227. It is composed of a device 2 17. At the center of the upper surface of the device main body 202, a disk mounting portion 203 is provided, and a CD-ROM 251 as shown in FIG. 11 is mounted therein. On the left side of the disc mounting unit 203, a power switch 205 operated when turning on or off the power of the device, and a reset switch 204 operated when the game is reset once. Is provided. Further, on the right side of the disk mounting portion 203, a disk operation switch 206 which is operated when the CD-ROM 251 is attached to and detached from the disk mounting portion 203 is provided.
- connecting portions 207A and 207B are provided on the front face of the apparatus main body 202. These connecting portions 207 A and 207 B are provided with a connecting terminal portion 226 provided at the end of a cable 227 derived from the operating device 217 and a memory card.
- a connection terminal insertion part 2 12 and a recording insertion part 208 are provided to connect the recording devices 228 to each other. That is, two operation devices 2 17 and two recording devices 2 28 can be connected to the device main body 202.
- connection terminal section 2 26 and the recording device 2 28 are mounted on the right connection section 2 07 B, and the connection terminal section is mounted on the left connection section 2 07 A.
- the figure shows a state in which neither 2 2 6 nor the recording device 2 2 8 are mounted.
- a shirt 209 is provided in the recording insertion section 208 for mounting the recording device 228, and the recording device 238 is attached to the main body 202 of the apparatus. 2 3 At the tip of 8, the shirt 209 is pushed in, so that it can be worn.
- connection terminal portion 226 and the gripping portion 242A of the recording device 238 are each subjected to a non-slip process such as knurling. As shown in the side view of FIG. 10, the lengths L of the connection terminal portions 226 and the recording device 238 are substantially the same.
- the operating device 17 is provided with support portions 220, 221 that are gripped by left and right hands, and the operating portions 218, 219 are provided at the tips of the support portions 220, 221. Is provided.
- 224 and 225 are operated with the forefinger of the left and right hands, and the operation units 218 and 219 are operated with the left and right thumbs.
- the operation units 218 and 219 there is a select switch 222 operated when performing a select operation during a game, and a start switch 222 operated when starting a game.
- a select switch 222 operated when performing a select operation during a game
- a start switch 222 operated when starting a game.
- Three are provided.
- the CD-ROM 251 mounted on the disk mounting unit 203 is reproduced by the CD-ROM drive 30.
- the operating device 217 corresponds to the input device 28 described above
- the recording device 228 corresponds to the auxiliary storage device 27 described above.
Description
Claims
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE69725807T DE69725807T2 (de) | 1996-02-29 | 1997-02-25 | Bildprozessor und bildverarbeitungsverfahren |
JP53078697A JP3620857B2 (ja) | 1996-02-29 | 1997-02-25 | 画像処理装置及び画像処理方法 |
US08/945,580 US6211890B1 (en) | 1996-02-29 | 1997-02-25 | Image processor and image processing method |
CA002218227A CA2218227C (en) | 1996-02-29 | 1997-02-25 | Image processor and image processing method |
AT97904636T ATE253235T1 (de) | 1996-02-29 | 1997-02-25 | Bildprozessor und bildverarbeitungsverfahren |
EP97904636A EP0827067B1 (en) | 1996-02-29 | 1997-02-25 | Image processor and image processing method |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8/43760 | 1996-02-29 | ||
JP4376096 | 1996-02-29 |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
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US08/945,580 A-371-Of-International US6211890B1 (en) | 1996-02-29 | 1997-02-25 | Image processor and image processing method |
US09/778,159 Continuation US6369823B2 (en) | 1996-02-29 | 2001-02-05 | Picture processing apparatus and picture processing method |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1997032248A1 true WO1997032248A1 (fr) | 1997-09-04 |
Family
ID=12672725
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/JP1997/000535 WO1997032248A1 (fr) | 1996-02-29 | 1997-02-25 | Processeur d'images et procede de traitement d'images |
Country Status (11)
Country | Link |
---|---|
US (2) | US6211890B1 (ja) |
EP (2) | EP1387287B1 (ja) |
JP (1) | JP3620857B2 (ja) |
KR (1) | KR100506959B1 (ja) |
CN (1) | CN1209736C (ja) |
AT (2) | ATE404922T1 (ja) |
CA (1) | CA2218227C (ja) |
DE (2) | DE69738920D1 (ja) |
ES (1) | ES2205176T3 (ja) |
TW (1) | TW329497B (ja) |
WO (1) | WO1997032248A1 (ja) |
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- 1997-02-25 DE DE69725807T patent/DE69725807T2/de not_active Expired - Lifetime
- 1997-02-25 AT AT03078283T patent/ATE404922T1/de not_active IP Right Cessation
- 1997-02-25 KR KR1019970707688A patent/KR100506959B1/ko not_active IP Right Cessation
- 1997-02-25 AT AT97904636T patent/ATE253235T1/de active
- 1997-02-25 US US08/945,580 patent/US6211890B1/en not_active Expired - Lifetime
- 1997-02-25 CA CA002218227A patent/CA2218227C/en not_active Expired - Lifetime
- 1997-02-25 CN CNB971900884A patent/CN1209736C/zh not_active Expired - Lifetime
- 1997-02-25 EP EP03078283A patent/EP1387287B1/en not_active Expired - Lifetime
- 1997-02-25 EP EP97904636A patent/EP0827067B1/en not_active Expired - Lifetime
- 1997-02-25 JP JP53078697A patent/JP3620857B2/ja not_active Expired - Lifetime
- 1997-02-25 ES ES97904636T patent/ES2205176T3/es not_active Expired - Lifetime
- 1997-02-26 TW TW086102345A patent/TW329497B/zh not_active IP Right Cessation
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2001
- 2001-02-05 US US09/778,159 patent/US6369823B2/en not_active Expired - Lifetime
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JPH08171657A (ja) * | 1994-12-19 | 1996-07-02 | Sony Corp | 画像情報生成方法、及び記録媒体 |
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TW329497B (en) | 1998-04-11 |
ATE404922T1 (de) | 2008-08-15 |
KR19990008163A (ko) | 1999-01-25 |
CA2218227C (en) | 2002-10-01 |
US20010005206A1 (en) | 2001-06-28 |
EP0827067A1 (en) | 1998-03-04 |
US6369823B2 (en) | 2002-04-09 |
JP3620857B2 (ja) | 2005-02-16 |
CA2218227A1 (en) | 1997-09-04 |
DE69725807T2 (de) | 2004-08-05 |
EP0827067B1 (en) | 2003-10-29 |
CN1209736C (zh) | 2005-07-06 |
ES2205176T3 (es) | 2004-05-01 |
DE69738920D1 (de) | 2008-09-25 |
ATE253235T1 (de) | 2003-11-15 |
US6211890B1 (en) | 2001-04-03 |
EP1387287B1 (en) | 2008-08-13 |
EP0827067A4 (en) | 1998-06-24 |
EP1387287A1 (en) | 2004-02-04 |
KR100506959B1 (ko) | 2005-11-11 |
DE69725807D1 (de) | 2003-12-04 |
CN1180426A (zh) | 1998-04-29 |
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