WO1997041592A1

WO1997041592A1 - A fluorinated oxide low permittivity dielectric stack for reduced capacitive coupling

Info

Publication number: WO1997041592A1
Application number: PCT/US1996/020485
Authority: WO
Inventors: Robert Dawson; Fred N. Hause; Basab Bandyopadhyay; Mark W. Michael; H. Jim Fulford; William S. Brennan
Original assignee: Advanced Micro Devices, Inc.
Priority date: 1996-05-02
Filing date: 1996-12-20
Publication date: 1997-11-06

Abstract

A low permittivity interlevel structure comprising a dielectric formed on the topography of a semiconductor substrate. The dielectric comprises a lower region proximal to the semiconductor substrate, an intermediate region comprised of an oxide into which fluorine is incorporated in an atomic concentration of approximately four to ten percent, and an upper region. A method of forming the dielectric structure includes forming a first interconnect level on a substrate. A first dielectric layer, preferably a CVD oxide, is formed on the topography defined by the first interconnect and the substrate. A second dielectric layer, having a dielectric constant lower than the first dielectric layer, is then formed on the first dielectric layer. A third dielectric layer is formed on the second dielectric layer. The second dielectric layer is preferably formed in a CVD chamber from a silane or TEOS source and a fluorinating material such as SiF4.

Description

A FLUORINATED OXIDE LOW PERMITTIVITY DIELECTRIC STACK FOR REDUCED CAPACITIVE COUPLING

BACKGROUND OF THE INVENTION

1 Field of the Invention

This invention relates to semiconductor device fabrication and more particularly to a low permittivity mterlevel dielectric structure and method for producing the same

2 Description ofthe Relevant Art

An integrated circuit includes numerous conductors extending across the topography of a monolithic substrate. A set of interconnect lines (.or conductors) which serve to electrically connect two or more components within a svstem is generally referred to as a "bus^". A collection ot voltage levels are forwarded across the conductors to allow proper operation of the components. For example, a microprocessor is connected to memories and input output devices by certain bus structures. There are numerous types of busses which are classified according to their operation. Examples of well-known types of busses include address busses, data busses, and control busses.

Conductors within a bus generally extend parallel to each other across the semiconductor topography. The conductors are isolated from each other and from underlying conductive elements by a dielectric, a suitable dielectric being, for example, silicon dioxide ("oxide"). Conductors are thereby lithography patterned across the semiconductor topography, wherein the topography compπses a substrate with a dielectric placed thereon. The topography can also include one or more layers of conductors which are sealed by an upper layer of dielectric mateπal Accordingly, the layers of conductors overlaid with a dielectric present a topography upon which a subsequent layer of conductors can be patterned.

Conductors are made from an electrically conductive material, a suitable material includes Al. Ti. Ta, W, Mo. polysilicon. or a combination thereof. Substrate includes any type of material which can retain dopant ions and the isolated conductivity regions brought about by those ions. Typically, substrate is a silicon-based mateπal which receives p-type or n-type ions.

Generally speaking, interconnect lines (or conductors) are fashioned upon the topography and spaced above an underlying conductor or substrate by a dielectric of thickness T_d|. Each conductor is dielectncally spaced from other conductors within the same level of conductors by a distance T ,. Accordingly, mterlevel capacitance C_LS (i.e., capacitance between conductors on different levels) is determined as follows.

C_LS * εW, L/T_dl (Eq. 1 )

Further, the imralevel capacitance Cn (i e., capacitance between conductors on the same level) is determmed as follows: C_LL * εT\ L/T_d2 (Eq. 2)

. where ε is the permittivity ofthe dielectric material (the dielectric material between the conductor and substrate or the dielectric mateπal between conductors), W, is the conductor width. T_c is the conductor thickness, and L is the conductor length. Resistance ofthe conductor is calculated as follows:

R = (pL)/W,T_c (Eq. 3)

, where p represents resistivity ofthe conductive material, and T_c is the interconnect thickness. Combinations of equations 1 and 3, and/or equations 2 and 3 indicate the propagation delay of a conductor as follows:

RC, , = reL-W, T_d2 (Eq. 4)

Propagation delay is an important characteristic of an integrated circuit since it limits the speed (frequency) at which the circuit or circuits can operate The shoπer the propagation delay, the higher the speed of the circuit or circuits It is therefore important that propagation delay be minimized as much as possible within the geometric constraints ofthe semiconductor topography

Equation 4 shows that the propagation delay of a circuit is proportional to the parasitic capacitance values (C_LL) between laterally spaced conductors, and parasitic capacitance values (C_LS) between vertically spaced conductors or between a conductor and the underlying subsrrate. As circuit density increases, lateral spacing and vertical spacing between conductors decrease and capacitance Q [ increases. Meanwhile, planarization mandates to some extent a decrease in vertical spacing Shallow trench processing, recessed LOCOS processing, and multi- layered interlevel dielectrics can bring about an overall reduction in veπical spacing and therefore an increase m C_LS Depending upon the geometries associated with a particular device, either C_LL or C_Ls can reduce the performance ofthe device Integrated circuits which employ narrow interconnect spacings thereby define C_LL as a predominant capacitance, and integrated circuits which employ thin interlevel dielectrics define C_Ls as a predominant capacitance.

It is therefore important to minimize propagation delay especially in critical speed paths. Given the constraints of chemical compositions, it is not readily plausible to reduce the resistivity p of conductor mateπals. Geometric constraints make it difficult to increase conductor thickness T_c or dielectric thickness T_dl or T^. Still further, instead of reducing length L of a conductor, most modem integrated circuits employ long interconnect lines which compound the propagation delay problems. Accordingly, a need arises for instituting a reduction in propagation delay but within the chemical and geometric constraints of existing fabrication processes. It is therefore desirable that a fabrication process be derived which can reduce propagation by reducing the permittivity ε of dielectric material. More specifically, the desired process must be one which reduces permittivity of dielectric material arranged between horizontally displaced or vertically displaced conductors As such, it would be desirable to employ a fabrication technique in which dielectrics between conductors achieve low permittivity

SUMMARY OF THE INVENTION

The problems outlined above are in large part addressed by a dielectric fabrication process that produces a low permittivirv dielectric between the interconnect lines arranged within the same elevation level C'intralevel permittivity ') and between interconnect lines within two separate planes or levels ("interlevel permittivirv"') A patterned laser of conductive material which forms a first interconnect level is formed on a semiconductor substrate Next, a first dielectric is formed on the substrate and the first interconnect level The first dielectπc preferablv comprises Sι0₂ formed from a silane or TEOS source in a plasma enhanced chemical vapor deposition chamber at approximately 375° C In one embodiment, the first dielectπc laver is 100 to 1000 angstroms thick

A second dielectric laver is then formed upon the first dielectric iayer The permittivity of the second dielectric is lower than the permittivirv of the first dielectric The second dielectric layer is preferablv comprised of a CVD o\ιde into which fluorine is incoφorated The atomic percentage of fluorine incorporated into the second dielectric layer in one embodiment is between 4% and 10% and the thickness ofthe second dielectric layer is preferablv greater than 1000 angstroms

A thσd dielectric, preferably a non-fluoπnated CVD oxide formed from a silane or TEOS source, is then formed upon the second dielectπc to provide a thermodynamicaily stable capping layer for the second dielectric layer in one embodiment, the third dielectπc is preferably between 500 to 3500 angstroms in thickness Formation ofthe third dielectπc layer can be followed by a planaπzation step preferably achieved with a chemical mechanical polish

The dielectric "stack (comprised of the first, second, and third dielectric layers) has a dielectπc constant that is preterably less than 3 5 (compared to conventional CVD oxides which have dielectπc constants in the range of 3.8 to 4 5) In one embodiment ofthe process, the dielectric stack is formed in a single deposition step with the fluorine bemg mcorporated in s-itu during an intermediate portion ofthe deposition cycle The third dielectric layer is provided because it is believed that fluorinated oxides may become unstable in air when the percentage of fluorme incorporated mto the film exceeds approximately six to eight percent

Broadly speaking, the present invention contemplates an interlevel dielectric compnsmg a first dielectπc layer formed on a topography cooperatively defined by a semiconductor substrate and a patterned first interconnect level formed on the semiconductor substrate Preferably, the first dielectric layer comprises CVD oxide formed from a silane or TEOS source A second dielectric layer, having a dielectric constant less than the dielectric constant ofthe first dielectric layer, is formed on the first dielectric layer. In an exemplary embodiment, the lower permittivity ofthe second dielectric layer is achieved by incoφorating fluorine into a CVD oxide in an atomic concentration ot approximately four to ten percent. A third dielectric layer is formed on the second dielectric layer.

The present invention further contemplates a method of forming an interlevel dielectric on a substantially planar first set of interconnects that is formed on an upper surface of a semiconductor substrate. A first dielectric layer, preferably a CVD oxide, is formed on the topography defined by the first set of interconnects and the semiconductor substrate. A second dielectric layer is then formed on the first dielectric ia>er The dielectric constant ofthe second dielectπc layer is lower than the dielectric constant of the first dielectric layer The second dielectric layer is preferably an oxide deposited in a CVD chamber using a TEOS or silane source coupled with a fluorinating material to produce an oxide layer having an atomic concentration of fluorine of approximately four to ten percent. A third dielectπc is then formed on the second dielectπc layer

The present invention still further contemplates a method of forming a interlevel dielectric comprising forming a lower, intermediate, and upper sections in a single CVD process wherein a fluorinating mateπal. such as SiF₄, is introduced into the chamber during an intermediate stage ofthe deposition

The present invention still further contemplates an interlevel dielectric comprising an oxide formed on a topography cooperatively defined by a semiconductor substrate and a first level interconnect, wherein the oxide comprises lower, intermediate, and upper regions, the intermediate region containing an approximately four to ten percent atomic concentration of fluorine.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects and advantages ofthe invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which.

Fig. 1 is a partial cross-sectional view of a semiconductor substrate upon vvhich a first level of interconnects and an oxide layer have been formed;

Fig. 2 is a processing step subsequent to that shown in Fig. 1 in which a second dielectric layer has been formed on the first dielectric layer, the second layer having a lower permittivity than the first dielectric;

Fig. 3 is a processing step subsequent to that shown in Fig. 2 in which a third dielectric has been formed on the second dielectric;

Fig.4 is a processing step subsequent to that shown in Fig. 3 in which an upper surface ofthe third dielectric has been planaπzed to produce a substantially planar upper surface;

Fig. 5 is a processing step subsequent to that shown in Fig. 4 in which a contact has been formed through the third, second, and first dielectrics to the first interconnect level: and Fig 6 is a processing step subsequent to that shown in Fig 5 in which the contact has been filled with a conductiv e material and a second level of interconnect has been formed on the third dielectπc

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail It should be understood however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims

DETAILED DFSCRIPTION OF THE DRAWINGS

Fig 1 shows semiconductor substrate 100. a first interconnect level 102. and first dielectric 104 Substrate 100 is tv picallv comprised of a single crvstal silicon water into which transistors and isolation regions are formed through a series ot processing steps well known in the an An upper surface ot substance 100 mav include a dielectπc for isolating first interconnect level 102 from the underlvmg transistor regions This dielectric typically has a plurality of contact openings for selectively coupling first interconnect level 102 to the transistor regions First level interconnect 102 compπses a pluraiitv of interconnect lines that connect the underlying transistors in a specified manner First interconnect level 102 is typically formed through a physical vapor deposition step using an aluminum target After first inierconncct level 102 is deposited, photoresist is deposited on the first interconnect level 102 and patterned in a photolithography step Individual interconnect lines are then formed in an etch step After formation of first interconnect level 102. a first dielectric 104 is formed upon the topography cooperatively defined b\ substrate 100 and first interconnect level 102 Formation of first dielectric 104 is preferablv earned out by depositing CVD oxide formed from a TEOS or a silane source

Fig 2 shows a processing step subsequent to that shown in Fig 1 in which a second dielectric 106 has been formed on first dielectric 104 Second dielectric 106 has a dielectric constant K₂ which is less than the dielectπc constant K| of first dielectric 104 In one embodiment first dielectric 104 is approximately 100 - 1000 angstroms m thickness while second dielectric 106 is approximately 3,000 - 10,000 angstroms thick Like first dielectric 104. second dielectric 106 is preferably formed in a CVD chamber with a TEOS or a silane source To achieve a lower permittivity film however, one embodiment incoφorates a fluorinating material into the CVD chamber during formation of second dielectric 106 The fluorinating material can be SιF₄, CF₄, or C₂F₆ in various embodiments Incoφorating fluorme mto second dielectric 106 is believed to result in a lower permittivity dielectric. Formation of second dielectric 106 is controlled such that the atomic concentration of fluorine in second dielectric 106 is preferably between 4% and 10% While incoφorating higher percentages of fluorme mto second dielectric 106 is believed to result in a lower permittivity film it is also believed that the fluorinated oxide may become thermodynamically unstable at fluorine concentrations greater than approximately 6-8% Accordingly , a first embodiment of second dielectric 106 has a low concentration of fluorine, low concentration being defined as less than 6% The low concentration embodiment might have the advantage of not requiring a third dielectπc formed on top of the fluorinated film as discussed below In a high concentration embodiment (where high concentration is defined as greater than 6%), second dielectric 106 mav require formation of a passivatmg film on top as disclosed below

Fig 3 shows a processing step subsequent to Fig 2 in which third dielectric 108 has been formed on > second dielectric 106 Third dielectric 108 is preterably formed m a CVD chamber with a TEOS or silane source, wherein the chamber has been purged of fluorinating material Third dielectric 108 has an upper surface 1 10 which may be planaπzed using a chemical mechanical polish or a resist etchback process to achieve a substantially planar upper surface 1 10 as shown in Fig 4 It is believed that third dielectπc 108 provides a thermodvnamicallv stable capping layer for fluorinated oxide 106 In embodiments in which fluorinated film 106 has a concentration of 0 fluorine below six percent third dielectric 108 mav be optionallv eliminated

First dielectric 104, second dielectric 106 and third dielectric 108 can be formed in a single CVD deposition process in which a fluorinating material is introduced into the CVD chamber duπng an intermediate stage of the deposition In this embodiment interlevel dielectric 107 is formed compnsmg lower region 107a, j intermediate region 107b, and upper region 107c wherein intermediate region 107b has a fluorine concentration of approximately 4% to 10%

Turning now to Fig 5, a processing step subsequent to that of Fig 4 is shown in which contact via 1 12 has been etched mto third dielectric 108, second dielectric 106 and first dielectric 104 to first interconnect level 102 0 The formation of contact via 1 12 is preferably accomplished with a plasma etch process Formation of contact via 1 12 exposes region 1 14 of second dielectric 106 In those embodiments in which a second dielectric 106 has a high concentration of fluorine, it may be undesirable to expose regions 1 14 since second dielectric 106 may be thermodvnamicallv unstable Accordingly, a passivatmg film 1 16. as shown in Fig 6, can be formed on the sidewall 1 13 of contact via 1 12 Passivatmg film 1 16 can be comprised of Sι0₂ formed in a CVD chamber void of 5 fluorinating material After formation of contact via 1 12 and the optional formation of passivatmg layer 1 16, contact via 1 12 is filled with a conductive material 1 18 Conductive material 1 18 is commonly formed in a CVD process with a tungsten source After deposition of conductive material 1 18, a mechanical polish can be performed to remove conductive material 1 18 from regions exterior to contact via 1 12 Subsequentlv. a second interconnect level can be formed, preferably from a PVD aluminum, and patterned as shown in Fig 6 0

As would be obvious to one skilled in the an having the benefit of this disclosure, the present invention discloses a novel and useful method of incoφorating a low permittivity dielectric into an interlevel structure of a semiconductor device The embodiments shown are merely exemplary of a single form of numerous forms Vanous modifications and changes may be made to the configurations shown as would be obvious to a person 5 skilled in the an havmg the benefit of this disclosure It is intended that the following claims be inteφreted to embrace all such modifications and changes and accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense

Claims

WHAT IS CLAIMED IS

1 An interlevel dielectric comprising

5 a first interconnect level formed and patterned on a semiconductor substrate, said first interconnect level and said substrate cooperatively defining a topography;

a first dielectric layer formed on said topography,

) a second dielectric layer formed on said first dielectric layer and having a dielectric constant less than a dielectric constant of said first dielectric laver wherein said second dielectπc layer comprises an oxide having an atomic concentration of fluorine between 4 and 10 percent, and

a third dielectπc laver formed on said second dielectric

I i

2 The dielectric of claim I wherein said first and third dielectric layers comprise oxide

3 The dielectric of claim 1 wherein said dielectric stack contains one or more contact via each said one or more contact via having a substantially cylindrical sidewall extending from an upper surface of said third 0 dielectric to said first interconnect level

4 The dielectric of claim 3 further comprising a passivatmg film on said substantially cylindrical sidewall of each said one or more contact via

25 5 The dielectric of claim 4 wherein said passivatmg film comprises an oxide

6 The interlevel dielectric of claim 1 wherein said interlevel dielectric has a composite dielectπc constant less than 3 5

30 7 A method of forming an interlevel dielectric comprising the steps of

forming a substantially planar first set of interconnects on an upper surface of a semiconductor substrate, said first set of interconnects and said upper surface of said substrate cooperatively define a topography;

35 forming a first dielectric layer on and substantially confoπnal to said topography,

forming a second dielectric layer having a dielecrπc constant less than or equal to a dielectric constant of said first dielectric laver on said first dielectric layer by depositing an oxide having an atomic 40 concentration of fluorine of approximately 4 to 10 percent on said first dielectric layer, and forming a third dielectπc layer on said second dielectric layer, whereby said first, second, and third dielectπc layers cooperatively define a dielectric stack

8 The method of claim 7 wherein the step of forming said first and third dielectric lavers comprises depositing an oxide in a chemical vapor deposition chamber using a TEOS or silane source

9 The method of claim 7 wherein said depositing of said second dielectric is accomplished in a chemical vapor deposition chamber using a TEOS or silane source gas into which fluorine is incoφorated

10 The method of claim 7 wherein the steps of forming said first, second, and third dielectric lavers are achieved in a single chemical vapor deposition cvcle using a TEOS or silane source

1 1 The method of claim 10 wherein said single chemical vapor deposition cvcle comprises an initial stage, an intermediate stage during which a fluorinating material is introduced into said chamber, and a latter stage prior to vvhich said fluorinating maieπal is purged from said chamber

12 The method of claim 7 further comprising the step of plasma etching one or more contact vias into said first, second, and third dielectric layers to said first interconnect level wherein each said one or more contact vias has a substantially cylindrical sidewall

13 The method of claim 12 further comprising forming a passivatmg film on each said one or more substantially cylindrical sidewalls

14 The method of claim 13 wherein the step of forming said passivatmg film comprises depositing an oxide on each said one or more substantially cylindrical sidewalls

15 The method of claim 7 wherein said interlevel dielectric has a composite dielectπc constant less than 3 5

16 An interlevel dielectric formed by the process of claim 7

17 An interlevel dielectric comprising

an oxide formed on a topography cooperatively defined by a semiconductor substrate and a first level interconnect formed and patterned on said substrate, wherein said oxide comprises a lower region, an intermediate region, and an upper region and wherein said intermediate region of said oxide has a atomic concentration of fluorme of approximately four to ten percent 18 The interlevel dielectric of claim 17 wherein said intermediate region ot said oxide is formed in a chemical vapor deposition chamber into which a fluorinating material is introduced.

19 The interlevel dielectπc of claim 18 wherein said fluorinating mateπal comprises SιF₄