WO1997044824A1 - High-density, integrated circuit chip package - Google Patents

High-density, integrated circuit chip package Download PDF

Info

Publication number
WO1997044824A1
WO1997044824A1 PCT/US1996/007290 US9607290W WO9744824A1 WO 1997044824 A1 WO1997044824 A1 WO 1997044824A1 US 9607290 W US9607290 W US 9607290W WO 9744824 A1 WO9744824 A1 WO 9744824A1
Authority
WO
WIPO (PCT)
Prior art keywords
package
integrated circuit
carrier
circuit chips
thermally conductive
Prior art date
Application number
PCT/US1996/007290
Other languages
French (fr)
Inventor
Sanjeev Sathe
Bahgat Sammakia
Morris Anschel
Original Assignee
Ibm Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm Corporation filed Critical Ibm Corporation
Priority to AU58665/96A priority Critical patent/AU5866596A/en
Publication of WO1997044824A1 publication Critical patent/WO1997044824A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5387—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors

Definitions

  • the present invention relates to a high-density package for
  • the present invention relates to a
  • the different types of memory generally include integrated circuit
  • the integrated circuit chips are made smaller and smaller in dimension, and yet
  • Another object of the present invention is to provide a high-
  • a feature of the present invention is to use a thermally
  • Still another feature of the present invention is to mount the
  • stiffener so as to increase the number of integrated circuit chips that may be
  • Still another feature of the present invention is to attach the
  • a further object of the present invention is to provide a
  • Figure 1 is a top view of a thermally conductive stiffener used
  • Figure 2 is a top view of a stiffener used for mounting a plurality
  • Figure 3 is a side view, partially in section, of a high-density
  • Figure 4 is a side view, partially in section, of an embodiment
  • FIG. 5 is a side view, partially in section, of another embodi ⁇
  • Figure 6 is a side view, partially in section, of a high-density
  • package including a plurality of stacked packages.
  • a thermally conductive stiffener 10 is provided with a plurality
  • thermally conductive stiffener is shown in the side view in Figure 3, with
  • thermally conductive member 10 has a pair
  • the integrated circuit chips 20 are shown mounted in the upper side.
  • the integrated circuit chips 20 may be mounted in the areas 12
  • the carrier 30 is bent around the member 10 so that it faces both
  • the carrier 30 will have an electrically conductive
  • the carrier 30 is connected to the other surfaces of the integrated circuit chips
  • solder bumps 21 in a conventional manner such as controlled-
  • C4 collapse-chip-connection
  • wire bond wire bond
  • the carrier 30 in Figure 3 is a flexible carrier
  • the carrier 30 may be connected to other carriers or a mother board
  • solder balls 22 shown connected to the bottom of the carrier in
  • the member 10 can have a single strip of integrated circuit
  • a member 10' can have a plurality
  • the member 10 is made of a high thermally conductive
  • member 10 in Figure 3 not only serves to provide heat dissipation, it also serves to provide heat dissipation, it also serves to provide heat dissipation, it also serves to provide heat dissipation, it also serves to provide heat dissipation, it also serves to provide heat dissipation, it also serves to provide heat dissipation, it also serves to provide heat dissipation, it also serves to provide heat dissipation, it also
  • stiffening member 10 may also have fins, extensions or heat pipes attached if
  • the solder balls 22 may be used to attach the carrier 30 to a
  • the carrier is formed in two parts 40 and 50.
  • the carrier can be a printed
  • circuit board made of FR4 material which is a metallic or copper plane
  • the stiffener 10 is made of thermally
  • the member 60 is formed with a plurality of channels 61
  • the channels 61 may
  • flexible carrier 30 is used for facing the opposite sides of the stiffener 60 and
  • Wire bonds may also be used for this purpose.
  • thermally conductive stiffener member which is able to dissipate quickly the
  • circuit chips may be put into the same sized volume previously used.
  • thermal conductivity of the mounting stiffener member permits such an
  • the printed circuit board material, FR4 provides

Abstract

A high-density package for integrated circuit chips (20) is provided. A plurality of integrated circuit chips (20) are mounted on opposite sides of a thermally conductive member (10) which serves as a stiffener for the package. A carrier member (30) is provided with a preselected, electrically conductive pattern, and is arranged to face a surface of each of the integrated circuit chips (20) and to be electrically thereto. This forms a compact package with heat dissipation properties.

Description

HIGH-DENSITY, INTEGRATED CIRCUIT CHIP PACKAGE
TECHNICAL FIELD
The present invention relates to a high-density package for
integrated circuit chips. More particularly, the present invention relates to a
high-density package for integrated circuit chips with thermal enhancement
capabilities.
BACKGROUND OF THE INVENTION
The field of computers has made substantial improvements
throughout the years. Most of the improvements deal with increasing the
memory capacity of the computers. At the same time, there is great effort in
decreasing the size of the computers so that portable computers and notebook-
sized computers presently have substantial memory capacity, easily equaling the
capacity of desktop computers of just a few years ago.
The different types of memory generally include integrated circuit
chips which are mounted on printed circuit boards or other types of carriers.
The integrated circuit chips are made smaller and smaller in dimension, and yet
carry more and more electronic elements thereon. As the number of integrated
circuit chips on a carrier increases, the heat generated by such chips poses a substantial problem. Clearly, excessive heat will adversely affect the operation
of the integrated circuits.
Therefore, the drive for increased memory capacity leads to more
integrated circuits in smaller and smaller areas. This poses substantial problems
to designers of high-density packages for integrated circuit chips.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide
a high-density package for integrated circuit chips.
Another object of the present invention is to provide a high-
density package which has substantially improved thermal capabilities.
A feature of the present invention is to use a thermally
conductive stiffener for mounting the integrated circuit chips thereon.
Still another feature of the present invention is to mount the
integrated circuit chips on opposite surfaces of the thermally conductive
stiffener, so as to increase the number of integrated circuit chips that may be
mounted in a specific volume of the high-density package.
Still another feature of the present invention is to attach the
integrated circuits mounted on the thermally conductive stiffener to a carrier member which can make electrical contact with the integrated circuit chips
mounted on both sides of the thermally conductive stiffener.
Still, a further object of the present invention is to provide a
high-density package which may be stacked with other similar high-density
packages and mounted on a mother board for use as memory in a computer, for
example.
BRIEF DESCRIPTION OF THE DRAWINGS
These and other objects, features, and advantages of the present
invention will become apparent upon further consideration of the following
detailed description of the invention, when read in conjunction with the figures
in which:
Figure 1 is a top view of a thermally conductive stiffener used
for mounting integrated circuit chips in accordance with the first embodiment
of the present invention;
Figure 2 is a top view of a stiffener used for mounting a plurality
of columns of integrated circuit chips in accordance with the present invention;
Figure 3 is a side view, partially in section, of a high-density
package constructed in accordance with an embodiment of the present invention, showing the thermally conductive stiffener, the integrated circuit chips, and a
carrier;
Figure 4 is a side view, partially in section, of an embodiment
similar to that of Figure 3, with a different type of carrier;
Figure 5 is a side view, partially in section, of another embodi¬
ment of the stiffener with cooling passages of the high-density package; and
Figure 6 is a side view, partially in section, of a high-density
package including a plurality of stacked packages.
DESCRIPTION OF THE INVENTION
Referring to the drawings, and more particularly to Figure 1 , it
can be seen that a thermally conductive stiffener 10 is provided with a plurality
of areas 12 adapted to mount an integrated circuit package thereon. The
thermally conductive stiffener is shown in the side view in Figure 3, with
integrated circuit chips 20 mounted thereon.
It can be seen that the thermally conductive member 10 has a pair
of opposite sides 11 and 13. In Figure 3, 11 is the bottom side, whereas 13 is
the upper side. The integrated circuit chips 20 are shown mounted in the
preformed areas 12 on both sides of the member 10. Thus, a plurality of
integrated circuit chips are shown mounted in Figure 3, such chips being
mounted on the pair of opposite sides of the member 10.
The integrated circuit chips 20 may be mounted in the areas 12
by using a high-thermal conductivity paste 16 arranged between one of the
surfaces of the integrated circuit chips 20 and the member 10. The other surface
of each of the integrated circuit chips are connected, in Figure 3, to a flexible
carrier 30.
The carrier 30 is bent around the member 10 so that it faces both
sides of the member 10. The carrier 30 will have an electrically conductive
pattern formed thereon, adapted to connect to the integrated circuit chips 20.
The carrier 30 is connected to the other surfaces of the integrated circuit chips
20 by means of solder bumps 21 in a conventional manner such as controlled-
collapse-chip-connection (C4), wire bond, or thermocompression bond
arrangement.
As noted above, the carrier 30 in Figure 3 is a flexible carrier
so that the arrangement shown in Figure 3 makes connections to all of the integrated circuit chips 20 mounted on the member 10 utilizing a very small
volume. The carrier 30 may be connected to other carriers or a mother board
by the use of solder balls 22, shown connected to the bottom of the carrier in
Figure 3.
While only a side view of the member 10 is shown in Figure 3,
it can be seen that the member 10 can have a single strip of integrated circuit
mounting areas 12 or, as shown in Figure 2, a member 10' can have a plurality
of columns of mounting areas 12' for mounting integrated circuit chips,
depending on the memory and capacity required.
Similarly, the member 10 is made of a high thermally conductive
material, such as aluminum, copper, or Thermalgraph 8000™ (trademark). The
member 10 in Figure 3 not only serves to provide heat dissipation, it also
serves as a stiffener, so that the high-density package shown in Figure 3 is very
compact and yet provides a stable arrangement for mounting the integrated
circuit chips and providing interconnections thereto. Because the stiffener is
made of a thermally conductive material and a high thermal conductivity paste
is used for attaching one surface of the integrated circuit chips to the stiffener,
heat generated by the operation of the integrated circuit chips is quickly dissipated into the air circulating about the stiffening member 10. The
stiffening member 10 may also have fins, extensions or heat pipes attached if
desired.
The solder balls 22 may be used to attach the carrier 30 to a
second level, as will be explained subsequently.
Referring now to Figure 4, a different type of carrier is shown.
Here the carrier is formed in two parts 40 and 50. The carrier can be a printed
circuit board made of FR4 material which is a metallic or copper plane
arranged with the appropriate electrical circuit pattern thereon or from other
packaging material such as teflon or ceramic. The electrical connections
between the parts 40 and 50 of the carrier in Figure 4 are made by an integral,
flexible cable 41. The parts of Figure 4 that are the same as the parts of Figure
3 are similarly numbered since the remaining elements of the high-density
package, aside from the carrier, remain the same.
Because the two-part carrier 40 and 50 face the opposite surfaces
of the integrated circuit chips, and the stiffener 10 is made of thermally
conductive material, heat is readily dissipated from the integrated circuit chips into the environment, even though the high-density package is unusually
compact.
The embodiment of Figure 5 shows a different type of stiffener
member 60. The member 60 is formed with a plurality of channels 61
therethrough in the form of a "cinder block" arrangement. The channels 61 may
have any desirable cross section depending on the application. In this
arrangement, increased heat dissipation surfaces are provided by the stiffener
60. In the embodiment of Figure 5, the elements numbered similarly to that of
Figures 3 and 4 serve similar functions.
With the channels 61 , a higher degree of heat dissipation may be
provided when necessary. It is seen, however, that the member 60 contains
mounting areas 12 for the circuit chips 20, as before. Also, in this figure, a
flexible carrier 30 is used for facing the opposite sides of the stiffener 60 and
the other surfaces of the integrated circuit chips 20.
Referring to Figure 6, an arrangement is shown in which three
carriers 30 are provided to form a multi-stack or multi-level arrangement. Each
of the carriers contains a package of the type shown in Figures 3 or 5. This
arrangement of Figure 6 forms a plurality of high-density packages for the integrated circuit chips. It can be seen that each carrier is electrically connected
to the carrier adjacent thereto, and the last or bottom carrier in Figure 6 is
connected to a mother board 70 by means of the solder balls 22'. Similar solder
balls or solder bumps are used for connecting the carriers to the adjacent
carriers. Wire bonds may also be used for this purpose.
Thus, a stacked, high-density package for integrated circuit chips
is provided and provides an unusually compact arrangement having very good
thermal conductivity. Each of the three packages shown in Figure 6 has a
thermally conductive stiffener member which is able to dissipate quickly the
heat generated by the integrated circuit chips to the surrounding environment.
This will permit higher memory capacity to be provided in a smaller volume
than previously permitted. Also, since the integrated circuit chips are mounted
on both, opposite sides of the stiffener member, a larger number of integrated
circuit chips may be put into the same sized volume previously used. The
thermal conductivity of the mounting stiffener member permits such an
arrangement.
It is clear that the use of this stiffener serving as heat sink in the
center of the high-density package allows for three-dimensional cooling of the entire package. As is known, the printed circuit board material, FR4, provides
an organic carrier.
While the integrated circuit chips have been described as utilizing
a high thermal conductivity paste for mounting the bottom surfaces of the
integrated circuit chips to the stiffener member, it is evident that other forms
of mounting may be used which have good thermal conductivity and thermal
dissipation characteristics.
While the present invention has been described with respect to
preferred embodiments, numerous modifications, changes, and improvements
will occur to those skilled in the art without departing from the spirit and scope
of the invention.

Claims

What is claimed is:
1. A high-density package for integrated circuit chips
comprising:
a thermally conductive member having a pair of opposite
sides, each of said sides having spaced areas adapted to have an
integrated circuit chip mounted thereon;
a plurality of integrated circuit chips, each having a top
and a bottom surface, one of said surfaces of each of said
plurality of chips being mounted respectively on one of said
areas of said thermally conductive member so that said plurality
of chips are mounted on said pair of opposite sides of said
thermally conductive member; and
a carrier member having a preselected electrically
conductive pattern thereon being electrically connected to the
other surface of each of said plurality of integrated circuit chips.
2. A package, as claimed in claim 1 , wherein said carrier is
a flex carrier that is bent around said thermally conductive member to face said
other surfaces of said plurality of integrated circuit chips.
3. A package, as claimed in claim 1, wherein said carrier is
a two-part printed circuit board facing said other surfaces, said two parts being
electrically connected to each other by an integral flexible cable.
4. A package, as claimed in claim 1 , wherein said integrated
circuit chips are mounted on said thermally conductive member by means of a
high thermal conductivity paste.
5. A package, as claimed in claim 1, wherein said thermally
conductive member serves as a stiffener for said high-density package.
6. A package, as claimed in claim 5, wherein said thermally
conductive member is made of aluminum.
7. A package, as claimed in claim 5, wherein said thermally
conductive member is made of copper.
8. A package, as claimed in claim 5, wherein said thermally
conductive member is made of Thermalgraph™.
9. A package, as claimed in claim 1, wherein said thermally
conductive member is formed with a plurality of open channels to permit the
passage of air or other fluids therethrough.
10. A plurality of high-density packages for integrated circuit
chips, each of said packages being formed, as claimed in claim 1 , and wherein
said packages are stacked one next to the other, with the carrier of each
package being electrically connected to the carrier adjacent thereto; and
a mother board electrically connected to one of said
carriers.
11. A package, as claimed in claim 3, wherein said carrier is
an organic card made of FR4 material.
12. A package, as claimed in claim 1, wherein said carrier is
connected to said other surface of each of said integrated circuit chips by solder
balls.
13. A package as claimed in claim 3, wherein said carrier is
made of teflon.
14. A package as claimed in claim 3, wherein said carrier is
made of ceramic.
15. A package as claimed in claim 1, wherein said carrier is
connected to said other surface of each of said integrated circuit chips by wire
bonds.
PCT/US1996/007290 1996-05-20 1996-05-21 High-density, integrated circuit chip package WO1997044824A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU58665/96A AU5866596A (en) 1996-05-20 1996-05-21 High-density, integrated circuit chip package

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US1715396P 1996-05-20 1996-05-20
US60/017,153 1996-05-20

Publications (1)

Publication Number Publication Date
WO1997044824A1 true WO1997044824A1 (en) 1997-11-27

Family

ID=21781018

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1996/007290 WO1997044824A1 (en) 1996-05-20 1996-05-21 High-density, integrated circuit chip package

Country Status (2)

Country Link
AU (1) AU5866596A (en)
WO (1) WO1997044824A1 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000002246A1 (en) * 1998-07-07 2000-01-13 R-Amtech International, Inc. Double-sided electronic device
EP1119049A2 (en) * 2000-01-18 2001-07-25 Sony Corporation Laminate type semiconductor apparatus
US6699730B2 (en) 1996-12-13 2004-03-02 Tessers, Inc. Stacked microelectronic assembly and method therefor
US7149095B2 (en) 1996-12-13 2006-12-12 Tessera, Inc. Stacked microelectronic assemblies
CN104900611A (en) * 2015-06-09 2015-09-09 中国科学院微电子研究所 Flexible-substrate-based three-dimensional packaging heat-radiation structure and preparation method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5050039A (en) * 1990-06-26 1991-09-17 Digital Equipment Corporation Multiple circuit chip mounting and cooling arrangement
US5345205A (en) * 1990-04-05 1994-09-06 General Electric Company Compact high density interconnected microwave system
EP0629000A1 (en) * 1993-06-08 1994-12-14 Alcatel N.V. High density and reliability integrated circuit assembly and method of making
DE4329936A1 (en) * 1993-09-04 1995-03-09 Ghassem Azdasht Plug-in multichip module with integrated cooling system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5345205A (en) * 1990-04-05 1994-09-06 General Electric Company Compact high density interconnected microwave system
US5050039A (en) * 1990-06-26 1991-09-17 Digital Equipment Corporation Multiple circuit chip mounting and cooling arrangement
EP0629000A1 (en) * 1993-06-08 1994-12-14 Alcatel N.V. High density and reliability integrated circuit assembly and method of making
DE4329936A1 (en) * 1993-09-04 1995-03-09 Ghassem Azdasht Plug-in multichip module with integrated cooling system

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
"CONCEPT FOR FORMING MULTILAYER STRUCTURES FOR ELECTRONIC PACKAGING", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 30, no. 3, August 1987 (1987-08-01), NEW YORK US, pages 1353 - 1356, XP002024165 *
"DENSELY POPULATED, VERTICALLY STACKED MULTI CHIP MODULE", 1 April 1995, IBM TECHNICAL DISCLOSURE BULLETIN, VOL. 38, NR. 4, PAGE(S) 59 - 62, XP000516073 *
"REMOVAL OF HEAT FROM DIRECT CHIP ATTACH CIRCUITRY", September 1989, IBM TECHNICAL DISCLOSURE BULLETIN, VOL. 32, NR. 4A, PAGE(S) 346 - 348, XP000039929 *

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6699730B2 (en) 1996-12-13 2004-03-02 Tessers, Inc. Stacked microelectronic assembly and method therefor
US7149095B2 (en) 1996-12-13 2006-12-12 Tessera, Inc. Stacked microelectronic assemblies
WO2000002246A1 (en) * 1998-07-07 2000-01-13 R-Amtech International, Inc. Double-sided electronic device
EP1119049A2 (en) * 2000-01-18 2001-07-25 Sony Corporation Laminate type semiconductor apparatus
EP1119049A3 (en) * 2000-01-18 2003-10-01 Sony Corporation Laminate type semiconductor apparatus
CN104900611A (en) * 2015-06-09 2015-09-09 中国科学院微电子研究所 Flexible-substrate-based three-dimensional packaging heat-radiation structure and preparation method thereof
CN104900611B (en) * 2015-06-09 2017-09-08 中国科学院微电子研究所 Three-dimension packaging radiator structure based on flexible base board and preparation method thereof

Also Published As

Publication number Publication date
AU5866596A (en) 1997-12-09

Similar Documents

Publication Publication Date Title
US6326696B1 (en) Electronic package with interconnected chips
US6545351B1 (en) Underside heat slug for ball grid array packages
US6114761A (en) Thermally-enhanced flip chip IC package with extruded heatspreader
US7704798B2 (en) Electronic assemblies with hot spot cooling and methods relating thereto
US6947286B2 (en) Stack up assembly
US7429792B2 (en) Stack package with vertically formed heat sink
US5642261A (en) Ball-grid-array integrated circuit package with solder-connected thermal conductor
EP0638931B1 (en) Multi-chip module
US5838545A (en) High performance, low cost multi-chip modle package
US6900529B2 (en) Electronic module having a three dimensional array of carrier-mounted integrated circuit packages
US5761044A (en) Semiconductor module for microprocessor
US20070045804A1 (en) Printed circuit board for thermal dissipation and electronic device using the same
US6567270B2 (en) Semiconductor chip package with cooling arrangement
EP0054539A2 (en) A semiconductor integrated circuit device with an improved heat sink
US7298028B2 (en) Printed circuit board for thermal dissipation and electronic device using the same
US5719745A (en) Extended surface cooling for chip stack applications
US7723843B2 (en) Multi-package module and electronic device using the same
KR20010070141A (en) Electronic module
US6008988A (en) Integrated circuit package with a heat spreader coupled to a pair of electrical devices
US20130068509A1 (en) Method and apparatus for connecting inlaid chip into printed circuit board
JPH09213851A (en) Heat radiation method and heat radiation means for ic device
JPH1187574A (en) Vertically mounted semiconductor chip package and package module including the same
WO1997044824A1 (en) High-density, integrated circuit chip package
KR100230189B1 (en) Ball grid array semiconductor package
US6137174A (en) Hybrid ASIC/memory module package

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AL AM AT AU AZ BB BG BR BY CA CH CN CZ DE DK EE ES FI GB GE HU IS JP KE KG KP KR KZ LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK TJ TM TR TT UA UG US UZ VN AM AZ BY KG KZ MD RU TJ TM

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): KE LS MW SD SZ UG AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN

121 Ep: the epo has been informed by wipo that ep was designated in this application
REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

NENP Non-entry into the national phase

Ref country code: JP

Ref document number: 97542256

Format of ref document f/p: F

WA Withdrawal of international application