WO1997047044A1

WO1997047044A1 - Insulated gate bipolar transistor with reduced losses

Info

Publication number: WO1997047044A1
Application number: PCT/US1997/009212
Authority: WO
Inventors: Krishna Shenai
Original assignee: The Board Of Trustees Of The University Of Illinois
Priority date: 1996-06-06
Filing date: 1997-05-29
Publication date: 1997-12-11
Also published as: AU3220597A

Abstract

An insulated gate bipolar transistor is provided including a substrate (36) of a first conductivity type forming a drift region, a collector (32) disposed in the substrate adjacent a surface of the substrate remote from a source (40) and a channel region, in which at least a portion of the collector (32) is either the first or a second conductivity type and has an average doping level of the second conductivity type of no more than three orders of magnitude higher than the drift region. A thin lifetime control region is disposed at the interface (34) of the drift region and the collector.

Description

INSULATED GATE BIPOLAR TRANSISTOR WITH REDUCED LOSSES

Field of the Invention The field of the invention relates to metal-oxide semiconductors (MOS) and, more particularly, to insulated gate bipolar transistors (IGBTs) .

Background of the Invention IGBTs are generally known in the field of power control. IGBTs are generally known to be high voltage (e.g., 100 volts, or more), high power devices (e.g., 1 kW, or more) that have a great deal of usefulness in a number of fields (e.g., motor controls, rectifiers, etc.).

IGBTs are usually constructed in the form of a 4-layer device similar to a silicon controlled rectifier (SCR) . As is the case with SCRs, once early IGBTs were triggered into a conductive state, the presence of regenerative currents within the IGBT tend to maintain the IGBT in a conductive state prior to loss of gate control. This condition is generally referred to as " latch-up" . In an effort to improve the usefulness of IGBTs, recent advances have included the creation of punch- through IGBTs having a buffer layer in a drift region, adjacent the collector, which interferes with regenerative currents, thereby reducing the likelihood of latch-up.

Where latch-up can be controlled, an IGBT can be created which has the ability of turning off under load. The ability to turn off under load makes an IGBT much more useful as a power control unit in such devices as inverters or power controllers.

While latch-up can generally be controlled, one of the remaining difficulties with the use of IGBTs is the inefficiencies associated with their slow turn-off times and internal resistance. IGBTs rely on a relatively thick drift region to resist electrical breakdown. With a generally accepted electrical breakdown voltage rating of 10 volt/μm within the drift region of silicon, a 1000 volt device generally requires a drift region of the order of 100 μm. The relatively thick drift region provides a significant charge reservoir during conduction and a source of difficulty in charge removal during turn-off. The presence of charge carriers (e.g., electrons and holes) in the drift region is necessary for device conduction. When charge remains in the drift region after removal of control voltage from an IGBT gate connection, current continues to flow through the drift region and, consequently, through the IGBT. As charge depletion gradually occurs during turn-off, a voltage builds up across the IGBT, eventually resulting in turn-off of the device. During turn-off, the power dissipated within the IGBT is determined by the product of current times voltage, according to well-known principles. While IGBTs have proven useful in inverters and elsewhere, their use is still limited to applications involving switching rates of less than 100 kHz. At frequencies above 100 kHz, the power dissipated during switching can result in overheating and, ultimately, device failure.

Efforts to improve device turn-off times have included the use of carrier lifetime control within the drift region. Carrier lifetime control, as that term is used in the art, refers to the creation of sites within the structure of the IGBT that facilitates the re-combination of electrons and holes. Lifetime control may include the dispersion of an appropriate material (e.g., gold particles) through the lattice of the substrate or irradiation. Irradiation of the substrate purposefully damages the crystal structure in such a way as to facilitate charge re-combination.

While lifetime control is effective to some degree in increasing the speed of turn-off, lifetime control also has the effect of increasing device resistance. Increasing device resistance also causes heat generation and heat build-up within the IGBT during any normal current flow. Increasing the lifetime control through metallic dispersions or irradiation, while allowing for an increase in maximum switching speeds, results in a trade-off which can cause an overall decrease in device efficiency.

Accordingly, it is an object of the invention to provide a mechanism for rapid charge depletion within the drift region of the IGBT after turn-off of the device that does not result in an overall increase in device resistance.

It is a further object of the invention to provide a mechanism for rapid charge depletion in the drift region that allows for an increase in a maximum switching rate for IGBTs. It is a further object of the invention to provide a structure for IGBTs that is applicable for punch through IGBTs and non-punch through IGBTs.

Summary In one embodiment of the invention, an insulated gate bipolar transistor is provided including a substrate of a first conductivity type forming a drift region, and a collector disposed in the substrate adjacent a surface of the substrate remote from a source and channel region. At least a portion of the collector is the first or a second conductivity type and has an average doping level of the second conductivity type of no more than three orders of magnitude higher than the drift region. A lifetime control region is disposed at the interface of the drift region and the collector.

Brief Description of the Drawings FIG. 1 is a cross-sectional view of a prior art insulated gate bipolar transistor; and

FIG. 2 is a net doping profile of the prior art device of FIG. 1. FIG. 3 is a cross-sectional view of an insulated gate bipolar transistor device in accordance with an embodiment of the invention;

FIG. 4 is a net doping profile of the device of FIG. 3; FIG. 5 is a zero-voltage switching turn-on waveform of the device of FIG. 3; FIG. 6 is a zero-voltage switching turn-off waveform of the device of FIG. 3;

FIG. 7 is a hard-switching turn-off waveform of the device of FIG. 3; FIG. 8 is a cross-sectional view of an insulated gate bipolar transistor as in FIG. 3 under an alternate embodiment using a p+/n+ mesh as a collector structure;

FIG. 9 is a plan view of a diffusion pattern diffused into the collector of FIG. 8; FIG. 10 is a zero-voltage switching turn-off waveform of the device of FIG. 8 with a p+/n+ mesh ratio of 30/70;

FIG. 11 is a zero-voltage switching turn-on waveform of the device of FIG. 8 with a p+/n+ mesh ratio of 30/70;

FIG. 12 is a zero-voltage switching turn-off waveform of the device of FIG. 8 with a p+/n+ mesh ratio of 50/50;

FIG. 13 is a zero-voltage switching turn-on waveform of the device of FIG. 8 with a p+/n+ mesh ratio of 50/50;

FIG. 14 is a zero-voltage switching turn-off waveform of the device of FIG. 8 with a p+/n+ mesh ratio of 70/30; FIG. 15 is a zero-voltage switching turn-on waveform of the device of FIG. 8 with a p+/n+ mesh ratio of 70/30;

FIG. 16 is a cross-sectional view of an insulated gate bipolar transistor as in FIG. 3 under an alternate embodiment using a p+/ⁿ mesh as a collector structure; FIG. 17 is a cross-sectional view of an insulated gate bipolar transistor as in FIG. 3 under an alternate embodiment using a p/p+ mesh as a collector structure;

FIG. 18 is a zero voltage switching turn-off waveform of FIG. 17 using a p/p+ mesh as a collector structure; FIG. 19 is a zero voltage switching turn-on waveform of FIG. 17 using a p/p+ mesh as a collector structure;

FIG. 20 is a zero voltage■ switching turn-off waveform of FIG. 16 using a p+/n mesh as a collector structure; and

FIG. 21 is a zero voltage switching turn-on waveform of FIG. 16 using a p+/n mesh as a collector structure. Detailed Description of the Invention Under an embodiment of the invention, latch-up is controlled by a carrier lifetime control region located in the vicinity of the interface between the drift region and collector of the IGBT, instead of as a separate buffer region within the drift region. Providing lifetime control at the interface between the drift region and collector has been determined to also improve device turn-off speed without increasing device resistance.

It has generally not been recognized in the art of IGBTs that a lifetime control system could be localized to a specific area and plane of the IGBT. Under the invention, lifetime control is achieved by disposing a lifetime control region in the plane of the junction of a drift and collector regions of the IGBT through ion implantation or selective crystal damage. The use of ion implantation avoids the need for dispersion of metallic particles within the drift region, or irradiation which increases the bulk resistance of the drift region.

FIG. 1 is a cross-sectional view of a prior art p-channel IGBT 10. As shown, a prior art IGBT 10 of FIG. 1 may be fabricated by an epitaxial process involving a number of diffusion and deposition steps. FIG. 2 is a doping profile of the prior art IGBT 10 of FIG. 1.

A p-substrate 12 having a doping level of lel9/cm^"3 (FIG. 2) is a typical choice for a p channel IGBT. A buffer region 14 having a n type doping level of lel7/cm^"3 is created on the substrate 12. A drift region 16 is then created having a low n- type doping level of lel4/cm^"3. The device 10 is then masked and a channel region 18 is created at a doping level of lel8/cm^"3. The device 10 is again masked for creation of the cathode 20 of a n+ type doping material at a level of 2el9/cm^"3.

To complete the process, a insulator 22 is created by masking the device 10 and depositing an insulating material (e.g., Si0₂) on the surface. The device 10 is again masked and gate and power connections 26, 28, 30 are created using an appropriate metalization process.

FIG. 3 is a cross-sectional view of an IGBT 20 in accordance with an embodiment of the invention. FIG. 4 is a doping profile of the inventive IGBT 20.

The IGBT 20, because of the features inherent in the structure shown in FIG. 3, may be fabricated using simpler, more environmentally friendly processes (e.g., bulk process of float zone, etc.) . The drift region of an n- type material of an appropriate doping level (e.g., Iel4/cm^"3) and the p type collector region of an appropriate doping level (e.g., 2el6/cm^" ³) may be diffused into a substrate from either side.

The channel region 38 of a p+ type material (e.g. , of a doping level of 2el7/cm^"3) and the cathode 40 of a n+ type material (e.g., of a doping level of 2el8/cm^"3) may be created as under the prior art by masking and diffusing. The gate insulator 42 may also be created of a similar material (e.g., Si0₂) , as under the prior art, by masking and deposition. Similarly, the emitter 46, gate 48 and collector 52 may be created by masking and by a metallic deposition process, as known in the art.

One difference between the prior art IGBT 10 and the inventive IGBT 20 is the level of doping of the collector 32. Under the illustrated embodiment of FIG. 3, the average doping level of the collector 32 is no more than one or two orders of magnitude higher than the drift region 36. It has been found that a lower doping level in the collector 32 provides the unexpected benefit of providing a lower charge barrier to current conduction, and more efficient charge transfer, thereby reducing forward conduction loss and improving turn- off speed.

Another difference with the IGBT 20 is the use of a carrier lifetime control region 34 at the intersection of the collector 32 and drift region 36. Under the embodiment, lifetime control is localized to the intersection through the use of an appropriate ion implantation process (e.g., hydrogen ion implantation) as is well known in the art (see, e.g., J. M. Shannon, Reducing the Effective Height of a Schottky Barrier Using Low-Energy Ion Implantation, Applied Physics Letters, Vol. 24, pp. 369-371 (1974)), and is limited to a distance of no more than a few micrometers in either direction of the intersection. The use of carrier lifetime control in the lifetime control region 34 causes a rapid elimination of charge carriers following removal of a control voltage from the gate 48.

FIGs. 5-7 are computer simulations of the turn-off waveforms to be expected from the IGBT 20. FIG. 5 provides instantaneous time versus collector voltage curves for the prior art IGBT 10 (solid line) and for the IGBT 30 of the current invention (dotted line) , in a soft-switching application. As indicated by FIG. 5, the internal stress (as demonstrated by p channel to drift region voltage) of the novel IBGT 30 during turn-on is virtually identical to the prior art IBGT 10.

FIG. 6 is a time scale showing the improvement of switching speed of the new IGBT 30 over a larger time scale. As indicated by FIG. 6 the use of the new IGBT 30 in a soft¬ switching application can result in up to a 6-fold improvement in switching efficiency (i.e., reduction in internal heat generation for each switching cycle) .

FIG. 7 shows switching times in a hard switching application. As shown the 6-fold improvement in switching efficiency is also present in hard-switching applications.

In another embodiment of the invention, the power connection to the IGBT 30 is improved at the ohmic contact with the collector through use of a second p+ layer 50. The layer 50 is typically of a higher doping level (e.g.,

Iel9/cm^"3) , but very thin (e.g., a few microns) . The use of the layer 50 improves the electrical contact with the collector power connection 52 while not effecting (because it is very thin) an average doping level of the collector 32. In another embodiment (FIG. 16) , the average p type doping level of the collector region 32 is reduced by using a checkerboard pattern of alternating p and n type doping regions, or p+ and p type doping regions. The checkerboard pattern provides a mesh structure which not only improves device switching characteristics but also provides a reduction in internal heat generation. Under the embodiment, the IGBT 30 is fabricated by masking the back side of the IGBT 30 during fabrication of the collector 32 (FIG. 9) and diffusing checkerboard a pattern of p type doping regions 54 into non- adjacent squares (FIGs. 9 and 16) or a pattern of p+ and p type doping regions 54, 56 into non-adjacent squares (FIGs. 9 and 17) . Carrier lifetime control is again disposed into a carrier lifetime region 34 at the intersection between the collector 32 and drift region 36.

The ratio of areas of the p and p+ type regions 54, 56 can be adjusted to an application specific trade-off between on-state voltage drop (and turn-on losses) and turn-off switching losses. Table I, given below, compares the performance of IGBTs 30 with different area ratios of p/p+. The on-state voltage drop is measured for 100 amps current while the turn-off switching losses are calculated when the device turns off 100 amps current at 600 volts from a bus with a 100 nF snubber capacitor across the bus (i.e., soft switching) .

TABLE I

Ratio of p/p+ On-state voltage (@ Turn-off loss (mJ) 100A) (V)

30/70 1.5 26.9

50/50 1.6 20.1

70/30 1.75 15.1

The ZVS performance for turn-on and turn-off can be seen by reference to FIGs. 18-19.

Where the p+ and n type checkerboard patterns 54, 56 are used (FIGs. 9 and 16) , the p+ type regions 54 also provide good turn-on and conduction performance. The n type regions 56 improve turn-off performance. Where the p+ and n type regions 54, 56 are used, the p+ type material is diffused into a surface that previously had a doping level identical to the drift region 36. After doping, the p+ regions 54 have a level of the p type material several levels of magnitude above the doping level of the drift region 36. The n type regions 56 of the collector 32 remain at a doping level almost identical to the drift region 36. The collector 32 still has a portion 56 of which still has a level of doping no more than two levels of doping above the drift region 36.

Again, the ratios of p+/n can be adjusted to give performance specific attributes. Table II gives performance levels for various ratios.

TABLE II

Ratio of p+/n On-state voltage (@ Turn-off energy 100A) (V) loss (mJ)

30/70 2.3 5.7

50/50 2.0 7.49

70/30 1.85 11.43

The performance of the p+/n collector can be seen by reference to FIG.s 20-21.

In another embodiment of the invention (FIG. 8) , the average p type doping level of the collector region 32 is reduced by using a checkerboard pattern of alternating p+ and n+ regions. Under the embodiment, the IGBT 30 is fabricated by masking the collector area 32 (FIG. 9) and diffusing a pattern of p+ and n+ doping areas into the collector area 32. A carrier lifetime control region 34 is, again, created at the intersection between the drift region 36 and collector 32.

It has been found that the use of the n+ regions 56 interspersed with other p+ regions 54 within the collector 32 decreases the overall series circuit power resistance of the IGBT 30 (i.e., anode 40 to channel 38 to drift region 36 to collector 32) . The area ratio of p+/n+ can be used to obtain a required trade-off between on-state voltage drop, turn-on losses and turn-off losses. A factor which affects this trade-off is the n+ diffusion depth. Computer simulations can be performed for different area ratios and different diffusion depths of n+. The results of these simulations for the different cases are shown in FIGs. 10-15. The n+ depth is varied in the simulations by defining the n+ regions to be gaussian and changing the characteristic length of the n+ regions (as the size of the squares increases, so does the n+ depth) . Shown below is a table (TABLE III) comparing the performance of IGBTs with different area ratios of p+/n+ and different n+ depths (different characteristic lengths) for each area ratio. The on-state voltage drop is measured for 100 amps of current while the turn-off losses are calculated when the device turns-off 100 amps at 600 volts bus voltage with a 100 nF snubber capacitor across the bus in a soft switching application.

TABLE III

Ratio of p+/n+ Gaussian On-state Turn-off

Characteristics Voltage (@ energy loss

100 A) (V) (mJ)

30/70 1.3 2.52 4.7

2.5 2.79 3.78

3.5 3.13 3.13

30/70 5.0 4.46 1.92

50/50 1.3 2.16 6.65

2.5 2.32 5.34

3.5 2.50 4.62

5.0 2.97 3.32

70/30 1.3 1.89 10.3

2.5 2.03 8.10

3.5 2.10 7.20

5.0 2.44 4.85

The relationship between gaussian characteristics and the depth at which gaussian n+ doping becomes equal to drift region doping is given in Table IV. TABLE IV

Gaussian Characteristics Depth at which n+ doping equals drift region (Doping μm)

1.3 7.6

2.5 10.0

3.5 15

5.0 18

Specific embodiments of novel apparatus for reducing losses and switching times in an IGBT according to the present invention have been described for the purpose of illustrating the manner in which the invention is made and used. It should be understood that the implementation of other variations and modifications of the invention and its various aspects will be apparent to one skilled in the art, and that the invention is not limited by the specific embodiments described. Therefore, it is contemplated to cover the present invention any and all modifications, variations, or equivalents that fall within the true spirit and scope of the basic underlying principles disclosed and claimed herein.

Claims

1. An insulated gate bipolar transistor comprising: a substrate of a first conductivity type forming a drift region; a collector disposed in the substrate, wherein at least a portion of the collector is one of the first and a second conductivity type and has an average doping level of the second conductivity type of no more than three orders of magnitude higher than the drift region; and a lifetime control region disposed at the interface of the drift region and the collector region.

2. The insulated gate bipolar transistor as in claim 1 wherein the lifetime control region is relatively thin.

3. The insulated gate bipolar transistor as in claim 1 wherein the lifetime control region further comprises implanted ions.

4. The insulated gate bipolar transistor as in claim 1 further comprising a second layer of the second conductivity type with a doping level greater than two orders of magnitude higher than the drift region disposed between the collector and a collector electrical output connection of the insulated gate bipolar transistor.

5. The insulated gate bipolar transistor as in claim 1 wherein the collector further comprises a checkerboard pattern of alternating high and low doping levels.

6. The insulated gate bipolar transistor as in claim 1 wherein the collector further comprises a checkerboard pattern of alternating high doping levels of the first and second conductivity types.

7. An insulated gate bipolar transistor comprising: a substrate of a first conductivity type forming a drift region; a collector disposed in the substrate in which the collector is of a second conductivity type and has an average doping level no more than three orders of magnitude higher than the drift region; and a lifetime control region disposed at the interface of the drift region and the collector region.

8. The insulated gate bipolar transistor as in claim 7 wherein the lifetime control region is relatively thin.

9. The insulated gate bipolar transistor as in claim 7 wherein the lifetime control region further comprises implanted ions.

10. The insulated gate bipolar transistor as in claim 7 further comprising a collector electrical contact disposed on the collector.

11. The insulate gate bipolar transistor as in claim 10 further comprising a second collector region of a doping level higher than two orders of magnitude higher than the drift region, disposed between the collector and collector contact.

12. An insulated gate bipolar transistor having a plurality of conductivity regions of a first and second conductivity type, such insulated gate bipolar transistor comprising: a substrate of the first conductivity type forming a drift region; and a collector disposed in the substrate, forming a plane in the substrate, in which the plane of the collector is a checkerboard pattern of first and second conductivity types in which at least some of the regions of the second conductivity type have doping levels no more than three orders of magnitude higher than the drift region.

13. An insulated gate bipolar transistor as in claim 12 further comprising a lifetime control region disposed at a junction of the drift region and the collector region.

14. An insulated gate bipolar transistor having a plurality of conductivity regions of a first and second conductivity type, such insulated gate bipolar transistor comprising: a substrate of the first conductivity type forming a drift region; and a collector disposed in the substrate, forming a plane in the substrate adjacent a surface of the substrate remote from a source and channel region, in which the plane of the collector is a checkerboard pattern of second conductivity types in which at least some of the regions of the second conductivity type have doping levels no more than three orders of magnitude higher than the drift region.

15. An insulated gate bipolar transistor as in claim 12 further comprising a lifetime control region disposed at a junction of the drift region and the collector region.

16. An insulated gate bipolar transistor comprising: a substrate of a first conductivity type forming a drift region; a collector disposed in the substrate adjacent a surface of the substrate remote from a source and channel region, in which at least a portion of the collector is one of the first and second conductivity type and has an average doping level of the second conductivity type of no more than three orders of magnitude higher than the drift region; and a lifetime control region disposed at the interface of the drift region and the collector region.

17. An insulated gate bipolar transistor having a plurality of conductivity regions of a first and second conductivity type, such insulated gate bipolar transistor comprising: a substrate of the first conductivity type forming a drift region; and a collector disposed in the substrate, forming a plane in the substrate adjacent a surface of the substrate remote from a source and channel region, in which the plane of the collector is a checkerboard pattern of regions first and second conductivity types.

18. The insulated gate bipolar transistor as in claim 17 wherein the regions of second conductivity type have doping levels no more than two levels of magnitude above the drift region.

19. The insulated gate bipolar transistor as in claim 17 further comprising a lifetime control region disposed at a junction of the drift region and the collector region.

20. The insulated gate bipolar transistor as in claim 17 wherein the regions of first and second conductivity types have doping levels that are substantially five orders of magnitude higher than the drift region.

21. An insulated gate bipolar transistor comprising: a substrate of a first conductivity type forming a drift region; a source region of the first conductivity type disposed in the substrate adjacent a surface of the substrate; a channel region of a second conductivity type surrounding the source region within the substrate, extending to the surface and encircling the source region adjacent the surface of the substrate; a first power connection of the insulated gate bipolar transistor disposed over and contacting a portion of the source and channel regions adjacent the surface; and a collector of the second conductivity type having an average doping level no more than two orders of magnitude higher than the drift region disposed in the substrate adjacent a surface of the substrate remote from the source and channel; and a second power connection disposed on the collector region adjacent the surface and forming a series power circuit with the first power connection through the source, channel, drift, and collector regions; a electrically insulative layer disposed over a portion of the channel and drift regions adjacent the surface; and a gate of the isolated gate bipolar transistor disposed over the electrically insulative layer over the portion of the channel and drift region.

22. The insulated gate bipolar transistor as in claim 21 further comprising a second layer of the second conductivity type with a doping level greater than two orders of magnitude higher than the drift region disposed between the collector and the second power connection.

23. The insulated gate bipolar transistor as in claim 21 wherein the collector further comprises a two-dimensional checkerboard pattern in the plane of the surface of the substrate of alternating high and low doping levels.

24. The insulated gate bipolar transistor as in claim 21 wherein the collector further comprises a two-dimensional checkerboard pattern in the plane of the surface of the substrate of alternating high doping levels of the first and second conductivity types.

25. The insulated gate bipolar transistor of claim 21 further comprising a lifetime control region disposed at the intersection of the collector and drift regions.

26. An insulated gate bipolar transistor comprising: a substrate of a first conductivity type forming a drift region; a source region of the first conductivity type disposed in the substrate adjacent a surface of the substrate; a channel region of a second conductivity type surrounding the source region within the substrate, extending to the surface and encircling the source region adjacent the surface of the substrate; a first power connection of the insulated gate bipolar transistor disposed over and contacting a portion of the source and channel regions adjacent the surface; and a collector of the second conductivity type having an average doping level no more than three orders of magnitude higher than the drift region disposed in a checkerboard pattern of alternating high and low doping levels in the plane of the substrate adjacent a surface of the substrate remote from the source and channel; and a second power connection disposed on the collector region adjacent the surface and forming a series power circuit with the first power connection through the source, channel, drift, and collector regions; a electrically insulative layer disposed over a portion of the channel and drift regions adjacent the surface; and a gate of the isolated gate bipolar transistor disposed over the electrically insulative layer over the portion of the channel and drift region.

27. An insulated gate bipolar transistor comprising: a substrate of a first conductivity type forming a drift region; a source region of the first conductivity type disposed in the substrate adjacent a surface of the substrate; a channel region of a second conductivity type surrounding the source region within the substrate, extending to the surface and encircling the source region adjacent the surface of the substrate; a first power connection of the insulated gate bipolar transistor disposed over and contacting a portion of the source and channel regions adjacent the surface; and a collector of the first and second conductivity type having disposed in a checkerboard pattern of alternating first and second conductivity types in a plane of a surface of the substrate remote from the source and channel; and a second power connection disposed on the collector region adjacent the surface and forming a series power circuit with the first power connection through the source, channel, drift, and collector regions; a electrically insulative layer disposed over a portion of the channel and drift regions adjacent the surface; and a gate of the isolated gate bipolar transistor disposed over the electrically insulative layer over the portion of the channel and drift region.

28. A method of fabricating an insulated gate bipolar transistor comprising the steps of: providing a drift region; providing a collector region having a doping level no more than two orders of magnitude above the drift region; and providing a lifetime control region at a junction of the drift region an collector region.