WO1997049122A1 - Method for cleaning a hole - Google Patents
Method for cleaning a hole Download PDFInfo
- Publication number
- WO1997049122A1 WO1997049122A1 PCT/NL1997/000339 NL9700339W WO9749122A1 WO 1997049122 A1 WO1997049122 A1 WO 1997049122A1 NL 9700339 W NL9700339 W NL 9700339W WO 9749122 A1 WO9749122 A1 WO 9749122A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- hole
- cleaning
- germane
- aluminium
- filling
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
Abstract
Method for making a conducting connection between two spaced metallic layers situated in a semiconductor substrate. After a hole, a so-called via, has been made by etching, tungsten or aluminium is introduced into the hole by conventional techniques, such as CVD or force filling. In order to provide optimum connection to the bottom metallic layer of the hole, it is necessary to clean the latter. It is proposed that this cleaning should be carried out with germane-containing gas.
Description
Method for cleaning a hole
The present invention relates to a method for making a conducting connection between two spaced first and second conducting layers in a semiconductor substrate, at least one dielectric being placed between said layers, comprising making a connecting hole (via) in at least said dielectric up to the first metallic layer and filling said hole with a metal, said hole being cleaned before said metal is introduced.
Such a method is known in the prior art. The desire to achieve ever further miniaturization has led to up to seven metal layers currently being used, stacked on top of each other, in a semiconductor substrate, and this number will increase even further in the future. Conducting structures have to be placed between them. These are achieved by first making holes by means of etching. Such holes are becoming smaller all the time, and are currently of the order of magnitude of 0.3 μm. The maximum height is becoming greater all the time through an increase in the number of metal layers.
After the holes have been made, they are filled, and tungsten- based and aluminium-based materials in particular are used for this purpose. The second metallic layer can be present before the via is made, but is generally applied when the via is being filled or thereafter.
However, it is important that in particular the bottom of the hole, i.e. the top side of the bottom layer or first metal layer, should be cleaned before the holes are filled. For residues are left behind after etching of the hole, and if aluminium is present, said residues contain aluminium oxide, which is non-conducting.
A first method of cleaning such holes is to use a liquid, but with diameters of the holes being of the order of 0.3 μm and the height starting from 1 μm, it has been found that it is no longer possible to use liquid.
Another proposal is to use ion bombardment, by means of which aluminium oxide can be blasted away. However, owing to the decreasing diameter and the increasing height, the chance of the aluminium oxide material being blasted away through the hole is slight, so that a lengthy and intensive bombardment is necessary. This involves considerable costs.
The object of the present invention is to provide a method for cleaning which is cheap and easy to use, and which is not hampered even in the case of small, relatively deep holes.
This object is achieved by a method of the type described above
by the fact that the cleaning comprises introducing into said hole a gas containing germane and/or digermane and that said other metallic layer contains aluminium.
Surprisingly, it has been found that if an adequate stream of germane is used, aluminium oxide is reduced or the oxide is removed by the position of the various equilibria. Although germane is an unstable and toxic gas, it is in general use in the prior art, and there is sufficient experience to make such use inexpensive and safe.
The method described above must be distinguished from what is described in the article 'Low Temperature, Low resistivity sub-half Micron Via/Interconnect Structure Using Reaction of Al-alloys and Germane' by R.V. Joshi and M. Tejwani in IEDM 95-257/258. This article mentions the use of germane after and during the introduction of an aluminium-copper-based filling. It is assumed that an Al-Cu-Ge alloy is produced by using germane. The filling is possibly facilitated and improved by this.
US Patent Specification 5403434 discloses the use of digermane for the formation of GeO, in order to achieve the reduction of SiO- to silicon. According to an advantageous embodiment of the method, the temperature of the substrate during cleaning lies between 200 and 400°C, and more particularly between 300 and 400°C.
The cleaning is preferably carried out at reduced pressure. The quantity of germane passed through depends on the conditions, but in a conventional tank a flow of at least 10 standard cm3 per minute is desirable. The substrate can be placed in a cluster plant, in which a number of processing stations are provided. In this case the substrate can be moved from station to station under conditions with reduced pressure. The holes which are cleaned and subsequently filled can be made by etching, as indicated above.
The invention will be explained below with reference to an exemplary embodiment shown (not to scale) in the drawing, in which:
Fig. 1 shows diagrammatically a cross-section of a semiconductor substrate after the etching of a hole;
Fig. 2 shows the step of cleaning according to the invention;
Fig. 3 shows the first stage of filling; and
Fig. 4 shows the semiconductor substrate after introduction of the filling of the via and application of the second conducting layer.
In Fig. 1 a semiconductor substrate is indicated in its entirety by 1. It consists of a first metallic layer 2 on which a semiconductor layer 4 has been applied.
The object is to connect the layer 2 to a second metallic layer 3 to be applied later (Fig. 4), and to that end a hole 5 is etched, which hole also extends through the semiconductor layer 4. During the etching, products which are not all discharged are produced, and the remaining part which is left behind on conducting layer 2, and which can contain aluminium oxide if aluminium is used for the conducting layer, is indicated by 6.
In Fig. 2 arrows 7 and 8 show the effect of a cleaning flow of germane by diffusion. Germane (GeH4) is passed through at a temperature of approximately 350°C and a pressure of approximately 1 torr for several minutes, with a flow of 10 seem3. It has been found that through sufficient flow of germane the reaction in which aluminium oxide is converted into aluminium is shifted sufficiently to the right to permit full cleaning of the surface of layer 2.
Hole 5 is then filled with a layer containing aluminium (and possibly copper) after the removal of deposit 6. During this process or thereafter the second metallic layer 3 is applied (Fig. 4). Various stages thereof are shown in Figs. 3 and 4. The method of filling is not important for the present invention, and can comprise any known method, such as use of CVD and the use of force fill. Force fill is a method in which a closing aluminium layer is placed above hole 5, and the aluminium is pressed by means of (liquid) pressure at raised temperature (up to 400°C) into hole 5.
Although the invention is described above with reference to a preferred embodiment, it will be understood that numerous modifications can be made thereto. For example, it is possible for layer 2 to be made of a metal other than aluminium-containing material, such as tungsten. This and other modifications lie within the scope of the appended claims.
Claims
1. Method for making a conducting connection between two spaced first and second conducting layers in a semiconductor substrate, at least one dielectric being placed between said layers, comprising making a connecting hole (via) in at least said dielectric up to the first metallic layer and filling said hole with a metal, said hole being cleaned before said metal is introduced, characterized in that the cleaning comprises introducing into said hole a gas containing GeH. and/or Ge2H6, and in that said other metallic layer contains aluminium.
2. Method according to Claim 1, in which the temperature lies between 200 and 400°C.
3. Method according to Claim 2, in which the temperature lies between 300 and 400°C.
4. Method according to one of the preceding claims, in which cleaning is carried out at a reduced pressure of 0.2 - 10 torr.
5. Method according to one of the preceding claims, in which the germane is passed through for a maximum period of 10 minutes, with a flow of at least 10 seem3.
6. Method according to one of the preceding claims, in which the movement of the substrate from the cleaning station and the station for filling said hole is carried out at reduced pressure.
7. Method according to one of the preceding claims, in which the hole is made by etching.
********
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
NL1003373A NL1003373C2 (en) | 1996-06-19 | 1996-06-19 | Method for cleaning an opening. |
NL1003373 | 1996-06-19 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1997049122A1 true WO1997049122A1 (en) | 1997-12-24 |
Family
ID=19763038
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/NL1997/000339 WO1997049122A1 (en) | 1996-06-19 | 1997-06-18 | Method for cleaning a hole |
Country Status (2)
Country | Link |
---|---|
NL (1) | NL1003373C2 (en) |
WO (1) | WO1997049122A1 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6229213B1 (en) | 1996-06-26 | 2001-05-08 | Micron Technology, Inc. | Germanium alloy electrical interconnect structure |
US6239029B1 (en) | 1995-07-17 | 2001-05-29 | Micron Technology, Inc. | Sacrificial germanium layer for formation of a contact |
US6309967B1 (en) | 1995-07-17 | 2001-10-30 | Micron Technology, Inc. | Method of forming a contact |
CN108831859A (en) * | 2018-06-15 | 2018-11-16 | 武汉新芯集成电路制造有限公司 | The manufacturing method of through-hole |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4579609A (en) * | 1984-06-08 | 1986-04-01 | Massachusetts Institute Of Technology | Growth of epitaxial films by chemical vapor deposition utilizing a surface cleaning step immediately before deposition |
JPS61256732A (en) * | 1985-05-10 | 1986-11-14 | Fujitsu Ltd | Method for selective epitaxial growth |
US5089441A (en) * | 1990-04-16 | 1992-02-18 | Texas Instruments Incorporated | Low-temperature in-situ dry cleaning process for semiconductor wafers |
US5403434A (en) * | 1994-01-06 | 1995-04-04 | Texas Instruments Incorporated | Low-temperature in-situ dry cleaning process for semiconductor wafer |
-
1996
- 1996-06-19 NL NL1003373A patent/NL1003373C2/en not_active IP Right Cessation
-
1997
- 1997-06-18 WO PCT/NL1997/000339 patent/WO1997049122A1/en active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4579609A (en) * | 1984-06-08 | 1986-04-01 | Massachusetts Institute Of Technology | Growth of epitaxial films by chemical vapor deposition utilizing a surface cleaning step immediately before deposition |
JPS61256732A (en) * | 1985-05-10 | 1986-11-14 | Fujitsu Ltd | Method for selective epitaxial growth |
US5089441A (en) * | 1990-04-16 | 1992-02-18 | Texas Instruments Incorporated | Low-temperature in-situ dry cleaning process for semiconductor wafers |
US5403434A (en) * | 1994-01-06 | 1995-04-04 | Texas Instruments Incorporated | Low-temperature in-situ dry cleaning process for semiconductor wafer |
Non-Patent Citations (1)
Title |
---|
PATENT ABSTRACTS OF JAPAN vol. 011, no. 108 (E - 495) 4 April 1987 (1987-04-04) * |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6239029B1 (en) | 1995-07-17 | 2001-05-29 | Micron Technology, Inc. | Sacrificial germanium layer for formation of a contact |
US6309967B1 (en) | 1995-07-17 | 2001-10-30 | Micron Technology, Inc. | Method of forming a contact |
US6597042B1 (en) | 1995-07-17 | 2003-07-22 | Micron Technology, Inc. | Contact with germanium layer |
US6229213B1 (en) | 1996-06-26 | 2001-05-08 | Micron Technology, Inc. | Germanium alloy electrical interconnect structure |
US6331482B1 (en) * | 1996-06-26 | 2001-12-18 | Micron Technology, Inc. | Method of VLSI contact, trench, and via filling using a germanium underlayer with metallization |
CN108831859A (en) * | 2018-06-15 | 2018-11-16 | 武汉新芯集成电路制造有限公司 | The manufacturing method of through-hole |
Also Published As
Publication number | Publication date |
---|---|
NL1003373C2 (en) | 1997-12-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0596364B1 (en) | Method of producing semiconductor device having buried contact structure | |
US6949450B2 (en) | Method for integrated in-situ cleaning and subsequent atomic layer deposition within a single processing chamber | |
US6054398A (en) | Semiconductor interconnect barrier for fluorinated dielectrics | |
US4963511A (en) | Method of reducing tungsten selectivity to a contact sidewall | |
US6083835A (en) | Self-passivation of copper damascene | |
US20020113273A1 (en) | Semiconductor device having contact plug and method for manufacturing the same | |
JP3607398B2 (en) | Method for forming metal wiring layer of semiconductor device | |
US5143867A (en) | Method for depositing interconnection metallurgy using low temperature alloy processes | |
US7166532B2 (en) | Method for forming a contact using a dual damascene process in semiconductor fabrication | |
US4349584A (en) | Process for tapering openings in ternary glass coatings | |
US6333265B1 (en) | Low pressure, low temperature, semiconductor gap filling process | |
WO2004044979A1 (en) | Side wall passivation films for damascene cu/low k electronic devices | |
CN100476021C (en) | Method to deposit an impermeable film onto a porous low-K dielectric film | |
US5227337A (en) | Interconnection forming method | |
US6043149A (en) | Method of purifying a metal line in a semiconductor device | |
WO2001071801A1 (en) | Semiconductor device and method of manufacturing same | |
US5849367A (en) | Elemental titanium-free liner and fabrication process for inter-metal connections | |
EP0740336A2 (en) | Method for fabricating semiconductor device having buried contact structure | |
WO1997049122A1 (en) | Method for cleaning a hole | |
CN1149654C (en) | Method and structure for contact to copper metallization in insulating via on semiconductor | |
EP2819162A1 (en) | Method for producing contact areas on a semiconductor substrate | |
EP0262719A2 (en) | Method for manufacturing a planar electrical interconnection utilizing isotropic deposition of conductive material | |
EP0849779A2 (en) | Process for forming a semiconductor structure comprising ion cleaning and depositing steps and integrated cluster tool for performiong the process | |
US5888901A (en) | Multilevel interconnection and method for making | |
WO2002046489A1 (en) | Method for integrated in-situ cleaning and subsequent atomic layer deposition within a single processing chamber |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): JP US |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE |
|
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
NENP | Non-entry into the national phase |
Ref country code: JP Ref document number: 98502718 Format of ref document f/p: F |
|
122 | Ep: pct application non-entry in european phase |