WO1997050116A1 - A capacitor and methods of forming a capacitor - Google Patents
A capacitor and methods of forming a capacitor Download PDFInfo
- Publication number
- WO1997050116A1 WO1997050116A1 PCT/US1997/010574 US9710574W WO9750116A1 WO 1997050116 A1 WO1997050116 A1 WO 1997050116A1 US 9710574 W US9710574 W US 9710574W WO 9750116 A1 WO9750116 A1 WO 9750116A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- capacitor
- plate
- forming
- barrier layer
- dielectric
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
Definitions
- This invention relates to a capacitor, and methods for forming a capacitor.
- active device regions formed within the wafer substrate typically comprising monocrystalline silicon.
- the active device regions are connected by highly conductive paths or lines which are fabricated above an insulator material, and which covers the substrate surface.
- an opening or contact is provided to provide electrical connection between the conductive path and active device regions.
- an electrically conductive contact filling material is provided in the contact opening to make electrical contact to the underlying active device region.
- this intervening layer is typically provided to prevent the diffusion of the silicon and suicide with an associated plug filling material and to effectively adhere the plug filling material to the underlying substrate .
- Such material is accordingly also electrically conductive and commonly referred to as a 'barrier layer" due to the anti-diffusion properties of same .
- a lower electrode is typically electrically connected to another substrate device by means of a polysilicon plug.
- the barrier layer separates the polysilicon plug from the lower electrode of the capacitor to prevent both silicon diffusion into the electrode and oxidation of the plug which may be occasioned by the continued processing of the integrated circuit.
- a DRAM storage node capacitor is formed when a dielectric layer is interposed between a lower electrode and an upper electrode.
- the capacitor is typically covered and protected by a planarized layer of silicon dioxide .
- the capacitor is accessed by a bit line contact through a field effect transistor gated by a word line .
- the dielectric layer is typically deposited or otherwise annealed at a very high temperature and in an oxygen ambient. Under these processing conditions, oxidation of the underlying barrier layer, polysilicon plug or active area may undesirably occur. If oxide forms, a parasitic capacitor will be created. This parasitic capacitor would be disposed in series with the storage node capacitor. The resulting parasitic capacitor will prevent the full application of voltage to the storage node . This, in turn, will result in a decrease in the amount of charge which can be stored by the capacitor.
- designers of integrated circuits are often faced with difficulties in providing adequate coverage of high dielectric constant materials over typical capacitor geometries utilized in high density DRAMS and other memory circuitry.
- Figure 1 is a diagrammatic, sectional view of a prior art semiconductor wafer.
- Figure 2 is a diagrammatic, sectional view of a semiconductor wafer at one processing step in accordance with the present invention.
- Figure 3 is a view of the Figure 2 wafer at a processing step subsequent to that shown by Figure 2.
- Figure 4 is a view of the Figure 2 wafer at a processing step subsequent to that shown in Figure 3.
- Figure 5 is a view of the Figure 2 wafer at a processing step subsequent to that shown by Figure 4.
- Figure 6 is a view of the Figure 2 wafer at a processing step subsequent to that shown in Figure 5.
- Figure 7 is a view of the Figure 2 wafer at a processing step subsequent to that shown in Figure 6.
- Figure 8 is a view of the Figure 2 wafer at a processing step subsequent to that shown in Figure 7.
- Figure 9 is a view of the Figure 2 wafer at a processing step subsequent to that shown in Figure 8.
- Figure 10 is a view of the Figure 9 wafer at a processing step subsequent to that shown in Figure 9. Best Modes for Carrying Out the Invention and Disclosure of Invention
- One aspect of the present invention relates to a method for forming a capacitor which includes: providing a substrate having a node location to which electrical connection to a capacitor is to be made; forming an inner capacitor plate over the node location, the inner capacitor plate having an exposed sidewall; forming an oxidation barrier layer over the exposed inner capacitor plate sidewall; forming a capacitor dielectric plate over the inner capacitor plate , the oxidation barrier layer restricting oxidation of the inner capacitor plate sidewall during provision of the capacitor dielectric plate; and forming an outer capacitor plate over the capacitor dielectric plate .
- Another aspect of the present invention relates to a method for forming a capacitor which includes: providing a substrate having a node location to which electrical connection to a capacitor is to be made; forming a diffusion barrier layer over the node location; forming an inner capacitor plate over the diffusion barrier layer, the inner capacitor plate and diffusion barrier layer being patterned to respectively have an exposed sidewall; forming an oxidation barrier layer over the inner capacitor plate sidewall and diffusion barrier layer sidewall; forming a capacitor dielectric plate over the inner capacitor plate , the oxidation barrier layer restricting oxidation of at least the inner capacitor plate sidewall during provision of the capacitor dielectric plate; and forming an outer capacitor plate over the capacitor dielectric plate .
- a further aspect of the present invention relates to a capacitor which comprises: an inner capacitor plate having at least one sidewall; an oxidation barrier layer positioned in covering relation relative to at least one sidewall; a capacitor dielectric plate positioned over the inner capacitor plate; and an outer capacitor plate positioned over the capacitor dielectric plate .
- the capacitor 10 is formed relative to a silicon substrate 1 1 in association with DRAM integrated circuitry. A field oxide region 19 and a pair of word lines 16 and 17, are formed relative to the substrate 1 1.
- the capacitor 10 has a lower electrode 12; an upper electrode 13, which is spaced therefrom; and a dielectric layer 14 which is positioned intermediate the upper and lower electrodes 12 and 13, respectively.
- a diffusion barrier layer 15 is positioned between the lower electrode 12, and a planarized silicon dioxide layer 27.
- the planarized silicon dioxide layer 27 is formed outwardly of the substrate 1 1 , and the word lines 16 and 17.
- a polysilicon plug 20 is ohmically electrically connected to the diffusion barrier layer 15.
- the diffusion barrier layer 15 is formed to prevent the diffusion of silicon from the conductive plug 20 into the capacitor 10.
- One material of choice for use as a diffusion barrier layer 15 is titanium nitride. Titanium nitride is an attractive material as a contact diffusion barrier in integrated circuits because it behaves as a substantially impermeable barrier to the diffusion of silicon, and because the activation energy for the diffusion of other impurities is very high.
- Titanium nitride is also chemically and thermodynamically very stable and exhibits low electrical resistivity typical of the transition metal carbides, borides and nitrides. Titanium nitride can be provided or formed in one of the following manners: a) by evaporating titanium in a nitrogen ambient; b) reactively sputtering titanium in an argon and nitrogen mixture ; c) sputtering from a titanium nitride target in an inert argon ambient; d) sputter depositing titanium in an argon ambient and converting it to titanium nitride in a separate plasma nitridation step; or e) by low pressure chemical vapor deposition.
- the polysilicon plug 20 is electrically connected with an underlying diffusion region 21 formed in the silicon substrate 11 and which is associated with the word line 17.
- a planarized silicon dioxide layer 22 over lies outer capacitor electrode 13.
- An electrically conductive contact plug 23 is formed through silicon dioxide layer 22, and is in ohmic electrical contact with the outer capacitor cell plate 13.
- An interconnect line 24 is formed outwardly of the silicon dioxide layer 22, with the conductive plug 23 electrically connecting the interconnect line 24, with the upper cell plate 13.
- Preferred methods for fabricating the capacitor 10 include the deposit of a high dielectric constant material plate layer 14 at a high temperature and in an oxygen ambient. Under these processing conditions, if oxidation of the diffusion barrier layer 15, polysilicon plug 20, or underlying diffusion region 21 occurs, a parasitic capacitor will be formed in series with the capacitor 10. Further, the illustrated sidewalls of lower electrode 12 will oxidize , further adding to the undesired parasitic capacitor effects.
- the present method for forming a capacitor comprises the following steps: forming an inner capacitor plate layer, the inner capacitor plate layer having a sidewall; and forming a capacitor dielectric plate over the inner capacitor plate under conditions which would effectively oxidize the inner capacitor plate sidewall, the method comprising shielding the inner capacitor plate sidewall from substantial oxidation during the provision of the capacitor dielectric plate under said conditions. Preferred features of this method are discussed in detail in the paragraphs which follow.
- a silicon substrate 30 is provided, and has diffusion regions 31 and 32 formed therein.
- a field oxide region 33, and a pair of word lines 34 and 35 are also formed outwardly relative to the substrate 30.
- a layer of silicon dioxide 36 is provided outwardly of the silicon substrate 30 and is disposed in covering relation relative to the word lines 34 and 35.
- Electrical connection to the underlying region 31 is formed by opening a contact 37 to the underlying region 31 .
- a conductive plug 38 which is preferably polysilicon, is provided in the contact opening.
- the outermost portion of plug 38 constitutes a node location 29 to which electrical connection to a capacitor 10 is to be made .
- a diffusion barrier layer 50 for example titanium nitride or another transition metal nitride is formed to a thickness of about 500 Angstroms atop the silicon dioxide layer 36 and node location 29.
- an inner capacitor plate layer 60 is formed over the barrier layer 50 and accordingly the node location 29.
- the inner capacitor plate layer comprises platinum which is formed to a thickness of approximately 500 to about 3,000 Angstroms.
- conditions are provided which are effective to pattern and remove a portion of the diffusion barrier layer 50, and the inner capacitor plate layer 60 into a desired shape by means of a dry etching process.
- An example dry etching chemistry includes C l-> . The patterning and etching step above , results in the diffusion barrier layer 50 and plate layer 60 having exposed sidewalls 51 and 61 , respectively.
- the method further comprises forming an oxidation barrier layer 70, which is preferably a dielectric material, over the exposed inner capacitor plate sidewalls 61 and the diffusion barrier sidewalls 51.
- the preferred oxidation barrier layer 70 is silicon nitride which is formed to a thickness of about 500 Angstroms. Most preferably, the oxidation barrier layer 70 has a thickness which is less than the thickness dimension of the inner capacitor plate layer 60.
- an oxide layer 80 preferably comprising silicon dioxide, is formed atop the oxidation barrier layer 70.
- This silicon dioxide layer 80 is preferably formed to a thickness of greater than about 5,000 Angstroms.
- conditions are provided which are effective to planarize, preferably by means of chemical mechanical polishing (CMP) or resist etch-back, the silicon dioxide layer 80 relative to the oxidation barrier layer 70.
- the selected technique preferably has high selectivity for stopping on silicon nitride 70, as shown.
- a preferred CMP technique employs a slurry containing abrasive particles which selectively remove Si0-> when used in conjunction with a perforated pad rotating at low polishing speeds.
- the method further comprises removing the oxidation barrier layer 70 from atop the inner capacitor plate 60. This removal is preferably achieved by a dry etching chemistry having a high selectivity for etching silicon nitride relative to silicon dioxide .
- An example chemistry includes CF 4 or CF 4 in the presence of O2.
- the method further comprises forming a capacitor dielectric plate 90 atop the lower capacitor plate 60.
- the capacitor dielectric plate 90 comprises preferably a high dielectric constant material or a ferroelectric material.
- high dielectric constant means greater than about 20.
- Specific example materials include Ba ⁇ Sr ⁇ _ ⁇ TiO ⁇ ; PbZr ⁇ Ti ⁇ _ ⁇ 0- j and SrBi 2 Ta 2 0 9 .
- an outer capacitor plate 100 which is preferably platinum, is thereafter formed.
- the method of the present invention provides a means for forming a capacitor wherein the inner capacitor plate sidewall 61 is shielded from substantial oxidation during the provision of the capacitor dielectric plate 90 under normal processing conditions. Thus, parasitic capacitor formation is reduced or substantially eliminated.
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU35722/97A AU3572297A (en) | 1996-06-26 | 1997-06-23 | A capacitor and methods of forming a capacitor |
DE69736816T DE69736816T2 (en) | 1996-06-26 | 1997-06-23 | METHOD FOR PRODUCING A CONDENSER |
EP97932203A EP0958600B1 (en) | 1996-06-26 | 1997-06-23 | Method of forming a capacitor |
JP50329798A JP3822642B2 (en) | 1996-06-26 | 1997-06-23 | Capacitor formation method |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/670,644 US5843830A (en) | 1996-06-26 | 1996-06-26 | Capacitor, and methods for forming a capacitor |
US08/670,644 | 1996-06-26 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1997050116A1 true WO1997050116A1 (en) | 1997-12-31 |
Family
ID=24691238
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1997/010574 WO1997050116A1 (en) | 1996-06-26 | 1997-06-23 | A capacitor and methods of forming a capacitor |
Country Status (8)
Country | Link |
---|---|
US (3) | US5843830A (en) |
EP (1) | EP0958600B1 (en) |
JP (2) | JP3822642B2 (en) |
KR (1) | KR100411353B1 (en) |
AT (1) | ATE342581T1 (en) |
AU (1) | AU3572297A (en) |
DE (1) | DE69736816T2 (en) |
WO (1) | WO1997050116A1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6888189B2 (en) | 2000-11-08 | 2005-05-03 | Sanyo Electric Co., Ltd. | Dielectric element including oxide-based dielectric film and method of fabricating the same |
US7221015B2 (en) | 2002-03-18 | 2007-05-22 | Fujitsu Limited | Semiconductor device and method of manufacturing the same |
Families Citing this family (53)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6093575A (en) * | 1996-09-04 | 2000-07-25 | Nippon Steel Corporation | Semiconductor device and production method of a semiconductor device having a capacitor |
US6251720B1 (en) | 1996-09-27 | 2001-06-26 | Randhir P. S. Thakur | High pressure reoxidation/anneal of high dielectric constant materials |
US5910880A (en) * | 1997-08-20 | 1999-06-08 | Micron Technology, Inc. | Semiconductor circuit components and capacitors |
JP3090198B2 (en) * | 1997-08-21 | 2000-09-18 | 日本電気株式会社 | Structure of semiconductor device and method of manufacturing the same |
US6063713A (en) * | 1997-11-10 | 2000-05-16 | Micron Technology, Inc. | Methods for forming silicon nitride layers on silicon-comprising substrates |
US6911371B2 (en) * | 1997-12-19 | 2005-06-28 | Micron Technology, Inc. | Capacitor forming methods with barrier layers to threshold voltage shift inducing material |
US6165833A (en) | 1997-12-19 | 2000-12-26 | Micron Technology, Inc. | Semiconductor processing method of forming a capacitor |
KR100506513B1 (en) * | 1997-12-27 | 2007-11-02 | 주식회사 하이닉스반도체 | How to Form Ferroelectric Capacitors |
US6150706A (en) * | 1998-02-27 | 2000-11-21 | Micron Technology, Inc. | Capacitor/antifuse structure having a barrier-layer electrode and improved barrier layer |
US7034353B2 (en) | 1998-02-27 | 2006-04-25 | Micron Technology, Inc. | Methods for enhancing capacitors having roughened features to increase charge-storage capacity |
US6682970B1 (en) | 1998-02-27 | 2004-01-27 | Micron Technology, Inc. | Capacitor/antifuse structure having a barrier-layer electrode and improved barrier layer |
US6191443B1 (en) | 1998-02-28 | 2001-02-20 | Micron Technology, Inc. | Capacitors, methods of forming capacitors, and DRAM memory cells |
US6162744A (en) * | 1998-02-28 | 2000-12-19 | Micron Technology, Inc. | Method of forming capacitors having high-K oxygen containing capacitor dielectric layers, method of processing high-K oxygen containing dielectric layers, method of forming a DRAM cell having having high-K oxygen containing capacitor dielectric layers |
US6730559B2 (en) | 1998-04-10 | 2004-05-04 | Micron Technology, Inc. | Capacitors and methods of forming capacitors |
US6156638A (en) | 1998-04-10 | 2000-12-05 | Micron Technology, Inc. | Integrated circuitry and method of restricting diffusion from one material to another |
US6165834A (en) * | 1998-05-07 | 2000-12-26 | Micron Technology, Inc. | Method of forming capacitors, method of processing dielectric layers, method of forming a DRAM cell |
US6255186B1 (en) | 1998-05-21 | 2001-07-03 | Micron Technology, Inc. | Methods of forming integrated circuitry and capacitors having a capacitor electrode having a base and a pair of walls projecting upwardly therefrom |
JP2000138349A (en) * | 1998-10-30 | 2000-05-16 | Sharp Corp | Manufacture of semiconductor memory device |
US6159786A (en) * | 1998-12-14 | 2000-12-12 | Taiwan Semiconductor Manufacturing Company | Well-controlled CMP process for DRAM technology |
EP1150354A4 (en) * | 1999-02-04 | 2002-08-28 | Rohm Co Ltd | Capacitor and method of its manufacture |
US6696718B1 (en) * | 1999-04-06 | 2004-02-24 | Micron Technology, Inc. | Capacitor having an electrode formed from a transition metal or a conductive metal-oxide, and method of forming same |
TW454330B (en) * | 1999-05-26 | 2001-09-11 | Matsushita Electronics Corp | Semiconductor apparatus and its manufacturing method |
US6720096B1 (en) | 1999-11-17 | 2004-04-13 | Sanyo Electric Co., Ltd. | Dielectric element |
JP3976462B2 (en) * | 2000-01-26 | 2007-09-19 | エルピーダメモリ株式会社 | Manufacturing method of semiconductor device |
US6590246B1 (en) | 2000-02-08 | 2003-07-08 | Micron Technology, Inc. | Structures and methods for improved capacitor cells in integrated circuits |
US7005695B1 (en) | 2000-02-23 | 2006-02-28 | Micron Technology, Inc. | Integrated circuitry including a capacitor with an amorphous and a crystalline high K capacitor dielectric region |
US6339007B1 (en) | 2000-05-02 | 2002-01-15 | International Business Machines Corporation | Capacitor stack structure and method of fabricating description |
US6833329B1 (en) | 2000-06-22 | 2004-12-21 | Micron Technology, Inc. | Methods of forming oxide regions over semiconductor substrates |
US6686298B1 (en) | 2000-06-22 | 2004-02-03 | Micron Technology, Inc. | Methods of forming structures over semiconductor substrates, and methods of forming transistors associated with semiconductor substrates |
US6660657B1 (en) * | 2000-08-07 | 2003-12-09 | Micron Technology, Inc. | Methods of incorporating nitrogen into silicon-oxide-containing layers |
US6461909B1 (en) | 2000-08-30 | 2002-10-08 | Micron Technology, Inc. | Process for fabricating RuSixOy-containing adhesion layers |
US6903005B1 (en) | 2000-08-30 | 2005-06-07 | Micron Technology, Inc. | Method for the formation of RuSixOy-containing barrier layers for high-k dielectrics |
US6562684B1 (en) | 2000-08-30 | 2003-05-13 | Micron Technology, Inc. | Methods of forming dielectric materials |
US6410968B1 (en) | 2000-08-31 | 2002-06-25 | Micron Technology, Inc. | Semiconductor device with barrier layer |
US6521544B1 (en) | 2000-08-31 | 2003-02-18 | Micron Technology, Inc. | Method of forming an ultra thin dielectric film |
US6576964B1 (en) * | 2000-08-31 | 2003-06-10 | Micron Technology, Inc. | Dielectric layer for a semiconductor device having less current leakage and increased capacitance |
US6709945B2 (en) * | 2001-01-16 | 2004-03-23 | Micron Technology, Inc. | Reduced aspect ratio digit line contact process flow used during the formation of a semiconductor device |
JP2002231903A (en) | 2001-02-06 | 2002-08-16 | Sanyo Electric Co Ltd | Dielectric element and method of manufacturing the same |
US6696336B2 (en) * | 2001-05-14 | 2004-02-24 | Micron Technology, Inc. | Double sided container process used during the manufacture of a semiconductor device |
KR100420121B1 (en) * | 2001-06-21 | 2004-03-02 | 삼성전자주식회사 | Ferroelectric device using ferroelectric layer as planarization layer and method of forming the same |
US6878585B2 (en) | 2001-08-29 | 2005-04-12 | Micron Technology, Inc. | Methods of forming capacitors |
US6670717B2 (en) * | 2001-10-15 | 2003-12-30 | International Business Machines Corporation | Structure and method for charge sensitive electrical devices |
US6723599B2 (en) | 2001-12-03 | 2004-04-20 | Micron Technology, Inc. | Methods of forming capacitors and methods of forming capacitor dielectric layers |
JP2004063559A (en) * | 2002-07-25 | 2004-02-26 | Renesas Technology Corp | Semiconductor device |
US7008840B2 (en) * | 2002-08-26 | 2006-03-07 | Matsushita Electrical Industrial Co., Ltd. | Method for manufacturing semiconductor device with capacitor elements |
KR100492903B1 (en) * | 2002-11-13 | 2005-06-02 | 주식회사 하이닉스반도체 | Method of manufacturing capacitor for ferroelectric memory device |
KR20050002032A (en) * | 2003-06-30 | 2005-01-07 | 주식회사 하이닉스반도체 | Method for fabricating ferroelectric random access memory with merged-top electrode-plateline capacitor |
US7230292B2 (en) * | 2003-08-05 | 2007-06-12 | Micron Technology, Inc. | Stud electrode and process for making same |
US7256980B2 (en) * | 2003-12-30 | 2007-08-14 | Du Pont | Thin film capacitors on ceramic |
US7126182B2 (en) * | 2004-08-13 | 2006-10-24 | Micron Technology, Inc. | Memory circuitry |
US7776715B2 (en) * | 2005-07-26 | 2010-08-17 | Micron Technology, Inc. | Reverse construction memory cell |
US8742540B2 (en) * | 2005-08-31 | 2014-06-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Insulation layer to improve capacitor breakdown voltage |
JP4954614B2 (en) * | 2006-05-30 | 2012-06-20 | セイコーエプソン株式会社 | Method for manufacturing ferroelectric memory device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5335138A (en) * | 1993-02-12 | 1994-08-02 | Micron Semiconductor, Inc. | High dielectric constant capacitor and method of manufacture |
US5440157A (en) * | 1992-07-17 | 1995-08-08 | Kabushiki Kaisha Toshiba | Semiconductor integrated-circuit capacitor having a carbon film electrode |
US5442213A (en) * | 1993-06-23 | 1995-08-15 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with high dielectric capacitor having sidewall spacers |
Family Cites Families (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4464701A (en) * | 1983-08-29 | 1984-08-07 | International Business Machines Corporation | Process for making high dielectric constant nitride based materials and devices using the same |
JPS63221646A (en) * | 1987-03-10 | 1988-09-14 | Nec Corp | Semiconductor device |
JPH0479317A (en) * | 1990-07-23 | 1992-03-12 | Sony Corp | Production of semiconductor device |
US5262343A (en) * | 1991-04-12 | 1993-11-16 | Micron Technology, Inc. | DRAM stacked capacitor fabrication process |
JP2722873B2 (en) * | 1991-07-29 | 1998-03-09 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
JP3055242B2 (en) * | 1991-09-19 | 2000-06-26 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
JPH05109982A (en) * | 1991-10-18 | 1993-04-30 | Sharp Corp | Semiconductor device and its manufacture |
US5401680A (en) * | 1992-02-18 | 1995-03-28 | National Semiconductor Corporation | Method for forming a ceramic oxide capacitor having barrier layers |
JP3141553B2 (en) * | 1992-08-06 | 2001-03-05 | 日本電気株式会社 | Method for manufacturing semiconductor device |
JPH0685193A (en) * | 1992-09-07 | 1994-03-25 | Nec Corp | Semiconductor device |
JPH0783061B2 (en) * | 1993-01-05 | 1995-09-06 | 日本電気株式会社 | Semiconductor device |
KR950009813B1 (en) * | 1993-01-27 | 1995-08-28 | 삼성전자주식회사 | Semiconductor device and manufacturing method thereof |
US5471364A (en) * | 1993-03-31 | 1995-11-28 | Texas Instruments Incorporated | Electrode interface for high-dielectric-constant materials |
US5330931A (en) * | 1993-09-22 | 1994-07-19 | Northern Telecom Limited | Method of making a capacitor for an integrated circuit |
JPH07106431A (en) * | 1993-10-01 | 1995-04-21 | Mitsubishi Electric Corp | Semiconductor device |
JPH07176627A (en) * | 1993-12-17 | 1995-07-14 | Nec Corp | Fabrication of semiconductor device |
US5504041A (en) * | 1994-08-01 | 1996-04-02 | Texas Instruments Incorporated | Conductive exotic-nitride barrier layer for high-dielectric-constant materials |
US5489548A (en) * | 1994-08-01 | 1996-02-06 | Texas Instruments Incorporated | Method of forming high-dielectric-constant material electrodes comprising sidewall spacers |
JPH08162528A (en) * | 1994-10-03 | 1996-06-21 | Sony Corp | Interlayer insulating film structure of semiconductor device |
JPH08148470A (en) * | 1994-11-21 | 1996-06-07 | Sanyo Electric Co Ltd | Manufacture of semiconductor device |
KR0168346B1 (en) * | 1994-12-29 | 1998-12-15 | 김광호 | Capacitor using high deelectric material and its fabrication method |
US5567636A (en) * | 1995-02-27 | 1996-10-22 | Motorola Inc. | Process for forming a nonvolatile random access memory array |
KR100199346B1 (en) * | 1995-04-04 | 1999-06-15 | 김영환 | Electrode of capacitor fabrication method |
JPH08316430A (en) * | 1995-05-15 | 1996-11-29 | Mitsubishi Electric Corp | Semiconductor storage device, its manufacture, and stacked capacitor |
US5654222A (en) * | 1995-05-17 | 1997-08-05 | Micron Technology, Inc. | Method for forming a capacitor with electrically interconnected construction |
US5663088A (en) * | 1995-05-19 | 1997-09-02 | Micron Technology, Inc. | Method of forming a Ta2 O5 dielectric layer with amorphous diffusion barrier layer and method of forming a capacitor having a Ta2 O5 dielectric layer and amorphous diffusion barrier layer |
US5786248A (en) * | 1995-10-12 | 1998-07-28 | Micron Technology, Inc. | Semiconductor processing method of forming a tantalum oxide containing capacitor |
-
1996
- 1996-06-26 US US08/670,644 patent/US5843830A/en not_active Expired - Lifetime
-
1997
- 1997-06-23 WO PCT/US1997/010574 patent/WO1997050116A1/en active IP Right Grant
- 1997-06-23 JP JP50329798A patent/JP3822642B2/en not_active Expired - Lifetime
- 1997-06-23 AT AT97932203T patent/ATE342581T1/en not_active IP Right Cessation
- 1997-06-23 AU AU35722/97A patent/AU3572297A/en not_active Abandoned
- 1997-06-23 KR KR10-1998-0710676A patent/KR100411353B1/en not_active IP Right Cessation
- 1997-06-23 EP EP97932203A patent/EP0958600B1/en not_active Expired - Lifetime
- 1997-06-23 DE DE69736816T patent/DE69736816T2/en not_active Expired - Lifetime
- 1997-08-15 US US08/912,900 patent/US5844771A/en not_active Expired - Lifetime
-
1998
- 1998-11-03 US US09/185,412 patent/US6171925B1/en not_active Expired - Lifetime
-
2006
- 2006-03-27 JP JP2006084544A patent/JP2006216978A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5440157A (en) * | 1992-07-17 | 1995-08-08 | Kabushiki Kaisha Toshiba | Semiconductor integrated-circuit capacitor having a carbon film electrode |
US5335138A (en) * | 1993-02-12 | 1994-08-02 | Micron Semiconductor, Inc. | High dielectric constant capacitor and method of manufacture |
US5442213A (en) * | 1993-06-23 | 1995-08-15 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with high dielectric capacitor having sidewall spacers |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6888189B2 (en) | 2000-11-08 | 2005-05-03 | Sanyo Electric Co., Ltd. | Dielectric element including oxide-based dielectric film and method of fabricating the same |
US7221015B2 (en) | 2002-03-18 | 2007-05-22 | Fujitsu Limited | Semiconductor device and method of manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
US6171925B1 (en) | 2001-01-09 |
JP2001525986A (en) | 2001-12-11 |
ATE342581T1 (en) | 2006-11-15 |
KR100411353B1 (en) | 2004-04-13 |
US5843830A (en) | 1998-12-01 |
JP3822642B2 (en) | 2006-09-20 |
KR20000022256A (en) | 2000-04-25 |
EP0958600B1 (en) | 2006-10-11 |
DE69736816T2 (en) | 2007-08-09 |
DE69736816D1 (en) | 2006-11-23 |
JP2006216978A (en) | 2006-08-17 |
EP0958600A1 (en) | 1999-11-24 |
AU3572297A (en) | 1998-01-14 |
US5844771A (en) | 1998-12-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5843830A (en) | Capacitor, and methods for forming a capacitor | |
US5701647A (en) | Method for making an isolated sidewall capacitor having a compound plate electrode | |
US6750500B1 (en) | Capacitor electrode for integrating high K materials | |
EP1022783B1 (en) | Integrated circuit device having dual damascene capacitor | |
US6424043B1 (en) | Semiconductor processing methods of forming integrated circuitry memory devices, methods of forming capacitor containers, methods of making electrical connection to circuit nodes and related integrated circuitry | |
EP1020905B1 (en) | Method for making integrated circuit device having dual damascene interconnect structure and metal electrode capacitor | |
US6993814B2 (en) | Method of fabricating a capacitor having sidewall spacer protecting the dielectric layer | |
KR100643426B1 (en) | Tapered electrode for stacked capacitors | |
JP3999383B2 (en) | Method for forming capacitor having high dielectric material | |
US6184074B1 (en) | Method of fabrication a self-aligned polysilicon/diffusion barrier/oxygen stable sidewall bottom electrode structure for high-K DRAMS | |
US5631804A (en) | Contact fill capacitor having a sidewall that connects the upper and lower surfaces of the dielectric and partially surrounds an insulating layer | |
US20020030217A1 (en) | Semiconductor memory device having plug contacted to a capacitor electrode and method for fabricating a capacitor of the semiconductor memory device | |
US6218258B1 (en) | Method for fabricating semiconductor device including capacitor with improved bottom electrode | |
US6784052B2 (en) | Method of forming a capacitor with two diffusion barrier layers formed in the same step | |
US6525358B2 (en) | Capacitor having the lower electrode for preventing undesired defects at the surface of the metal plug | |
JP3666877B2 (en) | Semiconductor memory device and manufacturing method thereof | |
US6171898B1 (en) | Method of fabricating an oxygen-stable layer/diffusion barrier/poly bottom electrode structure for high-K-DRAMS using a disposable-oxide processing | |
US6180446B1 (en) | Method of fabricating an oxygen-stable layer/diffusion barrier/poly bottom electrode structure for high-K DRAMS using disposable-oxide processing | |
US20020074661A1 (en) | Semiconductor device and method of manufacturing the same | |
KR100213263B1 (en) | Fabrication method of high dielectric capacitor | |
US20030038314A1 (en) | Semiconductor device and method of manufacturing the same | |
KR100307539B1 (en) | Fabricating method of capacitor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GE GH HU IL IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT UA UG US UZ VN YU ZW AM AZ BY KG KZ MD RU TJ TM |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): GH KE LS MW SD SZ UG ZW AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL |
|
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 1019980710676 Country of ref document: KR |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1997932203 Country of ref document: EP |
|
REG | Reference to national code |
Ref country code: DE Ref legal event code: 8642 |
|
WWP | Wipo information: published in national office |
Ref document number: 1997932203 Country of ref document: EP |
|
WWP | Wipo information: published in national office |
Ref document number: 1019980710676 Country of ref document: KR |
|
NENP | Non-entry into the national phase |
Ref country code: CA |
|
WWG | Wipo information: grant in national office |
Ref document number: 1019980710676 Country of ref document: KR |
|
WWG | Wipo information: grant in national office |
Ref document number: 1997932203 Country of ref document: EP |