WO1998015014A1 - Capacitor with an electrode core and a thin noble metal layer used as a first electrode - Google Patents

Capacitor with an electrode core and a thin noble metal layer used as a first electrode Download PDF

Info

Publication number
WO1998015014A1
WO1998015014A1 PCT/DE1997/002153 DE9702153W WO9815014A1 WO 1998015014 A1 WO1998015014 A1 WO 1998015014A1 DE 9702153 W DE9702153 W DE 9702153W WO 9815014 A1 WO9815014 A1 WO 9815014A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode
capacitor
connection structure
noble metal
layer
Prior art date
Application number
PCT/DE1997/002153
Other languages
German (de)
French (fr)
Inventor
Carlos Mazure-Espejo
Walter Hartner
Günther SCHINDLER
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Publication of WO1998015014A1 publication Critical patent/WO1998015014A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material

Definitions

  • the invention relates to a capacitor in an integrated circuit, in particular in an integrated semiconductor memory.
  • capacitor of a DRAM memory cell the space requirement can be reduced by using a paraelectric with high permittivity (high- ⁇ dielectric) as the capacitor dielectric, so that a smaller capacitor area is required for a given capacitance value.
  • Such capacitors are preferably used in the memory as so-called "stacked" capacitors (the capacitor of the cell is arranged above an associated selection transistor).
  • Memory cells that use paraelectric materials as a capacitor dielectric lose their charge and thus their stored information when the supply voltage is selected. Furthermore, these cells must be constantly rewritten due to the residual leakage current (refresh time).
  • the use of a ferroelectric material as a capacitor dielectric enables the construction of a non-volatile memory (FRAM) due to the different polarization directions of the ferroelectric, which does not lose its information if the supply voltage fails and does not have to be constantly rewritten. The cell's residual leakage current does not affect the stored signal.
  • At least the first electrode is usually made essentially of a noble metal such as platinum or ruthenium.
  • these new electrode materials are relatively unknown substances for semiconductor technology. They are difficult to apply and can only be structured satisfactorily with a small layer thickness. Furthermore, they are permeable to oxygen, which has the consequence that deeper structures are oxidized during the production of the capacitor dielectric and adequate contact between the first electrode and the selection transistor is not guaranteed. Therefore, a barrier below the capacitor dielectric is required that suppresses oxygen diffusion.
  • the capacitor with the high- ⁇ dielectric or ferroelectric as a capacitor dielectric has mostly been produced as a planar capacitor after the completion of the conventional CMOS transistor structure over the insulation region, which separates adjacent memory cells from one another.
  • the advantage here is that a sputtering or sol-gel process can be used to produce the planar capacitor dielectric, and furthermore that by applying the dielectric, which takes place in a strongly oxidizing environment, the diffusion of oxygen through the first electrode through the underlying layer can no longer harm, since there is already an oxide here. If one were to apply the ferro- or dielectric layer directly over the connection structure to the transistor, one would get find onoxidation no conductive connection.
  • the metallization usually takes place after the capacitor has been completed, because the deposition temperature is above the melting temperature of the aluminum.
  • a disadvantage of this cell concept is the large space requirement of the planar capacitor and the resulting memory cell.
  • the object of the present invention is to provide a capacitor with a high- ⁇ dielectric or ferroelectric as a capacitor dielectric, which is simple to manufacture and which requires little space when integrated in a memory cell.
  • a manufacturing method for such a capacitor is also to be specified.
  • the first electrode of the capacitor consists of an electrode core and a thin, noble metal-containing layer arranged thereon.
  • the electrode core consists of the same material as the connection structure (plug) or the barrier or is composed of these two materials.
  • the lower electrode is thus essentially formed from the plug or the barrier material and only has a coating of platinum, for example.
  • platinum alternatively indium, ruthenium, palladium etc., or a conductive oxide such as Ru0 2 , Ir0 2 etc. can be used.
  • connection structure for example nitrides or carbides such as WN, WC, WTiN, TaN, TiN, TiC etc. can be used as barrier material. These materials are easier to structure than platinum, suitable etching processes are known to the person skilled in the art.
  • the connection structure is through the barrier in front of the oxygen-containing atmosphere protected against oxidation during the deposition of the capacitor dielectric. This is followed by a thin layer containing precious metal, which is easier to structure than a thick layer.
  • the capacitor dielectric and the second electrode are then produced.
  • the second electrode preferably also has a thin layer containing noble metal at its interface with the capacitor dielectric (symmetry effects, in particular of the leakage current and the ferroelectric hysteresis curve).
  • connection structure can be produced by selective contact hole filling or by full-surface deposition with a subsequent etching process. In this etching process, the electrode core is preferably produced at the same time.
  • a self-aligned barrier can be created by RTP nitriding (rapid thermal processing) with nitrogen-containing gases.
  • FIGS. 1 and 2 The invention is explained in more detail below with reference to two exemplary embodiments which are shown in FIGS. 1 and 2.
  • FIG. 1 shows a cross section through a silicon semiconductor substrate 1 with a so-called stacked capacitor memory cell.
  • Two S / D regions 3, 4 of the selection transistor and an insulation region 2 for the isolation of an adjacent cell are arranged on the substrate surface.
  • the selection transistor further comprises a gate 5 applied insulated on the substrate surface.
  • the substrate surface is covered with an insulation layer 6, 7, which in this case consists of a silicon oxide / silicon nitride double layer.
  • a contact hole is etched into this insulation layer 6, 7 using a known method, which exposes the S / D region 3.
  • Tungsten is deposited over the entire surface and structured with the aid of a photographic technique in such a way that one filled contact hole (connection structure 8) and one remaining above it Part 9 of the Wolfra layer is formed.
  • a known etching process can be used for this.
  • An RTP nitridation is now carried out, so that a barrier 10 of tungsten nitride which is self-aligned to the layer part 9 and which completely covers the tungsten 9 is produced.
  • the remaining tungsten 9 and the barrier 10 together form the electrode core of the first electrode.
  • a thin platinum layer 11 is applied and structured.
  • Argon ion etching can be used for this.
  • the remaining platinum layer 11 virtually covers the entire barrier 10 and possibly a part of the surrounding insulation layer 7.
  • the upper part of the insulation layer made of silicon nitride ensures an improved adhesion of the platinum to the insulation layer, since silicon nitride acts as an adhesion promoter for noble metal layers.
  • the first electrode is therefore composed of tungsten 9 (at the same time material of the connection structure 8) and the barrier 10, which together form the electrode core, and the thin platinum layer 11.
  • the shape of the first electrode is essentially due to the structuring of the tungsten 9 determined.
  • the high- ⁇ capacitor dielectric 12 BST and the second electrode 13 made of platinum, for example, are applied.
  • FIG. 2 shows a second exemplary embodiment of the invention, only the differences from FIG. 1 being explained below.
  • the connection structure 8 consists of selectively deposited tungsten or doped polysilicon, its upper edge lies in one plane with the upper edge of the insulation layer 7.
  • a titanium nitride layer is applied thereon and structured to form the electrode core.
  • the remaining titanium nitride 10 also represents the oxygen barrier.
  • a thin platinum layer 11 is applied thereon.
  • the barrier 10 and the platinum layer 11 together form the first electrode, the shape of the first electrode being determined by the barrier 10 as the electrode core. The further procedure is as described above.

Abstract

A capacitor with a high ε dielectric or ferroelectric layer as a capacitor dialectric wherein the first electrode consists of an electrode core covered by a thin layer containing noble metal. The electrode core is made from material of a connecting structure and/or an oxygen barrier.

Description

Beschreibungdescription
Kondensator mit einem Elektrodenkern und einer dünnen Edelme- tallschicht als erster ElektrodeCapacitor with an electrode core and a thin layer of precious metal as the first electrode
Die Erfindung betrifft einen Kondensator in einer integrierten Schaltung, insbesondere in einem integrierten Halbleiterspeicher.The invention relates to a capacitor in an integrated circuit, in particular in an integrated semiconductor memory.
In integrierten Halbleiterschaltungen, beispielsweise in integrierten Speichern, ist die Erhöhung der Integrationsdichte ein vorrangiges Ziel. Bei einem Kondensator einer DRAM-Speicherzelle kann der Platzbedarf dadurch verringert werden, daß als Kondensator Dielektrikum ein Paraelektrikum mit hoher Permittivität (Hoch-ε-Dielektrikum) verwendet wird, so daß für einen vorgegebenen Kapazitätswert eine geringere Kondensatorfläche benötigt wird. Solche Kondensatoren werden in dem Speicher vorzugsweise als sogenannte "Stacked" -Kondensatoren (der Kondensator der Zelle ist oberhalb eines zugehörigen Auswahltransistors angeordnet) eingesetzt.In integrated semiconductor circuits, for example in integrated memories, increasing the integration density is a primary goal. With a capacitor of a DRAM memory cell, the space requirement can be reduced by using a paraelectric with high permittivity (high-ε dielectric) as the capacitor dielectric, so that a smaller capacitor area is required for a given capacitance value. Such capacitors are preferably used in the memory as so-called "stacked" capacitors (the capacitor of the cell is arranged above an associated selection transistor).
Speicherzellen, die als Kondensatordielektrikum paraelektrische Materialien benutzen, verlieren bei Auswahl der Versorgungsspannung ihre Ladung und somit ihre gespeicherte Infor- mation. Ferner müssen diese Zellen wegen des Rest-Leckstroms ständig neu beschrieben werden (Refresh-Time) . Der Einsatz eines ferroelektrischen Materials als Kondensatordielektrikum ermöglicht aufgrund der unterschiedlichen Polarisationsrichtungen des Ferroelektrikums den Bau eines nicht-flüchtigen Speichers (FRAM) , der seine Information bei Ausfall der VersorgungsSpannung nicht verliert und auch nicht ständig neu beschrieben werden muß. Der Rest-Leckstrom der Zelle beeinflußt nicht das gespeicherte Signal.Memory cells that use paraelectric materials as a capacitor dielectric lose their charge and thus their stored information when the supply voltage is selected. Furthermore, these cells must be constantly rewritten due to the residual leakage current (refresh time). The use of a ferroelectric material as a capacitor dielectric enables the construction of a non-volatile memory (FRAM) due to the different polarization directions of the ferroelectric, which does not lose its information if the supply voltage fails and does not have to be constantly rewritten. The cell's residual leakage current does not affect the stored signal.
Zur Lösung der genannten Probleme sind verschiedene Hoch-ε- Dielektrika und Ferroelektrika aus der Literatur bekannt . Beispiele sind Barium-Strontium-Titanat (BST) , Strontium- Titanat (ST) oder Blei-Zirconium-Titanat (PZT) , wie beispielsweise in den Artikeln Jap. Journal of Applied Physics, Vol. 34 (1995), Seiten 5178 bis 5183 und Seiten 5224 bis 5229 beschrieben. Die Herstellung dieser Materialien erfolgt durch einen Sputter-, Spin-on- oder Abscheideprozeß, der hohe Temperaturen in einer sauerstoffhaltigen Atmosphäre benötigt. Dies hat zur Folge, daß die in der Halbleitertechnologie als Elektrodenmaterial verwendeten leitfähigen Materialien (zum Beispiel Polysilizium, Aluminium oder Wolfram) ungeeignet sind, da sie unter diesen Bedingungen oxidieren. Daher wird zumindest die erste Elektrode üblicherweise im wesentlichen aus einem Edelmetall wie Platin oder Ruthenium hergestellt. Diese neuen Elektrodenmaterialien sind jedoch für die Halbleitertechnologie relativ unbekannte Substanzen. Sie sind schwierig aufzubringen und nur bei geringer Schichtdicke befriedigend strukturierbar. Ferner sind sie sauerstoffdurchlässig, was zur Folge hat, daß während der Herstellung des Kondensatordielektrikums tieferliegende Strukturen oxidiert werden und ein ausreichender Kontakt zwischen erster Elektro- de und dem Auswahltransistor nicht gewährleistet ist. Daher ist eine Barriere unterhalb des Kondensatordielektrikums notwendig, die eine Sauerstof diffusion unterdrückt.Various high-ε dielectrics and ferroelectrics are known from the literature for solving the problems mentioned. Examples are barium strontium titanate (BST), strontium Titanate (ST) or lead zirconium titanate (PZT), as for example in the articles Jap. Journal of Applied Physics, Vol. 34 (1995), pages 5178 to 5183 and pages 5224 to 5229. These materials are produced by a sputtering, spin-on or deposition process which requires high temperatures in an oxygen-containing atmosphere. As a result, the conductive materials (for example polysilicon, aluminum or tungsten) used as the electrode material in semiconductor technology are unsuitable because they oxidize under these conditions. Therefore, at least the first electrode is usually made essentially of a noble metal such as platinum or ruthenium. However, these new electrode materials are relatively unknown substances for semiconductor technology. They are difficult to apply and can only be structured satisfactorily with a small layer thickness. Furthermore, they are permeable to oxygen, which has the consequence that deeper structures are oxidized during the production of the capacitor dielectric and adequate contact between the first electrode and the selection transistor is not guaranteed. Therefore, a barrier below the capacitor dielectric is required that suppresses oxygen diffusion.
Bisher wurde der Kondensator mit dem Hoch-ε-Dielektrikum oder Ferroelektrikum als Kondensatordielektrikum meist nach Fertigstellung der konventionellen CMOS-Transistor-Struktur über dem Isolationsgebiet, das benachbarte Speicherzellen voneinander trennt, als planarer Kondensator hergestellt. Der Vorteil dabei ist, daß zur Herstellung des planaren Kondensator- dielektrikums ein Sputter- oder Solgelverfahren benutzt werden kann, und daß ferner durch das Aufbringen des Dielektrikums, das in stark oxidierender Umgebung stattfindet, die Diffusion des Sauerstoffs durch die erste Elektrode hindurch der darunterliegenden Schicht nicht mehr schaden kann, da sich hier bereits ein Oxid befindet. Würde man die ferro- oder dielektrische Schicht direkt über der Anschlußstruktur zum Transistor aufbringen, erhielte man aufgrund der statt- findenden Aufoxidation keine leitfähige Verbindung. Die Metallisierung erfolgt üblicherweise nach der Fertigstellung des Kondensators, weil die Abscheidetemperatur über der Schmelztemperatur des Aluminiums liegt. Nachteilig bei diesem Zellkonzept ist der große Platzbedarf des planaren Kondensators und der daraus resultierenden Speicherzelle.So far, the capacitor with the high-ε dielectric or ferroelectric as a capacitor dielectric has mostly been produced as a planar capacitor after the completion of the conventional CMOS transistor structure over the insulation region, which separates adjacent memory cells from one another. The advantage here is that a sputtering or sol-gel process can be used to produce the planar capacitor dielectric, and furthermore that by applying the dielectric, which takes place in a strongly oxidizing environment, the diffusion of oxygen through the first electrode through the underlying layer can no longer harm, since there is already an oxide here. If one were to apply the ferro- or dielectric layer directly over the connection structure to the transistor, one would get find onoxidation no conductive connection. The metallization usually takes place after the capacitor has been completed, because the deposition temperature is above the melting temperature of the aluminum. A disadvantage of this cell concept is the large space requirement of the planar capacitor and the resulting memory cell.
Aufgabe der vorliegenden Erfindung ist es, einen Kondensator mit einem Hoch-ε-Dielektrikum oder Ferroelektrikum als Kon- densatordielektrikum anzugeben, der einfach herstellbar ist und bei Integration in einer Speicherzelle einen geringen Platzbedarf aufweist. Ferner soll ein Herstellverfahren für einen solchen Kondensator angegeben werden.The object of the present invention is to provide a capacitor with a high-ε dielectric or ferroelectric as a capacitor dielectric, which is simple to manufacture and which requires little space when integrated in a memory cell. A manufacturing method for such a capacitor is also to be specified.
Diese Aufgabe wird durch einen Kondensator mit den Merkmalen des Patentanspruchs 1 sowie durch ein Verfahren mit den Merkmalen des Patentanspruchs 8 gelöst. Weiterbildungen sind Gegenstand von Unteransprüchen.This object is achieved by a capacitor with the features of patent claim 1 and by a method with the features of patent claim 8. Further training is the subject of subclaims.
Bei der Erfindung besteht die erste Elektrode des Kondensators aus einem Elektrodenkern und einer darauf angeordneten dünnen edelmetallhaltigen Schicht. Der Elektrodenkern besteht aus dem gleichen Material wie die Anschlußstruktur (Plug) oder die Barriere oder setzt sich aus diesen beiden Materia- lien zusammen. Die untere Elektrode wird also im wesentlichen aus dem Plug- oder dem Barrierenmaterial geformt und besitzt lediglich eine Auflage aus beispielsweise Platin. Anstelle von Platin kann alternativ Indium, Ruthenium, Palladium etc., oder ein leitendes Oxid wie Ru02 , Ir02 etc. eingesetzt wer- den.In the invention, the first electrode of the capacitor consists of an electrode core and a thin, noble metal-containing layer arranged thereon. The electrode core consists of the same material as the connection structure (plug) or the barrier or is composed of these two materials. The lower electrode is thus essentially formed from the plug or the barrier material and only has a coating of platinum, for example. Instead of platinum, alternatively indium, ruthenium, palladium etc., or a conductive oxide such as Ru0 2 , Ir0 2 etc. can be used.
Für die Anschlußstruktur wird bevorzugt Wolfram oder Polysi- lizium eingesetzt, als Barrierenmaterial können beispielsweise Nitride oder Carbide wie WN, WC, WTiN, TaN, TiN, TiC usw. verwendet werden. Diese Materialien sind leichter zu strukturieren als Platin, geeignete Ätzprozesse sind dem Fachmann bekannt. Die Anschlußstruktur wird durch die Barriere vor der sauerstoffhaltigen Atmospähre bei der Abscheidung des Kondensatordielektrikums vor der Oxidation geschützt . Hierauf folgt nun eine dünne edelmetallhaltige Schicht, die sich leichter strukturieren läßt als eine dicke Schicht. Danach werden das Kondensatordielektrikum und die zweite Elektrode hergestellt. Vorzugsweise besitzt die zweite Elektrode an ihrer Grenzfläche zum Kondensatordielektrikum ebenfalls eine dünne edelmetallhaltige Schicht (Symmetrieeffekte, insbesondere des Leckstroms und der ferroelektrischen Hysteresekurve) .Tungsten or polysilicon is preferably used for the connection structure, for example nitrides or carbides such as WN, WC, WTiN, TaN, TiN, TiC etc. can be used as barrier material. These materials are easier to structure than platinum, suitable etching processes are known to the person skilled in the art. The connection structure is through the barrier in front of the oxygen-containing atmosphere protected against oxidation during the deposition of the capacitor dielectric. This is followed by a thin layer containing precious metal, which is easier to structure than a thick layer. The capacitor dielectric and the second electrode are then produced. The second electrode preferably also has a thin layer containing noble metal at its interface with the capacitor dielectric (symmetry effects, in particular of the leakage current and the ferroelectric hysteresis curve).
Die Anschlußstruktur kann durch eine selektive Kontaktlochauffüllung oder durch eine ganzflächige Abscheidung mit einem anschließenden Ätzprozeß hergestellt werden. Bei diesem Ätz- prozeß wird vorzugsweise gleichzeitig der Elektrodenkem her- gestellt. Bei einer aus Wolfram bestehenden Anschlußstruktur kann eine dazu selbstjustierte Barriere durch eine RTP-Nitri- dation (Rapid Thermal Processing) mit stickstoffhaltigen Gasen erzeugt werden.The connection structure can be produced by selective contact hole filling or by full-surface deposition with a subsequent etching process. In this etching process, the electrode core is preferably produced at the same time. In the case of a connection structure consisting of tungsten, a self-aligned barrier can be created by RTP nitriding (rapid thermal processing) with nitrogen-containing gases.
Die Erfindung wird im folgenden anhand zweier Ausführungsbeispiele, die in den Figuren 1 und 2 dargestellt sind, näher erläutert .The invention is explained in more detail below with reference to two exemplary embodiments which are shown in FIGS. 1 and 2.
Figur 1 zeigt einen Querschnitt durch ein Silizium-Halblei- tersubstrat 1 mit einer sogenannten Stacked-Capacitor-Spei- cherzelle. An der Substratoberflache sind zwei S/D-Gebiete 3, 4 des Auswahltransistors sowie ein Isolationsgebiet 2 zur Isolation von einer benachbarten Zellen angeordnet. Der Aus- wahltransistor umfaßt ferner ein isoliert auf der Substrato- berflache aufgebrachtes Gate 5. Die Substratoberflache ist mit einer Isolationsschicht 6, 7 bedeckt, die in diesem Fall aus einer Siliziumoxid/Siliziumnitrid-Doppelschicht besteht. In diese Isolationsschicht 6, 7 wird ein Kontaktloch mit einem bekannten Verfahren geätzt, das das S/D-Gebiet 3 frei- legt. Es wird ganzflächig Wolfram abgeschieden und mit Hilfe einer Fototechnik so strukturiert, daß ein aufgefülltes Kontaktloch (Anschlußstruktur 8) und ein darüber verbleibender Teil 9 der Wolfra schicht gebildet wird. Dafür kann ein bekannter Ätzprozeß eingesetzt werden. Nun wird eine RTP- Nitridation durchgeführt, so daß eine zum Schichtteil 9 selbstjustierte Barriere 10 aus Wolframnitrid erzeugt wird, die das Wolfram 9 vollständig bedeckt. Das verbleibende Wolfram 9 und die Barriere 10 bilden zusammen den Elektrodenkern der ersten Elektrode. Anschließend wird eine dünne Platin- Schicht 11 aufgebracht und strukturiert . Dazu kann eine Argon-Ionen-Ätzung eingesetzt werden. Die verbleibende Platin- Schicht 11 bedeckt quasi als Auflage die gesamte Barriere 10 und gegebenenfalls einen Teil der umgebenden Isolations- schicht 7. Der obere Teil der Isolationsschicht aus Siliziumnitrid gewährleistet eine verbesserte Haftung des Platins auf der Isolationsschicht, da Siliziumnitrid als Haftvermittler für Edelmetallschichten wirkt. Die erste Elektrode setzt sich also zusammen aus Wolfram 9 (gleichzeitig Material der Anschlußstruktur 8) und der Barriere 10, die zusammen den Elektrodenkern bilden, sowie der dünnen Platin-Schicht 11. Die Form der ersten Elektrode ist dabei im wesentlichen durch die Strukturierung des Wolfram 9 bestimmt. Schließlich wird das Hoch-ε-Kondensatordielektrikum 12 BST und darauf die zweite Elektrode 13 beispielsweise aus Platin aufgebracht.FIG. 1 shows a cross section through a silicon semiconductor substrate 1 with a so-called stacked capacitor memory cell. Two S / D regions 3, 4 of the selection transistor and an insulation region 2 for the isolation of an adjacent cell are arranged on the substrate surface. The selection transistor further comprises a gate 5 applied insulated on the substrate surface. The substrate surface is covered with an insulation layer 6, 7, which in this case consists of a silicon oxide / silicon nitride double layer. A contact hole is etched into this insulation layer 6, 7 using a known method, which exposes the S / D region 3. Tungsten is deposited over the entire surface and structured with the aid of a photographic technique in such a way that one filled contact hole (connection structure 8) and one remaining above it Part 9 of the Wolfra layer is formed. A known etching process can be used for this. An RTP nitridation is now carried out, so that a barrier 10 of tungsten nitride which is self-aligned to the layer part 9 and which completely covers the tungsten 9 is produced. The remaining tungsten 9 and the barrier 10 together form the electrode core of the first electrode. Then a thin platinum layer 11 is applied and structured. Argon ion etching can be used for this. The remaining platinum layer 11 virtually covers the entire barrier 10 and possibly a part of the surrounding insulation layer 7. The upper part of the insulation layer made of silicon nitride ensures an improved adhesion of the platinum to the insulation layer, since silicon nitride acts as an adhesion promoter for noble metal layers. The first electrode is therefore composed of tungsten 9 (at the same time material of the connection structure 8) and the barrier 10, which together form the electrode core, and the thin platinum layer 11. The shape of the first electrode is essentially due to the structuring of the tungsten 9 determined. Finally, the high-ε capacitor dielectric 12 BST and the second electrode 13 made of platinum, for example, are applied.
Figur 2 zeigt ein zweites Ausführungsbeispiel der Erfindung, wobei im folgenden nur die Unterschiede zu Figur 1 erläutert werden. Die Anschlußstruktur 8 besteht in diesem Fall aus selektiv abgeschiedenem Wolfram oder aus dotiertem Polysilizi- um, ihre Oberkante liegt in einer Ebene mit der Oberkante der Isolationsschicht 7. Darauf wird eine Titannitrid-Schicht aufgebracht und zu dem Elektrodenkem strukturiert. Das verbleibende Titannitrid 10 stellt gleichzeitig die Sauerstoffbarriere dar. ie im ersten Ausführungsbeispiel ist darauf eine dünne Platin-Schicht 11 aufgebracht. Die Barriere 10 und die Platin-Schicht 11 bilden zusammen die erste Elektrode, die Form der ersten Elektrode wird dabei durch die Barriere 10 als Elektrodenkern bestimmt. Das weitere Vorgehen ist wie oben beschrieben. FIG. 2 shows a second exemplary embodiment of the invention, only the differences from FIG. 1 being explained below. In this case, the connection structure 8 consists of selectively deposited tungsten or doped polysilicon, its upper edge lies in one plane with the upper edge of the insulation layer 7. A titanium nitride layer is applied thereon and structured to form the electrode core. The remaining titanium nitride 10 also represents the oxygen barrier. In the first exemplary embodiment, a thin platinum layer 11 is applied thereon. The barrier 10 and the platinum layer 11 together form the first electrode, the shape of the first electrode being determined by the barrier 10 as the electrode core. The further procedure is as described above.

Claims

Patentansprüche claims
1. Kondensator in einer integrierten Halbleiterschaltung1. Capacitor in a semiconductor integrated circuit
• mit einer ersten Elektrode (9, 10, 11), die über eine An- Schlußstruktur (8) an ein leitfähiges Gebiet (3) in einem• With a first electrode (9, 10, 11), which is connected to a conductive area (3) in one via a connection structure (8)
Halbleitersubstrat (l) angeschlossen ist,Semiconductor substrate (l) is connected,
• mit einer zweiten Elektrode (13) ,With a second electrode (13),
• mit einem Kondensatordielektrikum (12) , das die erste und zweite Elektrode voneiander isoliert und aus einem Hoch-ε- Dielektrikum oder einem Ferroelektrikum besteht,With a capacitor dielectric (12) which insulates the first and second electrodes from one another and consists of a high-ε dielectric or a ferroelectric,
• mit einer Barriere (10) , die unterhalb des Kondensatordielektrikums (12) angeordnet ist, wobei die erste Elektrode einen Elektrodenkern (9, 10) und eine demgegenüber dünne edelmetallhaltigen Schicht (11) um- faßt, und der Elektrodenkern (9, 10) aus dem Material der Anschlußstruktur (8) und/oder der Barriere (10) besteht.• with a barrier (10), which is arranged below the capacitor dielectric (12), the first electrode comprising an electrode core (9, 10) and a thin, noble metal-containing layer (11), and the electrode core (9, 10) consists of the material of the connection structure (8) and / or the barrier (10).
2. Kondensator nach Anspruch 1, bei dem die Anschlußstruktur aus Wolfram besteht.2. A capacitor according to claim 1, wherein the connection structure consists of tungsten.
3. Kondensator nach einem der Ansprüche 1 bis 2, bei dem die Barriere aus einem leitfähigen Nitrid besteht.3. Capacitor according to one of claims 1 to 2, wherein the barrier consists of a conductive nitride.
4. Kondensator nach einem der Ansprüche 1 bis 3 , bei dem die zweite Elektrode eine edelmetallhaltige Schicht unfaßt, die an das Kondensatordielektrikum (11) angrenzt.4. Capacitor according to one of claims 1 to 3, wherein the second electrode comprises a noble metal-containing layer which is adjacent to the capacitor dielectric (11).
5. Kondensator nach einem der Ansprüche 1 bis 4, bei dem die erste Elektrode die Anschlußstruktur (8) und eine zur Anschlußstruktur benachbarte Isolationsschicht (6, 7) bedeckt .5. A capacitor according to any one of claims 1 to 4, wherein the first electrode covers the connection structure (8) and an insulation layer (6, 7) adjacent to the connection structure.
6. Kondensator nach Anspruch 5 , bei dem die Isolationsschicht in ihrem oberen Teil aus Sili- ziumnitrid besteht. 6. A capacitor according to claim 5, in which the insulation layer consists in its upper part of silicon nitride.
7. Kondensator nach einem der Ansprüche 1 bis 6, bei dem die edelmetallhaltige Schicht (11) aus Platin besteht.7. Capacitor according to one of claims 1 to 6, wherein the noble metal-containing layer (11) consists of platinum.
8. Herstellverfahren für einen Kondensator in einer integrierten Halbleiterschaltung,8. Manufacturing method for a capacitor in an integrated semiconductor circuit,
• bei dem auf einem Substrat (1) ein Elektrodenkern (9, 10) erzeugt wird, der über einen Anschlußstruktur (8) mit einem leitfähigen Gebiet (3) im Halbleitersubstrat (l) verbunden ist, und der eine Sauerstoffbarriere (10) umfaßt,In which an electrode core (9, 10) is produced on a substrate (1), which is connected via a connection structure (8) to a conductive region (3) in the semiconductor substrate (1) and which comprises an oxygen barrier (10),
• bei dem auf dem Elektrodenkem (9, 10) eine edelmetallhaltige Schicht (11) erzeugt wird, die eine geringere Schichtdicke als der Elektrodenkem aufweist und die gesamte freiliegende Oberfläche des Elektrodenkerns bedeckt, • bei dem auf der edelmetallhaltigen Schicht (11) ein Kondensatordielektrikum (12) erzeugt wird, das aus einem Hoch-ε- Dielektrikum oder Ferroelektrikum besteht,• in which a layer (11) containing noble metal is produced on the electrode core (9, 10), which has a smaller layer thickness than the electrode core and covers the entire exposed surface of the electrode core, • in which a capacitor dielectric (on the layer containing noble metal (11) 12) is generated, which consists of a high-ε dielectric or ferroelectric,
• bei dem auf dem Kondensatordielektrikum (12) eine zweite Elektrode (13) erzeugt wird.• in which a second electrode (13) is generated on the capacitor dielectric (12).
9. Herstellverfahren nach Anspruch 8, bei dem die Anschlußstruktur (8) aus Wolfram besteht.9. The manufacturing method according to claim 8, wherein the connection structure (8) consists of tungsten.
10. Herstellverfahren nach Anspruch 9, bei dem eine selbstjustierte Barriere (10) durch Nitridation erzeugt wird. 10. The manufacturing method according to claim 9, wherein a self-aligned barrier (10) is generated by nitridation.
PCT/DE1997/002153 1996-09-30 1997-09-23 Capacitor with an electrode core and a thin noble metal layer used as a first electrode WO1998015014A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE1996140244 DE19640244A1 (en) 1996-09-30 1996-09-30 Capacitor with an electrode core and a thin layer of precious metal as the first electrode
DE19640244.1 1996-09-30

Publications (1)

Publication Number Publication Date
WO1998015014A1 true WO1998015014A1 (en) 1998-04-09

Family

ID=7807404

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1997/002153 WO1998015014A1 (en) 1996-09-30 1997-09-23 Capacitor with an electrode core and a thin noble metal layer used as a first electrode

Country Status (2)

Country Link
DE (1) DE19640244A1 (en)
WO (1) WO1998015014A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19842684C1 (en) * 1998-09-17 1999-11-04 Siemens Ag Integrated circuit high-permittivity capacitor arranged on support structure in semiconductor arrangement e.g. for DRAM circuit or ADC

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000183296A (en) * 1998-12-16 2000-06-30 Rohm Co Ltd Semiconductor device and its manufacture
DE19919110C2 (en) * 1999-04-27 2002-06-27 Infineon Technologies Ag Process for structuring a metal or metal silicide layer and a capacitor produced with this process
JP2001237395A (en) * 2000-02-22 2001-08-31 Matsushita Electric Ind Co Ltd Semiconductor memory device
US6583507B1 (en) * 2002-04-26 2003-06-24 Bum Ki Moon Barrier for capacitor over plug structures

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0697717A1 (en) * 1994-08-01 1996-02-21 Texas Instruments Incorporated Method of making electrical connections to materials with high-dielectric-constant
US5506166A (en) * 1993-04-02 1996-04-09 Micron Technology, Inc. Method for forming capacitor compatible with high dielectric constant materials having a low contact resistance layer
DE19608182A1 (en) * 1995-03-04 1996-09-19 Lg Semicon Co Ltd Dielectric thin film for use in semiconductor memory device capacitor
US5566045A (en) * 1994-08-01 1996-10-15 Texas Instruments, Inc. High-dielectric-constant material electrodes comprising thin platinum layers

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0730077A (en) * 1993-06-23 1995-01-31 Mitsubishi Electric Corp Semiconductor device and manufacturing method thereof
US5504041A (en) * 1994-08-01 1996-04-02 Texas Instruments Incorporated Conductive exotic-nitride barrier layer for high-dielectric-constant materials

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5506166A (en) * 1993-04-02 1996-04-09 Micron Technology, Inc. Method for forming capacitor compatible with high dielectric constant materials having a low contact resistance layer
EP0697717A1 (en) * 1994-08-01 1996-02-21 Texas Instruments Incorporated Method of making electrical connections to materials with high-dielectric-constant
US5566045A (en) * 1994-08-01 1996-10-15 Texas Instruments, Inc. High-dielectric-constant material electrodes comprising thin platinum layers
DE19608182A1 (en) * 1995-03-04 1996-09-19 Lg Semicon Co Ltd Dielectric thin film for use in semiconductor memory device capacitor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19842684C1 (en) * 1998-09-17 1999-11-04 Siemens Ag Integrated circuit high-permittivity capacitor arranged on support structure in semiconductor arrangement e.g. for DRAM circuit or ADC

Also Published As

Publication number Publication date
DE19640244A1 (en) 1998-04-02

Similar Documents

Publication Publication Date Title
DE19630310C2 (en) Semiconductor device with a capacitor and method of manufacturing the same
EP0931355B1 (en) Semiconductor device with a protected barrier for a stack cell
DE19838741A1 (en) A metal-insulator-metal capacitor for a dynamic random access memory (DRAM) device
DE19928280A1 (en) Ferroelectric memory device, especially a ferroelectric RAM for modern data processing systems, is produced by forming a capacitor with a multilayer ferroelectric layer of titanate content exceeding its zirconate content
DE19926711A1 (en) Ferroelectric DRAM device and manufacture
DE10227346A1 (en) Ferroelectric memory device, e.g. ferroelectric random-access memories comprises bottom electrode patterns formed on semiconductor substrate, and first and second ferroelectric layers
DE10014315A1 (en) Semiconductor memory, especially with a ferroelectric capacitor, has a barrier metal covered at its side by an oxygen penetration preventing film and at its top by a lower capacitor electrode
DE10242033A1 (en) Ferroelectric random access memory device, has capacitor upper electrode formed around sidewalls of ferroelectric layer which is stacked to cover capacitor lower electrode
DE19712540C1 (en) Manufacturing method for a capacitor electrode made of a platinum metal
EP0931341B1 (en) Process for producing barrier-free semiconductor storage assemblies
DE19620185C2 (en) Method of manufacturing a capacitor of a semiconductor device
EP1202333B1 (en) Storage capacitor, contact structure and method of manufacturing
DE19950540B4 (en) Process for the preparation of a capacitor electrode with barrier structure
WO1998015014A1 (en) Capacitor with an electrode core and a thin noble metal layer used as a first electrode
EP1277230B1 (en) Method for producing capacitor structures
EP0931342A1 (en) Process for producing barrier-free semiconductor storage assemblies
DE10248704A1 (en) Formation of high dielectric constant stacked capacitor by etching exposed surface of polyplug to form recess, depositing in situ carrier layer and first metal or metal oxide layer, and depositing high dielectric constant material
EP0987756A2 (en) Stacked DRAM fin capacitor and method of making the same
DE19743268C2 (en) Capacitor with a barrier layer made of a transition metal phosphide, arsenide or sulfide, production method for such a capacitor and semiconductor memory arrangement with such a capacitor
DE19640448C1 (en) Stacked cell capacitor-containing integrated circuit production
DE19620833A1 (en) Production of capacitor for semiconductor device
EP0984490A1 (en) Process for the manufacture of structured material layers
DE19919110C2 (en) Process for structuring a metal or metal silicide layer and a capacitor produced with this process
EP0986095A2 (en) Layered structure with a material layer and a diffusion barrier layer disposed at the grain boundary of the material layer and process for fabricating the same
DE10112276C2 (en) Method for producing an integrated ferroelectric semiconductor memory and integrated ferroelectric semiconductor memory

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): CN JP KR US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase

Ref country code: JP

Ref document number: 1998516123

Format of ref document f/p: F

122 Ep: pct application non-entry in european phase