WO1998018074A1

WO1998018074A1 - System for providing custom operations of a processor for multimedia functions

Info

Publication number: WO1998018074A1
Application number: PCT/US1996/016690
Authority: WO
Inventors: Gerrit A. Slavenburg; Pieter S. Van Der Muelen; Yong H. Cho; Vijay K. Mehra; Yen C. Lee
Original assignee: Philips Electronics North America Corporation
Priority date: 1996-10-22
Filing date: 1996-10-22
Publication date: 1998-04-30
Also published as: AU7453396A

Abstract

Custom operations are useable in processor systems for performing functions including multimedia functions. These custom operations enhance a system, such as PC system, to provide real-time multimedia capabilities while maintaining advantages of a special-purpose, embedded solution, i.e., low cost and chip count, and advantages of a general-purpose processor reprogrammability. These custom operations work in a computer system which supplies input data having operand data, performs operations on the operand data, and supplies result data to a destination register. Operations performed may include audio and video processing including clipping or saturation operations. The present invention also performs parallel operations on select operand data from input registers and stores results in the destination register.

Description

SYSTEM FOR PROVIDING CUSTOM OPERATIONS OF A PROCESSOR FOR MULTIMEDIA FUNCTIONS

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application 60/003,140 filed September 1, 1995, and U.S. Provisional Application No. 60/004,642 filed September 25, 1995. The following applications are incorporated by reference herein for discussion of VLI processing systems:

US Patent No. 5,103,311: DATA PROCESSING MODULE AND VIDEO PROCESSING SYSTEM INCORPORATING SAME;

US Patent No. 5,450,556: VLIW PROCESSOR WHICH USES PATH INFORMATION GENERATED BY A BRANCH CONTROL UNIT TO INHIBIT OPERATIONS WHICH ARE NOT ON A CORRECT PATH;

US Patent No. 5,313,551: MULTIPORT MEMORY BYPASS UNDER SOFTWARE CONTROL;

US Application Serial No. 07/998,080 filed December 29, 1992 entitled VLIW PROCESSOR WITH LESS INSTRUCTION ISSUE SLOTS THAN FUNCTIONAL UNITS;

US Serial No. 07/594,534 filed October 5, 1990 entitled PROCESSING DEVICE INCLUDING A MEMORY CIRCUIT AND A GROUP OF FUNCTIONAL UNITS;

US Serial No. 08/358,127 filed December 16, 1994 entitled EXCEPTION RECOVERY IN A DATA PROCESSING SYSTEM; and

Concurrently filed applications entitled METHOD AND APPARATUS FOR CUSTOM OPERATIONS FOR MULTIMEDIA APPLICATIONS USING CLIPPING FUNCTIONS and METHOD AND APPARATUS FOR CUSTOM OPERATIONS USING MULTIPLE OPERANDS FOR PARALLEL PROCESSING UNDER CONTROL OF A SINGLE INSTRUCTION.

An updated version of the data book filed as provisional applications from which the present application claims priority is attached as Appendix A and incorporated herein.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention is custom operations for use in processor systems which perform functions including multimedia functions, such as, for example, a system with an ability to handle high-quality video and audio and for performing specialized, high-function operations. 2. Description of the Related Art

A system may include a general-purpose CPU and additional units to serve as a multi-function PC enhancement vehicle.

Typically, a PC must deal with multi-standard video and audio streams, and users desire both decompression and compression, if possible. While the CPU chips used in PCS are becoming capable of low-resolution real-time video decompression, high-quality video decompression and compression are still not possible.

Further, users demand that their systems provide live video and audio without sacrificing responsiveness of the system.

For both general-purpose and embedded microprocessor-based applications, programming in a high-level language is desirable. To effectively support optimizing compilers and a simple programming model, certain microprocessor architecture features are needed, such as a large, linear address space, general- purpose registers, and register-to-register operations that directly support manipulation of linear address pointers. A recently common choice in microprocessor architectures is 32-bit linear addresses, 32-bit registers, and 32-bit integer operations although 64 and 128 bit systems are currently in development.

For data manipulation in many algorithms, however, data operations using the entire number of bits (i.e., 32 bits for a 32-bit system) are wasteful of expensive silicon resources. Important multimedia applications, such as decompression of MPEG video streams, spend significant amounts of execution time dealing with eight-bit data items. Using 32-, 64-, 128-,..., bit operations to manipulate small data items makes inefficient use of 32-, 64-, 128-,..., bit execution hardware in the implementation. Therefore, custom operations may operate on data items simultaneously and improve performance by a significant factor with only a tiny increase in implementation cost. Although a similar performance increase through other means may be achieved, -e.g., executing a higher number of traditional microprocessor instructions per cycle - these other means are generally prohibitively expensive for low-cost target applications. Additionally, use of m-bit operations, for example 32-bit operations, to manipulate small data items of n- bits where n<m is an inefficient use of m-bit execution hardware in the implementation.

Logic of conventional dsp or DSP (digital signal processing) operations calculates modulo values. Clipping or saturation operations of the present invention are especially valuable in signal processing applications where the processing generates data that may run beyond physical limits of the registers. Conventionally, when this occurs, data are mapped to the other end of the physically available range. In processing of signals, this cyclical mapping can be disastrous. For example, a very low audio volume would be mapped onto the highest using the conventional scheme. In control applications and in video/audio applications modulo values are not desirable when the control range or intensity range saturates.

SUMMARY OF THE PRESENT INVENTION The present invention enhances a system, such as a PC system, to provide real-time multimedia capabilities while maintaining advantages of a special-purpose, embedded solution, i.e. low cost and chip count, and advantages of a general- purpose processor-reprogramability. For PC applications, the present invention surpasses the capabilities of fixed-function multimedia chips.

Accordingly, one object of the present invention is to achieve extremely high multimedia performance at a low price. A further object of the present invention is to increase processing speed in small kernels of applications.

A still further object of the present invention is to achieve full advantage of cache/memory bandwidth while not requiring an inordinate number of byte-manipulation instructions.

Another object of the present invention is to provide specialized, high-function operations to improve performance in multimedia applications. A further object of the present invention is to provide custom operations which efficiently use specified bit execution hardware in implementation of operations.

A still further object of the present invention is to provide custom operations which may be, for example, tailored to specific applications such as multimedia applications.

Another object of the present invention is to use multiple operand registers storing multiple operands for parallel processing under control of a single instruction. This is particularly advantageous in audio and/or video applications where samples are currently 8 or 16 bits.

An object of the present invention is to use a clipping operation to keep received signals, such as audio or video signals, in the correct side of a truncated range.

The present invention can be used in low-cost, single- purpose systems such as video phones to reprogrammable, multipurpose plug-in cards for traditional personal computers. Additionally, the present invention may be used in a system which easily implements popular multimedia standards such as MPEG-1 and MPEG-2. Moreover, orientation of the present invention around a powerful general-purpose CPU makes it capable of implementing a variety of multimedia algorithms, whether open or proprietary. Defining software compatibility at a source-code level has an advantage of providing freedom to strike an optimum balance between cost and performance. Powerful compilers ensure that programmers never need to resort to non-portable assembler programming. The present invention allows programmers to use powerful low level operations from source code with dsp-like operations being invoked with a familiar function-call syntax.

A computer system includes input registers, each for receiving input data, each input data comprising M bits and operand data comprising N bits, where N is less than or equal to M; a processor for performing a set of operations on selected operand data, each set of operations comprising at least one operation and producing result data of N bits; and a destination register for storing the result data from each set of operations. The set of operations may include a clipping or saturation operation. Additionally, the set of operations may be performed in parallel and in response to an instruction of an instruction set.

Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the invention is shown and described, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

BRIEF DESCRIPTION OF THE DRAWINGS

These objects as well as other objects of the present invention will be apparent from the description of the present invention including the aid of the following drawings:

Figure 1 is a block diagram of an example system for use with the present invention;

Figure 2 illustrates an example of CPU register architecture;

Figure 3(a) illustrates an example of an organization of a matrix in memory; Figure 3 (b) illustrates a task to be performed in the example;

Figure 4 illustrates an application for a byte-matrix transposition using custom operations;

Figure 5(a) and 5(b) illustrate a list of operations to perform the byte-matrix transposition shown in Figure 4; Figure 6 illustrates a dspiadd operation; Figure 7 illustrates a dspuadd operation; Figure 8 illustrates a dspidualadd operation; Figure 9 illustrates a dspuquadaddui operation; Figure 10 illustrates a dspimul operation; Figure 11 illustrate a dspumul operation; Figure 12 illustrates a dspidualmul operation; Figure 13 illustrates a dspisub operation; Figure 14 illustrates a dspusub operation; Figure 15 illustrates a dspidualsub operation; Figure 16 illustrates an ifirlδ operation; Figure 17 illustrates an ifirδii operation; Figure 18 illustrates an ifirδui operation; Figure 19 illustrates an ufirlδ operation;

Figure 20 illustrates an ufirδuu operation;

Figure 21 illustrates a mergelsb operation;

Figure 22 illustrates a mergemsb operation; Figure 23 illustrates a packlδlsb operation;

Figure 24 illustrates a packl6msb operation;

Figure 25 illustrates a packbytes operation;

Figure 26 illustrates a quadavg operation;

Figure 27 illustrates a quadumulmsb operation; Figure 28 illustrates an umeδii operation;

Figure 29 illustrates an umeδuu operation;

Figure 30 illustrates an iclipi operation;

Figure 31 illustrates an uclipi operation; and

Figure 32 illustrates an uclipu operation. DESCRIPTION OF PREFERRED EMBODIMENTS

Figure 1 shows a block diagram of an example system for use with the present invention. This system includes a microprocessor, a block of synchronous dynamic RAM (SDRAM) , and external circuitry needed to interface to incoming and/or outgoing multimedia data streams.

In this example, a 32-bit CPU forms a VLIW processor core. The CPU implements a 32-bit linear address space and 128 fully general-purpose 32-bit registers. In the present system, the registers are not separated into banks. Instead, any operation can use any register for any operand.

In this system, the CPU uses a VLIW instruction-set architecture allowing up to five simultaneous operations to be issued. These operations can target, in this example, any five of 27 functional units in the CPU, including integer and floating-point arithmetic units and data-parallel dsp-like units.

The operation set of a CPU utilizing the present invention may include traditional microprocessor operations in addition to multimedia-specific operations that dramatically accelerate standard video compression and decompression algorithms. A single special or "custom" operation, one of several operations issued in a single instruction, in this example five operations, can implement up to 11 traditional microprocessor operations. Multimedia-specific operations combined with VLIW, RISC, or other architecture result in tremendous throughput for multimedia applications. The present invention allows use of one register of 32, 64, 128,..., bits for data to perform these "multimedia" operations. Figure 2 illustrates one example of a CPU register architecture. The CPU of the present embodiment has 128 fully general-purpose 32-bit registers, labeled r0..rl27. In this embodiment, registers rO and rl are used for special purposes and registers r2 through rl27 are true general purpose registers.

In the present system, the processor issues one long instruction every clock cycle. Each such instruction includes several operations (5 operations for the present embodiment) . Each operation is comparable to a RISC machine instruction, except that execution of an operation is conditional upon the content of a general purpose register.

Data in the register may be in, for example, integer representation or floating point representation.

Integers may be considered, in the present embodiment, as 'unsigned integers' or 'signed integers', as binary and two's complement bit patterns, respectively. Arithmetic on integers does not generate traps. If a result is not representable, the bit pattern returned is operation specific, as defined in the individual operation description section. The typical cases are: wrap around for regular add and subtract type operations, clamping against the minimum or maximum representable value for dsp-type operations or returning the least significant 32-bit value of a 64-bit result (e.g., integer/unsigned multiply). Since the present embodiment is 32-bit architecture, it does not use floating point representation for values of data used in the multimedia operations. However, clearly for a 64 - bit, 128-bit, ... , architecture, floating point representation could be used for values of data used in the multimedia operations. For example, single precision (32-bit) IEEE-754 floating point arithmetic and/or double precision (64-bit) IEEE- 754 floating point could be used to represent data values.

In the architecture of the present invention, all operations are optionally 'guarded'. A guarded operation executes conditionally, depending on the value in a 'guard' register (rguard) . For example, a guarded integer add (iadd) is written as:

IF r23 iadd rl4 rlO → rl3

In this example, "if r23 then rl3:= rl4 + rlO". The 'if r23' clause evaluates TRUE or FALSE depending on the LSB of the value in r23. Hence, depending on the LSB of r23, rl3 is either unchanged or set to contain an integer sum of rl4 and rlO. For example, in this embodiment of the present invention, if the LSB is evaluated as 1, a destination register (rdest) , in this example rl3, is written. Guarding controls effects on programmer visible states of the system, i.e. register values, memory content and device state.

Memory in the present invention is byte addressable. Loads and stores are 'naturally aligned', i.e. a 16-bit load or store targets an address that is a multiple of 2. A 32-bit load or store targets an address that is a multiple of 4. One skilled in the art could easily modify this.

Compute operations are register-to-register operations. A specified operation is performed on one or two source registers and a result is written to a destination register (rdest) .

Custom operations are special compute operations and are like normal compute operations; however, these custom operations are not found in general purpose CPUs. The custom operations advantageously allow performance of operations for, for example, multimedia applications. The custom operations of the present invention are specialized, high-function operations designed to dramatically improve performance in important multimedia applications as well as in other applications. When properly incorporated into application source code, custom operations enable an application to take advantage of a highly parallel microprocessor implementation such as a Trimedia TM-1 chip manufactured by Philips Electronics, of the present invention.

For both general-purpose and embedded microprocessor-based applications, programming in a high-level language may be desirable. To effectively support optimizing compilers and a simple programming model, certain microprocessor architecture features are needed, such as a large, linear address space, general-purpose registers, and register-to-register operations that directly support manipulation of linear address pointers. The present invention allows use of the system's entire resources, such as, for example, 32-bit resources, to operate on two sixteen-bit data items or four eight-bit data items simultaneously. This use improves performance by a significant factor with only a tiny increase in implementation cost.

Additionally, this use achieves a high execution rate from standard microprocessor resources.

Some high-function custom operations eliminate conditional branches, which helps a scheduler effectively use five operation slots in each instruction of the present system, for example, the Philips TM-1 chip with TM-1 instructions. Filling up all five slots is especially important in inner loops of computationally intensive multimedia applications. Custom operations help the present invention achieve extremely high multimedia performance at the lowest possible cost.

Table 1 is a listing of custom operations of the present invention. Some custom operations exist in several versions that differ in treatment of respective operands and results. Mnemonics for these different versions attempt to clarify the respective treatment to aid in selection of the appropriate operation, although clearly, different mnemonics or names could be assigned.

Table 1. Custom operations listed by function type

Function Custom Pop Description

DSP dspiabs Clipped signed 32-bit absolute value absolute value dspidualabs Dual clipped absolute values of signed 16-bit halfwords dspiadd Clipped signed 32-bit add

DSP add dspuadd Clipped unsigned 32-bit add dspidualadd Dual clipped add of signed 16-bit halfwords dspuquadaddui Quad clipped add of unsigned/signed bytes dspimul Clipped signed 32-bit multiply

DSP multiply dspumul Clipped unsigned 32-bit multiply dspidualmul Dual clipped multiply of signed 16-bit halfwords dspisub Clipped signed 32-bit subtract

DSP subtract dspusub Clipped unsigned 32-bit subtract dspidualsub Dual clipped subtract of signed 16-bit halfwords ifirlό Signed sum of products of signed 16-bit halfwords ifιr8ii Signed sum of products of signed bytes

Sum of products ifirδui Signed sum of products of unsigned/signed bytes ufirlό Unsigned sum of products of unsigned 16-bit halfwords ufirδuu Unsigned sum of products of unsigned bytes mergelsb Merge least-significant bytes

Merge mergemsb Merge most-significant bytes

Pack packlδlsb Pack least-significant 16-bit halfwords packlόmsb Pack most-significant 16-bit halfwords packbytes Pack least-significant bytes

Byte quadavg Unsigned byte-wise quad average averages

Byte quadumulmsb Unsigned quad 8-bit multiply most significant multiplies ume8ii Unsigned sum of absolute values of signed 8-bit differences

Motion estimation umeδuu Unsigned sum of absolute values of unsigned 8-bit differences iclipi Clip signed to signed

Clipping uclipi Clip signed to unsigned uclipu Clip unsigned to unsigned An example is presented to illustrate use of a custom operation of the present invention. This example, a byte-matrix transposition, provides a simple illustration of how custom operations can significantly increase processing speed in small kernels of applications. As in most uses of custom operations, the power of custom operations in this case comes from their ability to operate on multiple data items in parallel.

For example, a task to transpose a packed, four-by-four matrix of bytes in memory. The matrix might, for example, contain eight-bit pixel values. Figure 3(a) illustrates both organization of the matrix in memory and, Figure 3(b) illustrates in standard mathematical notation, the task to be performed.

Performing this operation with traditional microprocessor instructions is straight forward but time consuming. One method to perform the manipulation is to perform 12 load-byte instructions to load bytes (since only 12 of the 16 bytes need to be repositioned) and 12 store-byte instructions to store the bytes back in memory in their new positions. Another method would be to perform four load-word instructions, reposition bytes of the loaded words in registers, and then perform four store-word instructions. Unfortunately, repositioning the bytes in registers requires a large number of instructions to properly shift and mask the bytes. Performing twenty four loads and stores makes implicit use of shifting and masking hardware in load/store units and thus yields a shorter instruction sequence.

The problem with performing twenty four loads and stores is that loads and stores are inherently slow operations: they must access at least cache and possibly slower layers in a memory hierarchy. Further, performing byte loads and stores when 32-bit word-wide accesses run as fast wastes the power of the cache/memory interface. A fast algorithm that takes full advantage of cache/memory bandwidth while not requiring an inordinate number of byte-manipulation instructions is desired. The present invention has instructions that merge

(merge sb and mergelsb) and pack bytes and 16-bit halfwords (packlδmsb and packlδlsb) directly and in parallel. Four of these instructions can be applied for the present example to speed up manipulation of bytes packed into words.

Figure 4 illustrates application of these instructions to the byte-matrix transposition example. Figure 5(a) shows a list of the operations needed to implement a matrix transpose. When assembled into actual instructions, these custom operations would be packed as tightly as dependencies allow, for example, up to five operations per instruction. Low-level code in Figure 5(a) is shown here for illustration purposes only.

A first sequence of four load-word operations (ld32d) in Figure 5(a) brings the packed words of the input matrix into registers rlO, rll, rl2, and rl3. A next sequence of four merge operations (mergemsb and mergelsb) produces intermediate results in registers rl4, rl5, rl6, and rl7. A next sequence of four pack operations (packl6msb and packlδlsb) may then replace the original operands or place the transposed matrix in separate registers if the original matrix operands were needed for further computations (a TM-1 optimizing C compiler could perform such an analysis automatically) . In this example, the transpose matrix is placed in separate registers (st32d) , registers rl8, rl9, r20, and r21. Four final four store-word operations put the transposed matrix back into memory.

Thus, using the custom operations of the present invention, the byte-matrix transposition requires four-word operations and four store-word operations (the minimum possible) and eight register-to-register data manipulation operations.

The result is 16 operations, or byte-matrix transposition at a rate of one operation per byte. Figure 5(b) illustrates an equivalent C-language fragment.

While the advantage of the custom-operation-based algorithm over brute-force code that uses 24 load-and store-byte instruction seems to be only eight operations (a 33% reduction) for the present example, the advantage is actually much greater. First, using custom operations, the number of memory references is reduced from twenty four to eight i.e., a reduction by a factor of three. Since memory references are slower than register-to-register operations (such as performed using the custom operations in this example) , the reduction in memory references is significant.

Further, the ability of the compiling system of the present system (TM-1 system) to exploit performance potential of the TM-1 microprocessor hardware is enhanced by the custom- operation-based code. Specifically, the compiling system more easily produces an optimal schedule (arrangement) of the code when the number of memory references is in balance with the number of register-to-register operations. Generally high- performance microprocessors have a limit on the number of memory references that can be processed in a single cycle. As a result, a long sequence of code that contains only memory references can cause empty operation slots in the long TM-1 instructions and thus, waste performance potential of the hardware .

As this example has shown, use of the custom operations of the present invention may reduce the absolute number of operations needed to perform a computation and can also help a compiling system produce code that fully exploits the performance potential of the respective CPU. Other applications such as MPEG image reconstruction for, for example, a complete MPEG video decoding algorithm and motion-estimation kernels could be benefited by use of the custom operations of the present invention, although this is not exhaustive.

The present invention includes those custom operations listed in Table 1. The specifics of each of these custom operations are set forth below. In the function code given below, standard symbols, syntax, etc. are used. For example, tempi and temp2 represent temporary registers. Further, as an example, a function tempi <- sign_extl6to32 (rsrcl<l5: >) means that tempi is loaded with the 15:0 bits (bits 0 to 15) of the rsrcl register with the sign bit (in this example, the 15th bit) being extended to the 16 to 32 bits (sign bit extension) .

Similarly, temp2 <- sign_extl6to32 (rsrcl<16: 31>) indicates that the 16th to 31st bits of rsrcl are extracted (and for calculation purposes, 'placed' in the 0 to 15th bits) and the sign bit which, in this example, is the 31st bit, is sign extended to the 16th to 32nd bits. This sign extension is used for signed values, in this example, signed integers. For unsigned values, zero fill is used. The notation for zero fill is very similar to that of sign extend. For example, zero_ext8to32 (rsrcl<15 : 0>) indicates that the value of the 15 to 0 bits are to be operated on and the 8th to 32nd bits are filled with zeros. rsrcl, rsrc2 and rdest may be any of the available registers as discussed above.

For each of the below listed operations, the operation optionally takes a guard, specified in rguard. If a guard is present, in this example its LSB controls modification of the destination register. In this example, if the LSB of rguard is 1, in this example, rdest is written; otherwise, rdest is not changed. dspiabs; dspiabs is a clipped signed absolute value operation, pseudo-op for h_dspiabs (hardware dspiabs) . This operation has the following function: if rguard then { if rsrcl> = 0 then rdest <- rsrcl else if rsrcl = 0x800000000 then rdest *- 0x7fffffff else rdest <- rsrcl }

The dspiabs operation is a pseudo operation transformed by the scheduler into an h_dspiabs with a constant first argument zero and second argument equal to the dspiabs argument. Pseudo operations generally are not used in assembly source files. h_dspiabs performs the same function; however, this operation requires a zero as first argument.

The dspiabs operation computes the absolute value of rsrcl, clips the result into a range [2³¹-1...0] or [0x7fffffff ...0] , and stores the clipped value into rdest (a destination register) . All values are signed integers. dspidualabs: dspidualabs is a dual clipped absolute value of signed 16-bit halfwords operation, pseudo-op for h_dspidualabs (hardware dspidualabs) . This operation has the following function: if rguard then { tempi <- sign_extl6to32 (rsrcl<15:0>) temp2 *- sign_extl6to32 (rsrcl<31:16>) if tempi = 0xffff8000 then tempi <- 0x7fff if temp2 = 0xffff8000 then temp2 *- 0x7fff if tempi < 0 then tempi +- -tempi if temp2 < 0 then temp2 *- -temp2 rdest<3l:l6> <- temp2<15:0> rdest<15:0> <- templ<15:0> } The dspidualabs operation is a pseudo operation transformed by the scheduler into an h_dspidualabs with, in this example, a constant zero as a first argument and the dspidualabs argument as a second argument. The dspidualabs operation performs two 16-bit clipped, signed absolute value computations separately on the high and low 16-bit halfwords of rsrcl. Both absolute values are clipped into a range [0x0..0x7fff] and written into corresponding halfwords of rdest. All values are signed 16-bit integers. h_dspidualabs performs the same function; however, this operation requires a zero as first argument. dspiadd; dspiadd is a clipped signed add operation. This operation has the following function: if rguard then { temp <- sign_ext32to64 (rscl) + sgn_ext32to64 (rsrc2) if temp < 0xffffffff80000000 then rdest <- 0x80000000 else if temp > 0x00000007fffffff then rdest <- 0x7fffffff else rdest <- temp }

As shown in Figure 6 , the dspiadd operation computes a signed sum rsrcl+rsrc2, clips the result into a 32-bit signed range [2³¹ - 1...-2³¹] or [0x7fffffff...0x80000000] , and stores the clipped value into rdest. All values are signed integers. dspuadd; dspuadd is a clipped unsigned add operation. This operation has the following function: if rguard then { temp <- zero_ext32to64 (rsrcl) +zero_ext32to64 (rsrc2) if (unsigned) temp > OxOOOOOOOOffffffff then rdest <- Oxffffffff else rdest <- tempo1:0> }

As shown in Figure 7 the dspuadd operation computes an unsigned sum rsrcl+rsrc2, clips the result into an unsigned range [2³²-1...0] or [Oxffffffff...0] , and stores the clipped value into rdest. dspidualadd; dspidualadd is a dual clipped add of signed 16-bit halfwords operation. This operation has the following function: if rguard then { tempi <- sign_extl6to32 (rsrcl<15 : 0>) + sign_extl6to32 (rsrc2<15 : 0>) temp2 <- sign_extl6to32 (rsrclOl: 16>) + sign_extl6to32 (rsrc2<31: 16>) if tempi < 0xffff8000 then tempi <- 0x8000 if temp2 = 0xffff8000 then temp2 *- 0x8000 if tempi > 0x7fff then tempi <- 0x7fff if temp2 < 0x7fff then temp2 <- 0x7fff rdest<31:16> <- temp2<15:0> rdest<15:0> <- templ<15:0>

}

As shown in Figure 8, the dspidualadd operation computes two 16-bit clipped, signed sums separately on two respective pairs of high and low 16-bit halfwords of rsrcl and rsrc2. Both sums are clipped into a range [2¹⁵-1...2¹⁵] or [0x7fff...0x8000] and written into corresponding halfwords of rdest. All values are signed 16-bit integers. dspuquadaddui : dspuquadaddui is a quad clipped add of unsigned/signed bytes operation. This operation has the following function: if rguard then { for (i<-0,m<-31,n<-24;i<4;i*-i+l,m<-m-8,n*-n-8) { temp <- zero_ext8to32 (rsrcl<m:n>) +sign_ext8to32 (rsrc2<m:n>) if temp < 0 then rdest<m:n> <- 0 else if temp > Oxff then rdest<m:n> <-0xff else rdest<m:n> <- temp<7:0>

}

As shown in Figure 9, the dspuquadaddui operation computes four separate sums of four respective pairs of corresponding 8-bit bytes of rsrcl and rsrc2. Bytes in rsrcl are considered unsigned values; bytes in rsrc2 are considered signed values. The four sums are clipped into an unsigned range [255...0] or [0xff...0]; thus, resulting byte sums are unsigned. All computations are performed without loss of precision. dspimul ; dspimul is a clipped signed multiply operation. This operation has the following function: if rguard then { temp <- sign_ext32to64 (rsrcl) +sign_ext32to64 (rsrc2) if temp < 0xffffffff80000000 then rdest <- 0x80000000 else if temp > 0x000000007fffffff then rdest «- 0x7fffffff else rdest <- tempol:0>

}

As shown in Figure 10, the dspimul operation computes a product rsrcl x rsrc2 , clips the results into a range [2³¹ -

1...-2³¹] or [0x7fffffff...0x80000000] , and stores the clipped value into rdest. All values are signed integers. dspumul : dspumul is a clipped unsigned multiply operation.

This operation has the following function: if rguard then { temp *- zero_ext32to64 (rsrcl) x zero_ext32to64 (rsrc2) if (unsigned) temp > OxOOOOOOOOffffffff then rdest <- Oxffffffff else rdest <- tempo1:0> }

As shown in Figure 11, the dspumul operation computes an unsigned product rsrcl x rsrc2 , clips the result into an unsigned range [2³²-1...0] or [Oxffffffff...0] , and stores the clipped value into rdest. dspidualmul: dspidual ul is a dual clipped multiply of signed

16-bit halfwords operation. This operation has the following: function: if rguard then { tempi <- sign_extl6to32 (rsrcl<15: 0>) x sign_extl6to32 (rsrc2<15: 0>) temp2 <- sign_extl6to32 (rsrclOl: 16>) x sign_extl6to32 (rsrc201: 16>) if tempi < OxffffδOOO then tempi <- 0x3000 if temp2 = OxffffδOOO then temp2 <- 0x8000 if tempi > 0x7fff then tempi <- 0x7fff if temp2 < 0x7fff then temp2 <- 0x7fff rdest<31:16> <- temp2<15:0> rdest<15:0> <- templ<15:0>

}

As shown in Figure 12 , the dspidualmul operation computes two 16-bit clipped, signed products separately on two respective pairs of high and low 16-bit halfwords of rsrcl and rsrc2. Both products are clipped into a range [2¹⁵ -1... -2¹⁵] or [0x7fff ...0x8000] and written into corresponding halfwords of rdest. All values are signed 16-bit integers. dspisub; dspisub is a clipped signed subtract operation. This operation has the following function: if rguard then { temp <- sign_ext32to64 (rsrcl) - sign_ext32to64 (rsrc2) if temp < 0xffffffff80000000 then rdest <- 0x80000000 else if temp > 0x000000007fffffff then rdest <- 0x7fffffff else rdest <- temp<31:0> }

As shown in Figure 13, the dspisub operation computes a difference rsrcl-rsrc2, clips the result into a range (0x80000000..0x7fffffff] , and stores the clipped value into rdest. All values are signed integers.

dspusub; dspusub is a clipped unsigned subtract operation. This operation has the following function: if rguard then { temp <- zero_ext32to64 (rsrcl) - zero_ext32to64 (rsrc2) if (signed) temp < 0 then rdest <- 0 else rdest <- tempo1:0> } As shown in Figure 14 , the dspusub operation computes an unsigned difference rsrcl-rsrc2 , clips the result into an unsigned range [0. Oxffffffff ] , and stores the clipped value into rdest. dspidualsub: dspidualsub is a dual clipped subtract of signed 16-bit halfwords operation. This operation has the following function: if rguard then { tempi <- sign_extl6to32 (rsrcl<15:0>) - sign_extl6to32 (rsrc2<15: 0>) temp2 <- sign_extl6to32 (rsrclOl: 16>) - sign_extl6to32 (rsrc2<31: 16>) if tempi < 0xffff8000 then tempi «- 0x8000 if temp2 < 0xffff8000 then temp2 <- 0x8000 if tempi > 0x7fff then tempi <- 0x7fff if temp2 > 0x7fff then temp2 <- 0x7fff rdest<31:16> <- temp2<15:0> rdest<15:0> <- templ<15:0> }

As shown in Figure 15, the dspidualsub operation computes two 16-bit clipped, signed differences separately on two respective pairs of high and low 16-bit halfwords of rsrcl and rsrc2. Both differences are clipped into a range [2¹⁵-1,,,-

2¹⁵ or [0x7fff...0x8000] and written into corresponding halfwords of rdest. All values are signed 16-bit integers. ifirlβ: ifirlδ is a sum of products of signed 16-bit halfwords operation. This operation has the following function: if rguard then rdest <- sign_extl6to32 (rsrclOl: 16>) x sign_extl6to32 (rsrc2<31: 16>) + sign_extl6to32 (rsrcl<15 : 0>) x sign_extl6to32 (rsrc2<15:0>)

As shown in Figure 16, the ifirl6 operation computes two separate products of two respective pairs of corresponding 16-bit halfwords of rsrcl and rsrc2 ; the two products are summed, and the result is written to rdest. All halfwords are considered signed; thus, the products and the final sum of products are signed. All computations are performed without loss of precision. ifir8ii; ifirδii is a signed sum of products of signed bytes operation. This operation has the following function: if rguard then rdest <- sign_ext8to32 (rsrclOl: 24>) x sign_ext8to32 (rsrc201: 24>) + sign_ext8to32 (rsrcl<23 : 16>) x sign_ext8to32 (rsrc2<23: 16>)+ sign_ext8to32 (rsrcl<15 : 8>) x sign_ext8to32 (rsrc2<15 : 8>) + sign_ext8to32 (rsrcl<7 : 0>) x sign_ext8to32 (rsrc2<7 : 0>) As shown in Figure 17, the ifirδii operation computes four separate products of four respective pairs of corresponding 8-bit bytes of rsrcl and rsrc2 ; the four products are summed, and the result is written to rdest. All values are considered signed; thus, the products and the final sum of products are signed. All computations are performed without loss of precision. ifir8ui; ifirδui is a signed sum of products of unsigned/signed bytes operation. This operation has the following function: if rguard then rdest <- zero_ext8to32 (rsrclOl: 24>) x sign_ext8to32 (rsrc2<31: 24>) + zero_ext8to32 (rsrcl<23 : 16>) x sign_ext8to32 (rsrc2<23 : 16>) + zero_ext8to32 (rsrcl<15 : 8>) x sign_ext8to32 (rsrc2<15:8>)+ zero_ext8to32 (rsrcl<7 : 0>) x sign_ext8to32 (rsrc2<7 : 0>)

As shown in Figure 18, the ifirδui operation computes four separate products of four respective pairs of corresponding

8-bit bytes of rsrcl and rsrc2 ; the four products are summed, and the result is written to rdest. Bytes from rsrcl are considered unsigned, but bytes from rsrc2 are considered signed; thus, the products and the final sum of products are signed.

All computations are performed without loss of precision. ufirlβ; ufirl6 is a sum of products of unsigned 16-bit halfwords operation. This operation has the following function: if rguard then { rdest *- (zero_extl6to32 (rsrclOl: 16>)x zero_extl6to32 (rsrc2<31: 16>) + zero_extl6to32 (rsrcKIS : 0>) x zero_extl6to32 (rsrc2<15:0>)

As shown in Figure 19, the ufirl6 operation computes two separate products of two respective pairs of corresponding 16-bit halfwords of rsrcl and rsrc2 , the two products are summed, and the result is written to rdest. All halfwords are considered unsigned; thus, the products and the final sum of products are unsigned. All computations are performed without loss of precision. The final sum of products is clipped into the range [Oxffffffff...0] before being written into rdest. ufirsuu; ufirδuu is a unsigned sum of products of unsigned bytes operation. This operation has the following function: if rguard then { rdest «- zero_extδto32 (rsrclOl: 24>)x zero_ext8to32 (rsrc201: 24>) + zero_ext8to32 (rsrcl<23 : 16>) x zero_ext8to32 (rsrc2<23 : 16>) + zer0_ext8to32 (rsrcl<15 : 8>) x zero_ext8to32 (rsrc2<15 : 8>) + zero_ext8to32 (rsrcl<7 : 0) x zero_ext8to32 (rsrc2<7 : 0>) As shown in Figure 20, the ufirδuu operation computes two separate products of four respective pairs of corresponding 8-bit bytes of rsrcl and rsrc2 , the four products are summed, and the result is written to rdest. All bytes are considered unsigned. All bytes are considered unsigned. All computations are performed without loss of precision. mergelsb; mergelsb is a merge least-significant byte operation. This operation has the following function: if rguard then { rdest<7:0> <- rsrc2<7:0> rdest<15:8> *- rsrcl<7:0> rdest<23:16> <- rsrc2<15:8> rdest<31:24> <- rsrcl<15:8>

As shown in Figure 21, the mergelsb operation interleaves two respective pairs of least-significant bytes from arguments rsrcl and rsrc2 into rdest. The least-significant byte from rsrc2 is packed into the least-significant byte of rdest; the least significant byte from rsrcl is packed into the second-least-significant byte or rdest; the second-least- significant byte from rsrc2 is packed into the second-most- significant byte of rdest; and the second-least-significant byte from rsrcl is packed into the most-significant byte of rdest. mergemsb; mergemsb is a merge most-significant byte operation.

This operation has the following function: if rguard then { rdest<7:0> <- rsrc2<23:15> rdest<15:8> <- rsrcl<23:15> rdest<23:16> <- rsrc2<31:24> rdest<31:24> <- rsrcl<31:24>

As shown in Figure 22, the mergemsb operation interleaves the two respective pairs of most-significant bytes from arguments rsrcl and rsrc2 into rdest. The second-most- significant byte from rsrc2 is packed into the least-significant byte of rdest; the second-most-significant byte from rsrcl is packed into the second-least-significant byte or rdest, the most-significant byte from rsrc2 is packed into the second-most- significant byte of rdest; and the most-significant byte from rsrcl is packed into the most-significant byte of rdest. packlβlsb; packlδlsb is a pack least-significant 16-bit halfwords operation. This operation has the following function: if rguard then { rdest<15:0> <- rsrc2<15:0> rdest<31:16> <- rsrcl<15:0>

}

As shown in Figure 23, the packl6lsb operation packs two respective least-significant halfwords from arguments rsrcl and rsrc2 into rdest. The half ord from rsrcl is packed into the most-significant halfword of rdest and the halfword from rsrc2 is packed into the least-significant halfword or rdest. packlβmsb; packl6msb is a pack most-significant 16 bits operation. This operation has the following function: if rguard then { rdest<15:0> <- rsrc2<31:16> rdest<31:16> <- rsrcl<31:l6> }

As shown in Figure 13, the packlδmsb operation packs two respective most-significant halfwords from arguments rsrcl and rsrc2 into rdest. The halfword from rsrcl is packed into the most-significant halfword of rdest and the halfword from rsrc2 is packed into the least-significant halfword or rdest. packbytes ; packbytes is a pack least-significant byte operation. This operation has the following function: if rguard then { rdest<7:0> <- rsrc2<7:0> rdest<15:8> <- rsrcl<7:0>

^}

As shown in Figure 25, the packbytes operation packs two respective least-significant bytes from arguments rsrcl and rsrc2 into rdest. The byte from rsrcl is packed into the second-least-significant byte of rdest and the byte from rsrc2 is packed into the least-significant byte or rdest. The two most-significant bytes of rdest are filled with zeros. quadavq; quadavg is a unsigned byte-wise quad average operation.

This operation has the following function: if rguard then { temp *- (zero_ext8to32 (rsrcl<7: 0>) + zero_ext8to32 (rsrc2<7: 0>)+ l)/2 rdest<7 : 0><-temp<7 : 0> temp <- (zero_ext8to32 (rsrcK15: 8>) + zero_ext8to32 (rsrc2<15:8>)+ l)/2 rdest<15 : 8><-temp<7 : 0> temp <- (zero_ext8to32 (rsrcl<23: 16>) + zero_ext8to32 (rsrc2<23 : 16>) + 1) /2 rdest<23 : 16><-temp<7 : 0> temp <- (zero_ext8to32 (rsrclOl: 24>) + zero_ext8to32 (rsrc2<31: 24>) + 1) /2 rdest01:24><-temp<7: 0> }

As shown in Figure 26, the quadavg operation computes four separate averages of four respective pairs of corresponding 8-bit bytes of rsrcl and rsrc2. All bytes are considered unsigned. The least-significant 8 bits of each average is written to the corresponding byte in rdest. No overflow or underflow detection is performed. quadumulmsb: quadumulmsb is a unsigned quad 8-bit multiply most significant operation. This operation has the following function: if rguard then { temp <- (zero_ext8to32 (rsrcl<7 : 0>) x zero_ext8to32 (rsrc2<7 : 0>) ) rdest<7 : 0><-temp<15 : 8> temp <- (zero_ext8to32 (rsrcl<15: 8>) x zero_ext8to32 (rsrc2<15 : 8>) ) rdest<15:8><-temp<15:8> temp <- (zero_ext8to32 (rsrcl<23: 16>)x zero_ext8to32 (rsrc2<23 : 16>) ) rdest<23 :16>+-temp<15:8> temp <- (zero_ext8to32 (rsrclOl :24>)x zero_ext8to32 (rsrc2<31:24>) ) rdest<31 : 24>«-temp<15 : 8> }

As shown in Figure 27, the quadumulmsb operation computes four separate products of four respective pairs of corresponding 8-bit bytes of rsrcl and rsrc2. All bytes are considered unsigned. The most-significant 8 bits of each 16-bit product is written to the corresponding byte in rdest. ume8ii; umeδii is a unsigned sum of absolute values of signed 8-bit differences operation. This operation has the following function: if rguard then rdest <- abs_val(sign_ext8to32 (rsrclOl: 24>) - sign_ext8to32 (rsrc2<31: 24>) ) + abs_val (sign_ext8to32 (rsrcl<23 : 16>) - sign_ext8to32 (rsrc2<23 : 16>) ) + abs_val(sign_ext8to32 (rsrcl<15:8>) - sign_ext8to32 (rsrc2<15 : 8>) ) + abs_val(sign_ext8to32 (rsrcl<7: 0) - sign_ext8to32 (rsrc2<7 : 0>) ) As shown in Figure 28, the umeδii operation computes four separate differences of four respective pairs of corresponding signed 8-bit bytes of rsrcl and rsrc2 , absolute values of the four differences are summed, and the sum is written to rdest. All computations are performed without lost of precision. umeβuu; umeδuu is a sum of absolute values of unsigned 8-bit differences. This operation has the following function: if rguard then rdest <- abs_val (zero_ext8to32 (rsrclOl: 24>) - zero_ext8to32 (rsrc2<31:24>) )+ abs_val (zero_ext8to32 (rsrcl<23 : 16>) - zero_ext8to32 (rsrc2<23 : 16>) ) + abs_val(zero_ext8to32 (rsrcl<15:8>) - zero_ext8to32 (rsrc2<15 : 8>) ) + abs_val(zero_ext8to32 (rsrcl<7:0) - zero_ext8to32 (rsrc2<7 : 0>) ) As shown in Figure 29, the umeδuu operation computes four separate differences of four respective pairs of corresponding unsigned 8-bit bytes of rsrcl and rsrc2. Absolute values of four differences are summed and the sum is written to rdest. All computations are performed without loss of precision. iclipi; iclipi is a clip signed to signed operation. This operation has the following function: if rguard then rdest <- min (max (rsrcl, - rsrc2-l) , rsrc2) The iclipi operation returns a value of rsrcl clipped into unsigned integer range (-rsrc2-l) to rsrc2 , inclusive. The argument rsrcl is considered a signed integer; rsrc2 is considered an unsigned integer and must have a value between 0 and 0x7fffffff inclusive. uclipi; uclipi is a clip signed to unsigned operation. This operation has the following function: if rguard then rdest <- min (max (rsrcl, 0) , rsrc2)

The uclipi operation returns a value of rsrcl clipped into unsigned integer range 0 to rsrc2 , inclusive. The argument rsrcl is considered an unsigned integer; rsrc2 is considered an unsigned integer. uclipu: uclipu is a clip unsigned to unsigned operation. This operation has the following function: if rguard then{ if rsrcl > rsrc2 then rdest <- rsrc2 else rdest<-rsrcl }

The uclipu operation returns a value of rsrcl clipped into unsigned integer range 0 to rsrc2 , inclusive. The arguments rsrcl and rsrc2 are considered unsigned integers.

By use of the above custom multimedia operations, an application can take advantage of highly parallel microprocessor implementations of multimedia functions with low cost. From the above disclosure, one may clearly understand that the present invention may be used with many highly parallel microprocessor implementations using VLIW, RISC, super scalar, etc. instruction formats. Additionally, one skilled in the art may easily add additional operations based on the above concepts. For example, a quad clipped subtract of bytes is not specifically described; however, clearly one skilled in the art could easily develop this operation based on the above disclosure. There accordingly has been described a system and method for custom operations for use in performing multimedia functions.

In this disclosure, there is shown and described only the preferred embodiment of the invention, but, as aforementioned, it is to be understood that the invention is capable of use in various other combinations and environments and is capable of changes or modifications within the scope of the inventive concept as expressed herein.

Claims

What is claimed is: 1. A computer system comprising: input registers receiving input data, each input data comprising M bits and having operand data comprising N bits of the M bits of input data, where N bits is less than M bits; a processor for performing a number of operations Q on the operand data of the input data in parallel, producing result data of N bits, under control of an instruction of an instruction set; a destination register for storing Q groups of result data as one output of M bits.

2. A computer system comprising: input registers for supplying input data of M bits, each input data comprising at least two operand data, each operand data comprising N bits, where N is less than M; a special purpose processor for performing a group of operations in parallel for selected sets of operand data of the input data, each group of operations producing result data of N bits, said processor performing in response to an instruction of an instruction set; a destination register comprising M bits, for storing the result data of N bits as one output of M bits.

3. A computer system as recited in claim 2, wherein: each input data of a respective input register of M bits comprises a first operand data of N bits and a second operand data of N bits; said processor comprises: means for adding the first operand data of a first input data to the first operand data of a second input data to produce a first result of N bits and adding the second operand data of the first input data to the second operand data of the second input data to produce a second result of N bits of N bits, and means for clipping each respective result into a specified range to produce respective clipped results, each clipped result being N bits; and said destination register stores the respective clipped results together.

4. A computer system as recited in claim 2, wherein: the input data of M bits comprises two operand data of N bits each; said processor comprises: means for computing an absolute value of each operand data, each computation producing a respective absolute value of N bits, and means for clipping each respective absolute value into a specified range to produce respective clipped results, each clipped result being N bits; and said destination register stores the respective clipped results together.

5. A computer system as recited in claim 2, wherein: the input data of M bits comprises a first operand comprising N bits and a second operand comprising N bits; said processor comprises: means for multiplying the first operand data of a first input data to the first operand of a second input data to produce a first product and multiplying the second operand data of the first input data to the second operand data of the second input data to produce a second product, the first and second products each comprising N bits, and means for clipping each respective product into a specified range to produce respective clipped results, each clipped result comprising N bits; and said destination register stores the respective clipped results together.

6. A computer system as recited in claim 2, wherein: the input data of M bits comprises a first operand and a second operand, the first and second operand each comprising N bits ; said processor comprises: means for subtracting the first operand data of a first input data to the first operand of a second input data to produce a first difference and subtracting the second operand data of the first input data to the second operand data of the second input data to produce a second difference, the first and second differences each comprising N bits and means for clipping the first difference and the second difference into a specified range to produce respective clipped results, each clipped result comprising N bits; and said destination register stores the respective clipped results together.

7. A computer system as recited in claim 2, wherein: the input data of M bits comprises P operand data of N bits each, P being at least two; said processor comprises: means for adding a respective operand data of a first input data to a respective operand data of a second input data for each operand data of the P operand data, each adding producing a respective sum of N bits, and means for clipping each respective sum into a specified range to produce P respective clipped results, each clipped result being N bits; and said destination register stores the P respective clipped results.

8. A computer system as recited in claim 2, wherein: the input data of M bits comprises P operand data of N bits each, P being at least two; said processor comprises: means for subtracting a respective operand data of a first input data to a respective operand data of a second input data for each operand data of the P operand data, each subtracting producing a respective difference of N bits, and means for clipping each respective difference into a specified range to produce P respective clipped results, each clipped result being N bits; and said destination register stores the P respective clipped results.

9. A computer system as recited in claim 2, wherein: the input data of M bits comprises P operand data of N bits each, P being at least two; said processor comprises: means for multiplying a respective operand data of a first input data to a respective operand data of a second input data for each operand data of the P operand data, each multiplying producing a respective product of N bits, and means for clipping each respective product into a specified range to produce P respective clipped results, each clipped result being N bits; and said destination register stores the P respective clipped results.

10. A computer system as recited in claim 2, wherein: the input data of M bits comprises P operand data of N bits each, P being at least two; said processor comprises means for computing a respective average of a respective operand data of a first input data and a respective operand data of a second input data for each operand data of the P operand data, each computing producing a respective average of N bits; and said destination register stores the P respective averages.

11. A computer system as recited in claim 2, wherein: the input data of M bits comprises P operand data of N bits each, P being at least two; said processor comprises means for multiplying a respective operand data of a first input data and a respective operand data of a second input data for each operand data of the P operand data, each multiplying producing a respective product of 2*N bits; and said destination register retrieves selected bits of each respective product to form respective intermediate data, the retrieved selected bits totaling N bits, and stores the P respective intermediate data in a destination register, the destination register being of M bits.

12. A computer system comprising: an input register supplying input data of M bits; a processor for retrieving N bits of data of the input data, N being less than M, for P input data; a destination register for storing the respective retrieved N bits of data of the P input data.

13. A computer system comprising: an input register for supplying input data of M bits; a processor for retrieving N bits of data of the input data, N being less than M, for P input data, said processor comprising means for packing the respective retrieved N bits of data of the P input data in a destination register.

14. A computer system as recited in claim 12 wherein: P is two; N is half of M; and said processor retrieves one of the most significant bits of the input data or the least significant bits of the input data.

15. A computer system as recited in claim 12, wherein: a first and a second input data are supplied; said processor retrieves the most significant bits (msb) of each respective input data, each respective most significant bits being supplied as the most significant bits (mmsb) of the most significant bits and the least significant bits (lmsb) of the most significant bits; said means for packing packs the most significant bits of the most significant bits (mmsb) of the first input data as the most significant bits of a destination register; said means for packing packs the most significant bits of the most significant bits (mmsb) of the second input data as the next most significant bits of the destination register; said means for packing packs the least significant bits of the most significant bits (lmsb) of the second input data as the least significant bits of the destination register; and said means for packing packs the least significant bits of the most significant bits (lmsb) of the first input data as the next least significant bits of the destination register.

16. A computer system as recited in claim 12, wherein: a first and a second input data are supplied; said processor retrieves the least significant bits (lsb) of each respective input data, each respective least significant bits being supplied as the most significant bits (mlsb) of the least significant bits and the least significant bits (llsb) of the least significant bits; said means for packing packs the most significant bits of the least significant bits (mlsb) of the first input data as the most significant bits of a destination register; said means for packing packs the most significant bits of the least significant bits (mlsb) of the second input data as the next most significant bits of the destination register; said means for packing packs the least significant bits of the least significant bits (llsb) of the second input data as the least significant bits of the destination register; and said means for packing packs the least significant bits of the least significant bits (llsb) of the first input data as the next least significant bits of the destination register.

17. A computer system as recited in claim 12, wherein: a first and a second input data are supplied; said processor retrieves least significant bits (lsb) of each respective input data; said means for packing packs the least significant bits (lsb) of the second input data as the least significant bits of a destination register; said means for packing packs the least most significant bits (lsb) of the first input data as the next least significant bits of the destination register; and said means for packing packs the most significant bits of the destination register with prespecified bit values.

18. A computer system comprising: an input register for receiving input data, each input data comprising M bits and a number of operand data Q, each operand data comprising N bits, where N is less than or equal to M; a processor for processing said input data, said processing comprising performing a group of operations in parallel on selected operand data and producing respective result data comprising N bits for each group of operations performed; and a destination register for storing Q result data as output data comprising M bits.

19. A computer system as recited in claim 18, wherein said processing is at least one of audio processing and video processing.

20. A computer system as recited in claim 18, wherein said computer system is integrated on a semiconductor substrate.

21. A computer system comprising: input registers for supplying input data, the input data comprising operand data; a processor for performing a number of operations on the operand data, the operations including a clipping function, said processor producing result data; and a destination register for storing selected data of the result data.

22. A computer system as recited in Claim 21, wherein: each input data comprises at least two operand data; and said processor performs selected operations in parallel in response to an instruction of an instruction set, the operations including a clipping function and the operations producing result data.

23. A computer system comprising: a plurality of input registers, each register storing a concatenation of multiple operands; processing means for receiving the operands from the input registers and performing a set of operations in parallel on specific operands of the operands in response to an instruction, the operations including first operations performed on a single operand and second operations performed using multiple operands and each operation producing result data, and each respective set of operations producing respective output data and comprising at least one operation; and a destination register coupled to the processing means for storing the respective output data together.

24. A signal processing system for processing signal data, said system comprising: at least one input register for storing and supplying the signal data; and a processor for performing, under instruction control, a plurality of instructions available in hardware, each instruction directing said processor to perform at least one operation to produce result data, the plurality of instructions comprising at least one instruction for clipping a result of an operation performed on the signal data prior to supplying the result to a destination register.

25. The computer system of Claim 24, wherein said computer system is integrated on a semiconductor substrate.