WO1998028881A1 - Method and apparatus for providing loop coherency - Google Patents

Method and apparatus for providing loop coherency Download PDF

Info

Publication number
WO1998028881A1
WO1998028881A1 PCT/US1997/023074 US9723074W WO9828881A1 WO 1998028881 A1 WO1998028881 A1 WO 1998028881A1 US 9723074 W US9723074 W US 9723074W WO 9828881 A1 WO9828881 A1 WO 9828881A1
Authority
WO
WIPO (PCT)
Prior art keywords
loop
primary
data communications
coherency
incoherency
Prior art date
Application number
PCT/US1997/023074
Other languages
French (fr)
Other versions
WO1998028881B1 (en
Inventor
Dennis Hahn
Jeremy D. Stover
Original Assignee
Symbios, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Symbios, Inc. filed Critical Symbios, Inc.
Priority to AU55274/98A priority Critical patent/AU5527498A/en
Publication of WO1998028881A1 publication Critical patent/WO1998028881A1/en
Publication of WO1998028881B1 publication Critical patent/WO1998028881B1/en

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/28Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/42Loop networks
    • H04L12/437Ring fault isolation or reconfiguration

Abstract

A method and apparatus for providing loop coherency between a multiplicity of nodes. The disclosed technique and apparatus utilize a primary loop (110) for nominal data communications and a normally unutilized secondary loop (116). A loop coherency circuit (122) detects a loop incoherency condition which results in an interruption of the primary loop (110). The loop coherency circuit (122) reroutes the flow of data to a secondary loop segment (116) and back to a primary loop (110) segment to provide a continuous coherent arbitrated loop (100).

Description

METHOD AND APPARATUS FOR PROVIDING LOOP COHERENCY
CROSS REFERENCE TO RELATED APPLICATIONS
The present invention is related to commonly assigned and co-pending U.S. application entitled "Port Bypass Circuit with Loopback Capability", invented by Charles Binford and Jeremy Stover, and having an internal docket number of 96-025 and serial number 08/772,615, filed concurrently herewith on December 23, 1996, and co-pending U.S. application entitled "Methods and Apparatus for Dynamic Topology Configuration in a Daisy-Chained Communication Environment" invented by Charles Binford, Rodney DeKoning and Jeremy Stover, having an internal docket number of 96-027 and serial number 08/771,006, filed concurrently herewith on December 23, 1996, and both of which are hereby incorporated by reference.
1. TECHNICAL FIELD The present invention relates generally to arbitrated loop environments and more specifically to maintaining loop coherency in Fibre Channel arbitrated loop environments.
2. DESCRIPTION OF THE RELATED ART
Fibre Channel is a 1 gigabit per second data transfer interface technology that maps several common transport protocols including IP and SCSI, allowing it to merge to high-speed I/O and networking functionality in a single connectivity technology. Fibre Channel is an open standard as defined by ANSI and OSI standards and operates over copper and fiber optic cabling at distances of up to 10 kilometers. ANSI ASC (Accredited Standards Committee) X3T11 is the primary committee responsible for Fibre Channel. It is unique in its support of multiple inter-operable topologies including point-to-point, arbitrated loop and switching and it offers several classes of service for network optimization. With its large packet sizes, Fibre Channel is ideal for storage, video, graphic and mass data transfer applications.
Fibre Channel Arbitrated Loop was developed with peripheral connectivity in mind. It natively maps SCSI (as SCSI FCP), making it an ideal technology for high speed I/O connectivity. Native Fibre Channel Arbitrated Loop (FC-AL) disk drives allows storage applications to take full advantage of Fibre Channel's gigabit bandwidth, passing SCSI data directly onto the channel with access to multiple servers or nodes. FC-AL supports 127 node addressability and 10 km cabling ranges between nodes. Gigabit bandwidth and functionality also make Fibre Channel technology an attractive solution for server clustering.
Fibre Channel Arbitrated Loop (FC-AL) offers the highest overall performance and distance of any serial interface. Fibre Channel can transfer at 200 Mbytes/sec in full duplex mode over distances of 10 kilometers. Fibre Channel supports dual loop capability to provide a high resiliency environment. If a single loop is unavailable, the second loop continues operation. Fibre Channel hubs represent an additional level of control and resiliency. Hubs provide expansion flexibility where additional hosts and storage subsystems can be added with no disruption in the loop.
Arbitrated loop is implemented as a topology that takes the logic of switched topology and distributes it to all devices on the loop. This enables each device to use the loop as a point-to-point connection. Arbitrated loop works in a fashion where each device arbitrates for loop access, and once granted, has a dedicated connection between sender and receiver. The available bandwidth of the loop is shared between all devices. Since no switch is required to connect multiple devices, the cost per connection is significantly less.
When interconnecting Fibre-Channel Arbitrated Loop (FC-AL) enclosures together containing multiple FC devices, disruption of the loop may arise. For example, a cable may become detached from an enclosure or power may be inadvertently shut off or lost for a particular enclosure, an enclosure may need to be removed from the loop for servicing, etc. Under any of the above conditions, the loop is opened and the system becomes inoperable since each FC device in an FC-AL system acts as a repeater passing data around a loop unidirectionally. In Fibre Channel Arbitrated Loop environments, because each Fibre Channel node acts as a repeater for all other nodes that it is connected to, one failed node will bring the entire loop down. Typically, an active hub or concentrator may be utilized into which each enclosure is connected. However, utilization of an active hub has several disadvantages. The central hub is a single point of failure which will bring down the entire loop if failure of the hub occurs. Additionally, the use of an active hub adds cost to the FC-AL system.
An enhancement to this method of providing loop coherency in Fibre Channel systems is achieved by creating PORT A and PORT B loops. The PORT A loop is utilized exclusively until a failure condition at which time the traffic is switched to the PORT B loop. These loops are created by cabling two fully independent, physical loops between enclosures. Redundant cabling and hardware provide full data path redundancy.
Although a hub or concentrator will automatically bypass a problem port and avoid most faults, it represents a single point of failure. Redundancies can be built into concentrators or fully redundant cabling and concentrators can be used to work around this. A concentrator configuration may detrimentally add to the cost of the loop system.
None of the known techniques to provide loop integrity in a Fibre Channel
Arbitrated Loop environment provide a loop system having scaleable architecture and no central point of failure at a low cost. Thus, there lies a need to provide an economical and scaleable method and apparatus for maintaining loop coherency without a central point of loop failure in Fibre Channel Arbitrated Loop environments.
3. SUMMARY OF THE INVENTION
The present invention provides loop coherency in a Fibre Channel Arbitrated Loop environment without the need for utilizing a central hub. A loop coherency circuit having a pair of loop redundancy chips (LRC) or Port Bypass Circuits within each enclosure is utilized to provide loop coherency in the event of loop failure. The present invention is particularly advantageous in embedded system environments in which multiple Fibre Channel devices are stored locally in a single enclosure.
4. BRIEF DESCRIPTION OF THE DRAWINGS The numerous objects and advantages of the present invention may be better understood by those skilled in the art by reference to the accompanying figures in which:
FIG. 1 depicts a hybrid Fibre Channel Arbitrated Loop system at steady state under normal operating system conditions;
FIG. 2 depicts a Fibre Channel Arbitrated Loop of the present invention comprising three enclosures or loop ports each functioning as FC-AL nodes;
FIG. 3 depicts the Fibre Channel Arbitrated Loop of FIG. 2 further illustrating a loop incoherency condition due to cabling failure;
FIG. 4 depicts the Fibre-Channel Arbitrated Loop of FIG. 2 further illustrating a loop incoherency condition due to node failure; FIG. 5 depicts a Fibre Channel Arbitrated Loop system of the present invention illustrating a host based configuration; and
FIG. 6 depicts a loop coherency circuit fabricated on a single integrated circuit.
5. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to FIG. 1, a typical Fibre Channel Arbitrated Loop system is shown comprising three enclosures or loop ports each functioning as FC-AL nodes. The enclosures (102, 104 and 106) of the loop system 100 may contain a plurality of Fibre Channel devices 108, for example storage devices, disk drives, etc. which may be implemented in a RAID system (redundant array of inexpensive disks), for example. A primary Fibre Channel loop 110 provides a Fibre Channel Arbitrated Loop path for data transfer. The data flow on loop 110 enters each of enclosure at point 112 and egresses from each enclosure at point 114, passing through each of the Fibre Channel devices 108 contained within the enclosure. Since the loop 110 is a single closed path, any break or interruption of the loop 110 will bring down the entire system 100 in typical Fibre Channel Arbitrated Loop systems
Referring now to FIG. 2, a typical Fibre Channel Arbitrated Loop (FC-AL) 100 is shown comprising three enclosures (102, 104 and 106) functioning as FC-AL nodes (also referred to as a loop port). Each enclosure may contain a plurality of Fibre Channel devices 108, for example storage devices, disk drives, etc. which may be implemented in a RAID system (redundant array of inexpensive disks), for example. A primary Fiber Channel loop 110 provides a Fibre Channel Arbitrated Loop path for data transfer. The data flow on primary loop 110 enters each of enclosure at point 112 and egresses from each enclosure at point 114, passing through each of the Fibre Channel devices 108 contained within the enclosure.
A second complete Fibre Channel loop 116 is further provided and is connected to each enclosure at points 118 and 120. The secondary loop 116 is a complete and independent path being wholly separate from the primary loop 110. Data is nominally transferred only on the primary loop 110 so long as the primary loop 110 provides a complete uninterrupted path and all enclosures on the loop are properly powered and functioning. The primary loop is held in steady state by the signal being passed between nodes and being watched by the loop coherency circuit. The secondary standby loop does not carry data but does have signal passed around it to keep it in steady state. A loop coherency circuit will look for signal levels present to hold it in steady state. The secondary loop 116 is utilized only upon a condition of loop incoherency (e.g., a break in the primary loop or a node failure). Upon a condition of loop incoherency, data flow is transferred to the secondary loop 116 which in conjunction with the remaining coherent section of the primary loop 110, provides a complete path for the flow of data to all functioning devices. Thus, the secondary loop 116 may be referred to as a bypass loop. The primary loop 110 and the secondary loop 116 may be provided in a single Fibre Channel cable. Control of the utilization of the secondary loop 116 upon a loop incoherency condition is maintained by a loop coherency circuit 122 provided within each enclosure (102, 104, 106). Each loop coherency circuit includes first and second multiplexers, or MUX, (124 and 126) operably connected to the primary loop 110 and the secondary loop 116, respectively. Each MUX functions to reroute the data flow from its nominal loop to the other respective bypass loop.
Referring now to FIG. 3, the Fibre Channel Arbitrated Loop of FIG. 2 is shown illustrating a loop incoherency condition. As depicted is FIG. 3, data normally flows on the primary loop 110 from node 102 to node 106 to node 104 and then back to node 102. A loop incoherency condition may arise upon a break in the arbitrated loop 100 caused by an inadvertent disconnecting of cabling between enclosures 104 and 106 as illustrated as loop discontinuity 128 which is a physical break in both the primary loop 110 and the secondary loop 116. The primary loop 110 thereupon becomes an open, incomplete path which would normally bring down a typical arbitrated loop. However, the loop coherency circuit 122 of enclosure 106 detects that downstream communications on the primary loop 110 to enclosure 104 have been lost and thereby activates multiplexer 126 associated with enclosure 104 to reroute data from point 114 on the primary loop 110 to point 118 on the bypass loop 116 for node 106. Data thereafter flows from enclosure 106 to enclosure 102 via the bypass loop 116. The direction of signal flow on the bypass loop 116 is in the opposite direction of signal flow on the primary loop 110. Simultaneously, the loop coherency circuit 122 of node 104 detects the loss of upstream communications from enclosure 106 on the primary loop 110 upon the loop incoherency condition indicated at 128 and thereby activates multiplexer 124 associated with enclosure 104 to reroute data from point 118 on the bypass loop 116 to point 120 on the primary loop 110 through node 104. Thus, for a given break on the primary loop 110, data is effectively rerouted to the bypass loop 116 for the failed portion of the loop 110 and then rerouted back the to remaining intact portion of the primary loop 110 such that loop coherency is maintained.
The discontinuity 128 on the loop system 100 is thereby avoided and coherency of the loop system 100 is thereby maintained. Further, a flag or warning may be indicated upon a loop coherency condition such that the discontinuity 128 may be found and remedied (e.g., reconnecting or replacing the cabling).
Referring now to FIG. 4, a Fibre-Channel Arbitrated Loop system is shown exhibiting a loop incoherency condition due to the failure of a node. A loop incoherency condition due to node failure may be caused by the removal of a node such as enclosure 102 from the arbitrated loop system 100. The removal of an enclosure from the loop system 100 may arise in several situations, for example power failure or shutdown, failure of the internal components contained within the enclosure, temporary shutdown for servicing, etc. In order to provide coherency of the arbitrated loop system 100, the loop coherency circuit 122 of enclosure 104 detects the loss of downstream communications to enclosure 102 due to the removal of enclosure 102 from the loop, thereby indicating a loop incoherency condition. Upon detecting a loop incoherency condition, the loop coherency circuit 122 of enclosure 104 activates MUX 126 associated with communications to enclosure 102 to switch the flow of data from the primary loop 110 to the secondary loop 116. Similarly, the loop coherency circuit 122 of enclosure 106 activates MUX 124 when it detects a loop incoherency condition by the loss of upstream communications from the removal of enclosure 102 from the loop 110. Upon detecting a loop incoherency condition, the loop coherency circuit 122 of enclosure 106 activates MUX 124 triggered by a loss of communications from enclosure 102 to switch the flow of data from the secondary loop 116 back to the primary loop 110. The inoperable node 102 is removed from the arbitrated loop system 100 and coherency of the loop system 100 is thereby maintained. Further, a return back to the redundant loop system 100 will occur automatically upon a loop coherency condition such that the failed node 102 being found and remedied (e.g., powered up or repaired).
Referring now to FIG. 5, a Fibre Channel Arbitrated Loop of the present invention is shown illustrating a host based configuration. A host configuration as shown in FIG. 5 may utilized a host enclosure 130 for allocating storage and I/O resources to each of the nodes on the arbitrated loop 110. The host 130 in the host based configuration of FIG. 5 becomes a node on the arbitrated loop 100. The host enclosure 130 includes a loop coherency circuit 122 such as the loop coherency circuits utilized in the other nodes (102, 104 and 106) of the arbitrated loop system 100. The loop coherency circuit 122 of the host enclosure 130 operates to maintain loop coherency in the event of a loop discontinuity or a node failure as described in the descriptions of FIGS. 3 and 4. Other FC-AL devices may be utilized with the arbitrated loop of the present invention in a manner similar to the utilization of the host enclosure 130. The cables between the devices utilize a single standard FC-AL twin-axis cable. The devices may utilize the loop coherency circuit 122 of the present invention to protect the integrity and coherency of the arbitrated loop system 100.
Referring now to FIG. 6, a loop coherency circuit is shown fabricated on a single integrated circuit. The coherency circuit 122 may be fabricated entirely on an integrated circuit 132 for implementation on a Fibre-Channel controller board, for example on a Series 3 Fibre-Channel RAID Controller available from Symbios Logic Inc. of Fort Collins, Colorado. The loop coherency circuit 122 includes first and second multiplexers (124, 126) and first and second detector circuits (134, 136) respectively. Dectors and multiplexors are known in the art, such as those available in repeater hub circuit P/N VSC7120, available from Vitesse Semiconductor Corporation in Camarillo, California. The detector circuits (134, 136) are operably connected at 138 to the multiplexers (124, 126) and function to control the switching of the multiplexers (124, 126) upon detecting a loop incoherency condition. Connection 138 also provides a data path between the detector circuits (134, 136) and the multiplexors (124, 126). The integrated circuit 132 may be utilized in an enclosure functioning as node N in a Fibre Channel Arbitrated Loop. As shown, the integrated circuit connects between the Fibre Channel devices contained in the node N enclosure, ("TO BOX N DEVICES") and ("FROM BOX N DEVICES"), to the previous node ("BOX N-l") and to the succeeding node ("BOX N+l") on the arbitrated loop.
It is believed that the method and apparatus for providing loop coherency in Fibre Channel Arbitrated Loop environments of the present invention and many of its attendant advantages will be understood by the foregoing description, and it will be apparent that various changes may be made in the form, construction and arrangement of the components thereof without departing from the scope and spirit of the invention or without sacrificing all of its material advantages. The form herein before described being merely an explanatory embodiment thereof. It is the intention of the following claims to encompass and include such changes.

Claims

1. A data communications network, comprising: a plurality of nodes, each of said plurality of nodes containing at least one device; a primary loop and a secondary loop each being connected to each of said plurality of nodes; a loop coherency circuit associated with each of said plurality of nodes, each of said loop coherency circuits being operably connected to said primary loop and to said secondary loop, said loop coherency circuit for at least partially routing data between the primary loop and the secondary loop upon detecting a loop incoherency condition such that said primary loop and said secondary loop together form a complete loop.
2. A data communications network as claimed in claim 1, wherein said loop coherency circuit includes first and second link redundancy circuits each being connected to said primary loop and to said secondary loop, said first link redundancy circuit being connected to a previous node and said second link redundancy circuit being connected to a succeeding node.
3. A data communications network as claimed in claim 1, wherein said loop coherency circuit comprises first and second loop incoherency detectors being associated with first and second multiplexers, respectively, said first and second loop coherency detectors for detecting a loop incoherency condition and for controlling said first and second multiplexers, respectively to route data between said primary loop and said secondary loop.
4. A data communications network as claimed in claim 1, wherein said plurality of nodes contain at least one Fibre-Channel device.
5. A data communications network as claimed in claim 1, wherein said primary loop is an independent arbitrated loop.
6. A data communications system as claimed in claim 1, wherein said secondary loop is normally unused for data routing.
7. A data communications network as claimed in claim 1 , wherein said primary loop and said secondary loop together form a complete arbitrated loop during a primary loop incoherency condition.
8. A data communications network system as claimed in claim 1, wherein said primary loop and said secondary physical loop together form a complete Fibre
Channel Arbitrated loop during a primary loop incoherency condition.
9. A data communications network system as claimed in claim 1, wherein said primary loop and said secondary loop include Fibre-Channel arbitrated loop twin- axis cables.
10. A data communications network, comprising: a plurality of nodes, each of said plurality of nodes containing at least one device; a primary loop and a secondary loop each being connected to each of said plurality of nodes; a host for allocating storage and I/O resources to each of said plurality of nodes, said host containing at least one device, said primary loop and said secondary loop connecting said host to said plurality of nodes; and a loop coherency circuit associated with each of said plurality of nodes and with said host, each of said loop coherency circuits being operably connected to said primary loop and to said secondary loop, wherein said loop coherency circuit at least partially routes data between the primary loop and the secondary physical loop upon detection of a loop incoherency condition such that said primary loop and said secondary loop together form a complete loop.
11. A data communications network as claimed in claim 10, wherein said loop coherency circuit includes first and second link redundancy circuits each being connected to said primary loop and to said secondary loop, said first link redundancy circuit being connected to a previous node and said second link redundancy circuit being connected to a succeeding node.
12. A data communications network as claimed in claim 10, wherein said loop coherency circuit associated with said host includes first and second link redundancy circuits each being connected to said primary loop and to said secondary loop, said first link redundancy circuit being connected from said host to a previous node and said second link redundancy circuit being connected from said host to a succeeding node.
13. A data communications network as claimed in claim 10, wherein said loop coherency circuit comprises first and second loop incoherency detectors being associated with first and second multiplexers, respectively, said first and second loop coherency detectors for detecting a loop incoherency condition and for controlling said first and second multiplexers, respectively to route data between said primary loop and said secondary loop.
14. A data communications network as claimed in claim 10, wherein said device of said plurality of nodes is a Fibre-Channel device.
15. A data communications network as claimed in claim 10, wherein said device of said host is a Fibre-Channel device.
16. A data communications network as claimed in claim 10, wherein said primary loop is an independent arbitrated loop and said secondary physical loop.
17. A data communications system as claimed in claim 10, wherein said secondary loop is normally unused for data routing.
18. A data communications network as claimed in claim 10, wherein said primary loop and said secondary physical loop together form a complete arbitrated loop during a primary loop incoherency condition.
19. A data communications network system as claimed in claim 10, wherein said primary loop and said secondary loop together form a complete Fibre Channel Arbitrated loop during a primary loop incoherency condition.
20. A data communications network as claimed in claim 10, wherein said primary loop and said secondary loop include Fibre-Channel arbitrated loop twin-axis cables.
21. A method for providing loop coherency in a data communications system, comprising: nominally routing data communications flow on a primary loop; detecting a loop incoherency condition in the primary loop; and at least partially rerouting data between a primary loop segment and a secondary loop segment such that the primary loop and the secondary loop together comprise a coherent loop.
22. The method according to claim 21 wherein said detecting step includes detecting a break in the primary loop path between nodes of the data communications system.
23. The method according to claim 21 wherein said detecting step includes detecting a removal of a node from the data communications system.
24. The method according to claim 21 wherein said rerouting step includes rerouting data upstream from the detected loop incoherency condition from the primary loop to the secondary loop.
25. The method according to claim 21 wherein said rerouting step includes rerouting data downstream from the detected loop incoherency condition from the secondary loop segment to the primary loop segment.
26. The method according to claim 21, wherein said primary loop is an independent arbitrated loop.
27. The method according to claim 21, wherein said secondary loop is normally unused for data routing.
28. The method according to claim 21, wherein said primary loop and said secondary loop include Fibre-Channel arbitrated loop twin-axis cables.
29. The method according to claim 21, further comprising the step of automatically rerouting data back to said primary loop while said secondary loop remains at a steady state condition upon the loop incoherency condition being remedied.
30. A method of operating a loop data communications system to provide loop coherency, comprising: nominally routing data communications flow through the loop data communications system on a primary loop, said primary loop and a secondary physical loop being held in a steady state condition by being provided a steady state signal; monitoring the loop coherency of the loop data communications system by monitoring the steady state signal of said primary loop and said secondary physical loop; detecting a loop incoherency condition in the loop data communications system by detecting the loss of the steady state signal from said primary loop or said secondary physical loop; and at least partially rerouting data between a segment of said primary loop and a segment of said secondary loop such that the primary loop and said secondary physical loop form a complete coherent loop in a steady state condition.
31. The method according to claim 30, wherein said detecting step includes the step of detecting the loss of upstream data communications to a present node of the loop data communications system from a preceding node of the loop data communications system.
32. The method according to claim 31, wherein said detecting step includes the step of detecting the loss of downstream data communications from a present node of the loop data communications system to a succeeding node of the loop data communications system.
33. The method according to claim 31 wherein said detecting step includes detecting a break in the primary loop path between nodes of the loop data communications system.
34. The method according to claim 31 wherein said detecting step includes detecting a removal of a node from the loop data communications system.
35. The method according to claim 31 wherein said rerouting step includes rerouting data upstream from the detected loop incoherency condition from the primary loop segment to the secondary physical loop segment.
36. The method according to claim 31 wherein said rerouting step includes rerouting data downstream from the detected loop incoherency condition from the secondary loop segment to the primary loop segment.
37. The method according to claim 31, wherein said primary loop is an independent arbitrated loop and said secondary physical loop is a physical normally unused cable loop.
38. The method according to claim 31, wherein said primary loop above and said secondary physical loop above are Fibre Channel Arbitrated loops.
39. The method according to claim 31, wherein said primary loop and said secondary loop include Fibre-Channel arbitrated loop twin-axis cables.
40. The method according to claim 31, further comprising the step of automatically rerouting data back to said primary loop while said secondary physical loop remains at a steady state condition upon the loop incoherency condition being remedied.
41. A loop coherency circuit for providing loop coherency on a loop data communications system, comprising: first and second multiplexers; and first and second detector circuits, operably connected to said first and second multiplexers, respectively, for controlling the switching of said first and second multiplexers in response to a loop incoherency condition in the loop data communications system.
42. A loop coherency circuit as claimed in claim 41, further comprising an integrated circuit substrate upon which said first and second multiplexers and said first and second detector circuits are fabricated.
PCT/US1997/023074 1996-12-23 1997-12-15 Method and apparatus for providing loop coherency WO1998028881A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU55274/98A AU5527498A (en) 1996-12-23 1997-12-15 Method and apparatus for providing loop coherency

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/772,616 1996-12-23
US08/772,616 US5991891A (en) 1996-12-23 1996-12-23 Method and apparatus for providing loop coherency

Publications (2)

Publication Number Publication Date
WO1998028881A1 true WO1998028881A1 (en) 1998-07-02
WO1998028881B1 WO1998028881B1 (en) 1998-09-17

Family

ID=25095660

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1997/023074 WO1998028881A1 (en) 1996-12-23 1997-12-15 Method and apparatus for providing loop coherency

Country Status (3)

Country Link
US (1) US5991891A (en)
AU (1) AU5527498A (en)
WO (1) WO1998028881A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004109688A1 (en) * 2003-06-10 2004-12-16 Samsung Electronics Co., Ltd. System and method for audio/video data copy protection

Families Citing this family (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6185203B1 (en) 1997-02-18 2001-02-06 Vixel Corporation Fibre channel switching fabric
US6118776A (en) * 1997-02-18 2000-09-12 Vixel Corporation Methods and apparatus for fiber channel interconnection of private loop devices
JP3196726B2 (en) * 1998-06-10 2001-08-06 日本電気株式会社 Disk array connection system, fault occurrence device detection method thereof, and recording medium recording control program therefor
US6567890B1 (en) 1999-06-30 2003-05-20 Emc Corporation Fibre channel port by-pass selector section for dual ported disk drives
US6629216B1 (en) 1999-06-30 2003-09-30 Emc Corporation Fibre channel by-pass
US6636934B1 (en) 1999-06-30 2003-10-21 Emc Corporation Fiber channel port by-pass selector section for dual ported disk drives
US6581136B1 (en) 1999-06-30 2003-06-17 Emc Corporation Fibre channel data storage system having expansion/contraction
US6459701B1 (en) * 1999-08-06 2002-10-01 Emulex Corporation Variable access fairness in a fibre channel arbitrated loop
US6571355B1 (en) * 1999-12-29 2003-05-27 Emc Corporation Fibre channel data storage system fail-over mechanism
US6615315B1 (en) 1999-12-29 2003-09-02 Emc Corporation Fibre channel data storage system having improved fro-end I/O adapted hub
US6560683B1 (en) 1999-12-29 2003-05-06 Emc Corporation Fibre channel data storage system having improved rear-end I/O adapted hub
US6574687B1 (en) 1999-12-29 2003-06-03 Emc Corporation Fibre channel data storage system
US6775686B1 (en) 2000-08-30 2004-08-10 Motorola, Inc. High availability redundant array of data storage elements that bridges coherency traffic
US6975590B2 (en) * 2000-09-07 2005-12-13 Eurologic Systems Limited Fiber-channel arbitrated-loop split loop operation
US6980510B1 (en) * 2000-09-12 2005-12-27 International Business Machines Corporation Host interface adaptive hub storage system
US6684282B1 (en) 2001-01-26 2004-01-27 Dell Products L.P. System and method for adding an internal RAID controller
US20020141402A1 (en) * 2001-03-08 2002-10-03 Chang Li-Tien Telecommunication auto-looper
IES20010611A2 (en) * 2001-03-08 2002-09-18 Richmount Computers Ltd Distributed lock management chip
JP3536829B2 (en) * 2001-06-14 2004-06-14 日本電気株式会社 Link diagnosis method and apparatus for FC-AL system
US7200108B2 (en) * 2001-06-29 2007-04-03 International Business Machines Corporation Method and apparatus for recovery from faults in a loop network
JP2003067263A (en) * 2001-08-22 2003-03-07 Fujitsu Ltd Connection control circuit and information storage device
US6766482B1 (en) 2001-10-31 2004-07-20 Extreme Networks Ethernet automatic protection switching
US6732201B2 (en) * 2001-12-17 2004-05-04 Lsi Logic Corporation Hardware speed selection behind a disk array controller
JP3722429B2 (en) * 2002-01-17 2005-11-30 インターナショナル・ビジネス・マシーンズ・コーポレーション EXTERNAL STORAGE DEVICE, CONTROL DEVICE, EXTERNAL STORAGE SYSTEM, CONTROL METHOD, PROGRAM, AND RECORDING MEDIUM
US7630300B2 (en) * 2002-07-02 2009-12-08 Emulex Design & Manufacturing Corporation Methods and apparatus for trunking in fibre channel arbitrated loop systems
US7664018B2 (en) * 2002-07-02 2010-02-16 Emulex Design & Manufacturing Corporation Methods and apparatus for switching fibre channel arbitrated loop devices
US7397788B2 (en) * 2002-07-02 2008-07-08 Emulex Design & Manufacturing Corporation Methods and apparatus for device zoning in fibre channel arbitrated loop systems
US7382790B2 (en) * 2002-07-02 2008-06-03 Emulex Design & Manufacturing Corporation Methods and apparatus for switching fibre channel arbitrated loop systems
US7660316B2 (en) * 2002-07-02 2010-02-09 Emulex Design & Manufacturing Corporation Methods and apparatus for device access fairness in fibre channel arbitrated loop systems
WO2004034641A1 (en) * 2002-10-09 2004-04-22 Xyratex Technology Limited Connection apparatus and method for network testers and analysers
US8005918B2 (en) * 2002-11-12 2011-08-23 Rateze Remote Mgmt. L.L.C. Data storage devices having IP capable partitions
US7170890B2 (en) 2002-12-16 2007-01-30 Zetera Corporation Electrical devices with improved communication
JP2006506847A (en) 2002-11-12 2006-02-23 ゼテーラ・コーポレイシヨン Communication protocol, system and method
US7649880B2 (en) 2002-11-12 2010-01-19 Mark Adams Systems and methods for deriving storage area commands
US7362697B2 (en) * 2003-01-09 2008-04-22 International Business Machines Corporation Self-healing chip-to-chip interface
US20040160975A1 (en) * 2003-01-21 2004-08-19 Charles Frank Multicast communication protocols, systems and methods
US7379418B2 (en) * 2003-05-12 2008-05-27 International Business Machines Corporation Method for ensuring system serialization (quiesce) in a multi-processor environment
US7386768B2 (en) * 2003-06-05 2008-06-10 Intel Corporation Memory channel with bit lane fail-over
US6883300B2 (en) * 2003-07-11 2005-04-26 Allan Sanders Assembly including a chain for suspending an article such as a light and for concealing an electrical conductor
JP2005031928A (en) * 2003-07-11 2005-02-03 Hitachi Ltd Storage system and method for specifying failure of storage system
US7103826B2 (en) * 2003-07-31 2006-09-05 Hewlett-Packard Development Company, L.P. Memory system and controller for same
US7545817B1 (en) * 2003-12-01 2009-06-09 Vitesse Semiconductor Corporation Data loop port acceleration circuit
US20050149783A1 (en) * 2003-12-11 2005-07-07 International Business Machines Corporation Methods and apparatus for testing an IC
US8243590B2 (en) * 2003-12-12 2012-08-14 Broadcom Corporation Method and system for seamless dual switching in a port bypass controller
US7619981B2 (en) * 2004-03-15 2009-11-17 International Business Machines Corporation Apparatus, system, and method for identifying network mis-cabling
US7539891B2 (en) * 2004-06-18 2009-05-26 International Business Machines Corporation Switched FC-AL fault tolerant topology
US7702850B2 (en) 2005-03-14 2010-04-20 Thomas Earl Ludwig Topology independent storage arrays and methods
US7620981B2 (en) * 2005-05-26 2009-11-17 Charles William Frank Virtual devices and virtual bus tunnels, modules and methods
US8819092B2 (en) * 2005-08-16 2014-08-26 Rateze Remote Mgmt. L.L.C. Disaggregated resources and access methods
US7743214B2 (en) 2005-08-16 2010-06-22 Mark Adams Generating storage system commands
US9270532B2 (en) 2005-10-06 2016-02-23 Rateze Remote Mgmt. L.L.C. Resource command messages and methods
US7924881B2 (en) 2006-04-10 2011-04-12 Rateze Remote Mgmt. L.L.C. Datagram identifier management
US7584378B2 (en) * 2006-09-07 2009-09-01 International Business Machines Corporation Reconfigurable FC-AL storage loops in a data storage system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0453273A2 (en) * 1990-04-20 1991-10-23 Matsushita Electric Industrial Co., Ltd. Loop back method for loop type LAN transmission line
US5535035A (en) * 1994-09-15 1996-07-09 International Business Machines Corporation Optical fiber ring communications system and communications method

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4064369A (en) * 1975-01-31 1977-12-20 North Electric Company Method and apparatus for path testing in a time division multiplex switching network
US4042780A (en) * 1975-07-23 1977-08-16 Johnson Controls, Inc. Multiple message frame adaptor apparatus for loop communication system
US4454508A (en) * 1982-03-05 1984-06-12 Burroughs Corporation Timed token ring
CA1252168A (en) * 1985-07-24 1989-04-04 Kenneth A. Bobey Communications network
US4837856A (en) * 1987-05-04 1989-06-06 Glista Jr Andrew S Fault-tolerant fiber optic coupler/repeater for use in high speed data transmission and the like
FR2617354B1 (en) * 1987-06-29 1994-03-04 Applusix A X COUPLERS FOR INFORMATION TRANSMISSION NETWORKS AND RESULTING NETWORKS
US4927225A (en) * 1989-05-30 1990-05-22 Finisar Corporation 2×2 Optical bypass switch
JPH03230639A (en) * 1990-02-05 1991-10-14 Mitsubishi Electric Corp Data communication equipment
US5164960A (en) * 1990-02-15 1992-11-17 Advanced Micro Devices Inc. Medium attachment unit for use with twisted pair local area network
US5134619A (en) * 1990-04-06 1992-07-28 Sf2 Corporation Failure-tolerant mass storage system
US5317198A (en) * 1990-06-26 1994-05-31 The Mitre Corporation Optically controlled remote by-pass switch
US5182747A (en) * 1990-06-26 1993-01-26 International Business Machines Corporation Method for controlling the insertion of stations into fddi network
US5289589A (en) * 1990-09-10 1994-02-22 International Business Machines Corporation Automated storage library having redundant SCSI bus system
JP2754922B2 (en) * 1991-01-11 1998-05-20 三菱電機株式会社 Transmission system and transmission method
US5249183A (en) * 1991-03-14 1993-09-28 Level One Communications, Inc. Interfacing unit for local area networks
JP2637299B2 (en) * 1991-03-20 1997-08-06 富士通株式会社 External monitoring device for communication systems
US5251213A (en) * 1992-05-12 1993-10-05 Microcom Systems, Inc. Multiport source routing token ring bridge apparatus
US5406401A (en) * 1992-10-02 1995-04-11 At&T Corp. Apparatus and method for selective tributary switching in a bidirectional ring transmission system
US5517498A (en) * 1993-09-20 1996-05-14 International Business Machines Corporation Spatial reuse of bandwidth on a ring network
US5522047A (en) * 1993-12-15 1996-05-28 Xlnt Designs, Inc. Graceful insertion of a tree into a ring network
US5485576A (en) * 1994-01-28 1996-01-16 Fee; Brendan Chassis fault tolerant system management bus architecture for a networking
JP3439533B2 (en) * 1994-06-24 2003-08-25 富士通株式会社 SDH2-fiber ring optical multiplexer having selective protection function
US5490007A (en) * 1994-10-31 1996-02-06 Hewlett-Packard Company Bypass switching and messaging mechanism for providing intermix data transfer for a fiber optic switch
KR960027720A (en) * 1994-12-23 1996-07-22 양승택 Hybrid network protection / recovery device for synchronous digital line splitter (SDH DXC)
US5659570A (en) * 1995-01-30 1997-08-19 Harris Corporation Circuit and method for loopback test and on-hook transmission integrated in a telephone subscriber line interface circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0453273A2 (en) * 1990-04-20 1991-10-23 Matsushita Electric Industrial Co., Ltd. Loop back method for loop type LAN transmission line
US5535035A (en) * 1994-09-15 1996-07-09 International Business Machines Corporation Optical fiber ring communications system and communications method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004109688A1 (en) * 2003-06-10 2004-12-16 Samsung Electronics Co., Ltd. System and method for audio/video data copy protection

Also Published As

Publication number Publication date
US5991891A (en) 1999-11-23
AU5527498A (en) 1998-07-17

Similar Documents

Publication Publication Date Title
US5991891A (en) Method and apparatus for providing loop coherency
US6895528B2 (en) Method and apparatus for imparting fault tolerance in a switch or the like
US6055228A (en) Methods and apparatus for dynamic topology configuration in a daisy-chained communication environment
US20080215910A1 (en) High-Availability Networking with Intelligent Failover
JP3818613B2 (en) Fiber Channel arbitrated dynamic loop sizing
US6411599B1 (en) Fault tolerant switching architecture
WO1998028881B1 (en) Method and apparatus for providing loop coherency
JPH04154242A (en) Network failure recovery system
US6636478B1 (en) Configurable scalable communications equipment protection method system
US20030179700A1 (en) Method for restoring a virtual path in an optical network using 1‘protection
KR20070033866A (en) Recording medium recording information processing apparatus, communication load balancing method and communication load balancing program
US20050243716A1 (en) Systems and methods implementing 1‘and N:1 line card redundancy
US7263060B1 (en) Multiple switch protected architecture
JP3811007B2 (en) Virtual connection protection switching
US20040085895A1 (en) Apparatus and method for protection switching
CN110213162B (en) Fault-tolerant routing method for large-scale computer system
US8208370B1 (en) Method and system for fast link failover
US20050050243A1 (en) Modified core-edge topology for a fibre channel network
US6347074B1 (en) Centralized method and system for excluding components from a restoral route in a communications network
US6980510B1 (en) Host interface adaptive hub storage system
JP3621634B2 (en) Redundant configuration switching system
US6498779B1 (en) Multiple endpoint paths
US20130111259A1 (en) Connection control apparatus, storage system, and control method of connection control apparatus
US6973041B1 (en) Path AIS insertion for concatenated payloads across multiple processors
US7539891B2 (en) Switched FC-AL fault tolerant topology

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GE GH HU IL IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT UA UG UZ VN YU ZW AM AZ BY KG KZ MD RU TJ TM

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW SD SZ UG ZW AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase