WO1998032213A3 - Leistungsmodul mit einer aktive halbleiterbauelemente und passive bauelemente aufweisenden schaltungsanordnung sowie herstellungsverfahren hierzu - Google Patents

Leistungsmodul mit einer aktive halbleiterbauelemente und passive bauelemente aufweisenden schaltungsanordnung sowie herstellungsverfahren hierzu Download PDF

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Publication number
WO1998032213A3
WO1998032213A3 PCT/EP1998/000655 EP9800655W WO9832213A3 WO 1998032213 A3 WO1998032213 A3 WO 1998032213A3 EP 9800655 W EP9800655 W EP 9800655W WO 9832213 A3 WO9832213 A3 WO 9832213A3
Authority
WO
WIPO (PCT)
Prior art keywords
components
active semiconductor
circuit arrangement
passive components
printed
Prior art date
Application number
PCT/EP1998/000655
Other languages
English (en)
French (fr)
Other versions
WO1998032213A2 (de
Inventor
Hans-Peter Feustel
Friedrich Loskarn
Reinhard Rueckert
Original Assignee
Alsthom Cge Alcatel
Feustel Hans Peter
Friedrich Loskarn
Reinhard Rueckert
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alsthom Cge Alcatel, Feustel Hans Peter, Friedrich Loskarn, Reinhard Rueckert filed Critical Alsthom Cge Alcatel
Priority to JP53376998A priority Critical patent/JP2001508240A/ja
Priority to US09/341,527 priority patent/US6344973B1/en
Priority to EP98906929A priority patent/EP1008231A2/de
Publication of WO1998032213A2 publication Critical patent/WO1998032213A2/de
Publication of WO1998032213A3 publication Critical patent/WO1998032213A3/de

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/162—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01067—Holmium [Ho]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0355—Metal foils
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

Die Erfindung betrifft ein Leistungsmodul mit einer aktive Halbleiterbauelemente (11) und passive Bauelemente (10) aufweisenden Schaltungsanordnung und mit einem Schaltungsträger, wobei zumindest ein Teil der aktiven Halbleiterbauelemente (11) auf ein DCB-Substrat (3) aufgelötet und zumindest ein Teil der passiven Bauelemente in Dickschichttechnik auf mindestens einen Keramikträger (21) gedruckt ist. Die Oberseite des DCB-Substrats (3) ist zur Bildung von Leiterbahnen und von Anschlußflächen zur Aufnahme der aktiven Halbleiterbauelemente (11) und der passiven Bauelemente (10) der Schaltungsanordnung strukturiert. Auf den Keramikträger (21) ist für jedes passive Bauelement (10) in Dickschichttechnik eine erste Druckschicht und mindestens eine Kontaktfläche als weitere, sich lateral an die erste Druckschicht anschließende Druckschicht gedruckt. Die Keramikträger (21) für die passiven Bauelemente (10) in Dickschichttechnik sind über die mindestens eine Kontaktfläche (14) mit der/den korrespondierenden Anschlußfläche/n des DCB-Substrats (3) über eine Lötstelle verbunden.
PCT/EP1998/000655 1997-01-14 1998-01-14 Leistungsmodul mit einer aktive halbleiterbauelemente und passive bauelemente aufweisenden schaltungsanordnung sowie herstellungsverfahren hierzu WO1998032213A2 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP53376998A JP2001508240A (ja) 1997-01-14 1998-01-14 能動半導体部品および受動部品を備えた回路装置を有するパワーモジュールならびにその製造方法
US09/341,527 US6344973B1 (en) 1997-01-14 1998-01-14 Power module with a circuit arrangement comprising active semiconductor components and passive components, and method for producing same
EP98906929A EP1008231A2 (de) 1997-01-14 1998-01-14 Leistungsmodul mit einer aktive halbleiterbauelemente und passive bauelemente aufweisenden schaltungsanordnung sowie herstellungsverfahren hierzu

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19700963A DE19700963C2 (de) 1997-01-14 1997-01-14 Verfahren zur Herstellung eines Leistungsmoduls mit einer aktive Halbleiterbauelemente und passive Halbleiterbauelemente aufweisenden Schaltungsanordnung
DE19700963.8 1997-01-14

Publications (2)

Publication Number Publication Date
WO1998032213A2 WO1998032213A2 (de) 1998-07-23
WO1998032213A3 true WO1998032213A3 (de) 1999-03-18

Family

ID=7817310

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP1998/000655 WO1998032213A2 (de) 1997-01-14 1998-01-14 Leistungsmodul mit einer aktive halbleiterbauelemente und passive bauelemente aufweisenden schaltungsanordnung sowie herstellungsverfahren hierzu

Country Status (5)

Country Link
US (2) US6344973B1 (de)
EP (1) EP1008231A2 (de)
JP (1) JP2001508240A (de)
DE (1) DE19700963C2 (de)
WO (1) WO1998032213A2 (de)

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US6965165B2 (en) 1998-12-21 2005-11-15 Mou-Shiung Lin Top layers of metal for high performance IC's
EP1063700B1 (de) * 1999-06-22 2012-07-25 Infineon Technologies AG Substrat für Hochspannungsmodule
DE10024516B4 (de) * 2000-05-18 2006-03-09 eupec Europäische Gesellschaft für Leistungshalbleiter mbH & Co. KG Leistungshalbleitermodul
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DE10204200A1 (de) * 2002-02-01 2003-08-21 Conti Temic Microelectronic Leistungsmodul
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US8368150B2 (en) * 2003-03-17 2013-02-05 Megica Corporation High performance IC chip having discrete decoupling capacitors attached to its IC surface
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JP4091562B2 (ja) * 2004-03-29 2008-05-28 ファナック株式会社 モータ駆動装置
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Also Published As

Publication number Publication date
DE19700963A1 (de) 1998-07-16
EP1008231A2 (de) 2000-06-14
JP2001508240A (ja) 2001-06-19
WO1998032213A2 (de) 1998-07-23
US6344973B1 (en) 2002-02-05
DE19700963C2 (de) 2000-12-21
US20020008967A1 (en) 2002-01-24

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