WO1998033211A1 - Method for casing integrated circuits - Google Patents

Method for casing integrated circuits Download PDF

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Publication number
WO1998033211A1
WO1998033211A1 PCT/EP1998/000260 EP9800260W WO9833211A1 WO 1998033211 A1 WO1998033211 A1 WO 1998033211A1 EP 9800260 W EP9800260 W EP 9800260W WO 9833211 A1 WO9833211 A1 WO 9833211A1
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WO
WIPO (PCT)
Prior art keywords
main surface
carrier substrate
front main
connection
carrier
Prior art date
Application number
PCT/EP1998/000260
Other languages
German (de)
French (fr)
Inventor
Michael Feil
Original Assignee
Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
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Publication date
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Publication of WO1998033211A1 publication Critical patent/WO1998033211A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Definitions

  • the present invention relates to a method for packaging integrated circuits (ICs) which enables the production of packaged integrated circuits in chip size (chip size package).
  • ICs integrated circuits
  • Integrated circuits are typically marketed in ceramic or plastic packages.
  • the space requirement of the housing in relation to the chip size is very unfavorable. Therefore, in particular with multi-pole ICs, there are strong efforts to reduce the housing size to the chip size (chip size package, abbreviation: CSP).
  • the finished silicon wafers (silicon wafers) have generally been cut into individual chips in a first step using a saw and then further processed on a chip basis.
  • the further work steps differ depending on the type of housing.
  • the chips When pressing into plastic housings (transfer molds), the chips are attached to a lead frame with an adhesive. The electrical connections from the chip to the carrier frame are made by wire bonding. The parts are then given a plastic coating in an injection press. The final steps are deburring, punching and bending the connecting legs, as well as labeling.
  • the housing When using ceramic housings, the housing is already prefabricated. The chips are usually glued into a recess provided for this purpose. The electrical Contacting is again done by wire bonding. The last step is to solder a housing cover. A hermetically sealed housing is thus achieved
  • Another, hermetically sealed housing is the metal housing.
  • the working steps are similar to the procedure for the ceramic housing.
  • the housing cover is usually welded onto the metal housing.
  • a method for housing integrated circuits which reduces the area requirement of the housing approximately to chip size.
  • a silicon substrate with integrated circuits and pads is first connected to the front of a carrier substrate. After the connection, solder bumps are attached to the back of the carrier substrate and electrical connections are made between the solder bumps and the electrical connections of the integrated circuits through the carrier substrate.
  • US-A-5,535,101 a method for connecting a single chip to a carrier is known.
  • the carrier is preferably larger than the chip.
  • the carrier is also substantially larger than the chip. No full-wafer connection technology is therefore used in either method.
  • the invention has for its object to provide a method for packaging ICs in chip size, which can be carried out without the risk of a reduction in yield.
  • the present invention now relates to a method for housing integrated circuits with the following method steps:
  • - Providing a semiconductor wafer with a plurality of integrated circuits, which has electrical connection areas on a front main surface, and; - Providing a carrier substrate with a front and a rear main surface having the electrical connection surfaces, electrical connection surfaces of the front main surface being electrically conductively connected to electrical connection surfaces of the rear main surface via vias;
  • a completely processed semiconductor substrate with one or more integrated circuits is initially provided.
  • This semiconductor substrate has electrical connection surfaces on a front main surface.
  • the main surface on the front side is to be understood as the side of the semiconductor substrate on which the integrated circuits are located.
  • a carrier substrate is provided which has electrical connection surfaces on its front and rear main surface.
  • the electrical connection surfaces on the front side are already electrically conductively connected to the electrical connection surfaces on the rear side via vias.
  • Vias refer to any type of electrically conductive connection through the carrier substrate.
  • the vias can therefore be direct or indirect, e.g. over metallization levels in the carrier substrate.
  • the two substrates provided, the semiconductor substrate and the carrier substrate, are finally adjusted with respect to one another with their respective front-side main surface in such a way that the connection surfaces which have to be connected lie opposite one another.
  • the front connection surfaces of the semiconductor substrate and of the carrier substrate will therefore generally match each other in mirror image.
  • the two main surfaces on the front are connected to one another, so that there is both a mechanical connection between the semiconductor substrate and the carrier substrate, and also an electrically conductive connection between the mutually aligned connection surfaces.
  • a housing size can be realized which is equal to the chip size. Since the semiconductor substrate and carrier substrate are connected, after both substrates have been processed independently of one another, no further process steps after the connection are necessary, which could reduce the yield.
  • the connection between the semiconductor substrate and the carrier substrate that is to say the mechanical fastening and the electrical connection, can moreover take place in a single work step, as will be described below.
  • the method can also be carried out advantageously at the wafer level. Since a large number of chips can be housed in the wafer network and the process steps can be simplified, this enables a drastic reduction in costs. After the method according to the invention has been carried out, there are thus finished housed components.
  • the method can be carried out with a semiconductor substrate, the electrical connection areas of which have been placed on active areas, so that a further area saving (i.e. more ICs per wafer) and thus cost reduction is achieved.
  • Another advantage is that, due to the freedom in the manufacture of the carrier substrate, different connection grids and pin assignments can be realized on the front and rear of the carrier substrate.
  • FIG. 1 an example of the side view of a unit made from the semiconductor wafer and carrier substrate produced by the method according to the invention
  • Figure 2 the side view of a portion of a unit according to Figure 1, in which
  • Semiconductor wafers and carrier substrates are connected via double-sided metallic bumps and a non-conductive adhesive;
  • FIG. 3 shows the side view of a region of a unit according to FIG. 1, in which the semiconductor wafer and carrier substrate are connected to one another by an anisotropic adhesive;
  • Figure 4a the side view of a portion of a unit according to Figure 1, in which
  • FIG. 4b a top view of an isolated chip from FIG. 4a;
  • FIG. 5 an example of the side view of a region of a carrier substrate, as is used in the method according to the invention.
  • a silicon wafer is used as the semiconductor substrate (1).
  • the further process steps are carried out at the wafer level.
  • a connection of the entire surface of the wafer (1) to the carrier (4) is carried out. This is shown in Figure 1.
  • the front main surface (2) of the semiconductor wafer (1) and the front main surface (5) of the carrier substrate (4) with the respective connection surfaces (3, 7) are adjusted to one another and connected to one another.
  • the connection patterns which are formed by the arrangement of the electrical connection surfaces (3, 7) on the front main surfaces (2, 5) match each other in mirror image.
  • the mechanical fastening and the production of the electrical connections from the wafer to the carrier are achieved simultaneously in one work step.
  • the following options are available for the design of the connecting means.
  • both on the wafer (2) and on the carrier side (5) are reinforced by electrically conductive, usually metallic bumps (bumps 11).
  • An electrically non-conductive adhesive (12) is applied to the entire surface (e.g. by spinning or
  • an anisotropically conductive adhesive (13) is used for the connection.
  • Anisotropically conductive adhesives are filled with metal or metallized plastic balls in such a way that an electrically conductive connection (14) is formed only under pressure in the direction perpendicular to the joint surface.
  • This adhesive is also applied over the entire surface to one or both joining partners. In addition to the methods mentioned under a), this can also be in the form of a laminated on
  • underfill As a rule on the saw, to prevent water or saw dust from entering between the chip and carrier, an underfill on a plastic basis (underfill) must be provided.
  • underfill a very thin epoxy resin is used at the wafer level, which is drawn into the spaces between the wafer and the carrier by capillary forces.
  • This underfilling also serves to compensate for mechanical stresses between the wafer and the carrier. Such stresses arise in particular when using carrier materials that are not adapted to the thermal expansion coefficient of the silicon wafer (e.g. printed circuit boards or flex materials).
  • FIGS. 4a and b A further, very advantageous design of the connecting means is shown in FIGS. 4a and b.
  • the methods known from flip chip technology for producing solder bumps and matching metallizations are also used here.
  • the solder bumps (15) can (as in c)) be applied to the connection surfaces (3, 7) on one or both front main surfaces (2, 5).
  • soldering bumps (15), which are later on a common chip (10) after being separated, are enclosed by a soldering frame (16).
  • the solder frame has roughly the outline of the chip. However, the shape can vary as long as the purpose of the soldering frame to prevent water or saw dust from entering between the chip and the carrier is fulfilled.
  • FIG. 4b shows a top view of an isolated chip (10) with soldering bumps (15) and soldering frame (16).
  • the saw cuts (18) for separating the chips (10) from the wafer (1) are shown in FIG. 4a.
  • the soldering frames can be produced during the processing of the carrier substrate or the silicon wafer in the same process step as the application of the solder bumps (e.g. by screen printing or electroplating). Only a different layout configuration is required. Here, too, the wafer and carrier are connected (as in c) by mutual adjustment and subsequent soldering process at the wafer level.
  • the use of semiconductor wafers or carrier substrates with solder frames has the particular advantage that a hermetically sealed housing is achieved, which is not possible with adhesives.
  • the aforementioned methods advantageously enable mechanical attachment between the wafer and carrier and the electrical connection of the connection surfaces in a single work step.
  • connection from the front (5) to the rear (6) of the carrier is implemented via plated-through holes (9) which were already produced before the connection to the silicon wafer. These can either directly on the connection surfaces (7, 8)
  • connection surfaces should be distributed over the respective main surfaces in particular in case d) for a more uniform distribution of the mechanical stresses. Since today's ICs almost exclusively have an arrangement of the connections on the edges, these must be redistributed beforehand. In cases a) and b) this can also be achieved on the carrier side, since mechanical stresses are already absorbed by the adhesive.
  • the connection patterns on the two carrier sides can, but do not have to be identical. A certain asymmetry in the connection pattern is advantageous for an unambiguous assignment of the connections or a right-sided use of the carrier, as is indicated, for example, in FIG. 4b.
  • the wafer with the connected carrier substrate is finally separated into chips, so that a package the size of a chip is achieved. This can be done by sawing, as already indicated with the saw cuts (18) in FIGS. 1 to 4.
  • connection surfaces (8) of the carrier are provided on their underside (6) with ⁇ -balls (17).
  • ⁇ -balls are metallic bumps with significantly smaller dimensions than ball grid arrays.
  • a suitable choice of the ⁇ -ball metallization can ensure SMD capability ( ⁇ -ball grid array).
  • the metallization can be carried out, for example, from a Sn / Pb solder (as a solder bump) or from a Cu / Ni / Au alloy (as a hard plug contact).
  • FIG. 5 shows an example of a carrier substrate (4).
  • the carrier can for example consist of materials such as Si, glass, ceramics, printed circuit board materials (eg FR4) or flex materials.
  • the openings for the plated-through holes (9) are first created in the carrier. Depending on the carrier material, this can be done using different methods, such as standard drilling, laser drilling, ultrasonic drilling or etching. In the case of conductive substrates, such as Si, the surfaces and drilling walls must be insulated.
  • the metallizations are carried out in standard processes such as electroless deposition, electroplating, Sputtering, vapor deposition or thick film technology applied. This applies to all parts to be metallized, i.e.
  • the vias should be completely filled. Either the holes are so small that they can be completely filled during the metallization, or they have to be closed subsequently, for example with a synthetic resin drop.
  • the plated-through holes (9) are placed next to the connections (15, 17) on both sides. However, it is also conceivable to place both or one of the two connections (15, 17) on the plated-through holes (9).
  • a multi-layer carrier with an internal wiring level multilayer circuit board or ceramic
  • the finished chip can be covered with a plastic film for mechanical protection if necessary. This can be done either before further assembly at component level, or after assembly similar to a "globe-top" (e.g. synthetic resin drops over the chip) in chip-on-board technology. At the same time, this measure in cases a, b and c provides better protection against moisture penetrating into the joint between the Si chip and the carrier.
  • a plastic film for mechanical protection if necessary. This can be done either before further assembly at component level, or after assembly similar to a "globe-top" (e.g. synthetic resin drops over the chip) in chip-on-board technology.
  • this measure in cases a, b and c provides better protection against moisture penetrating into the joint between the Si chip and the carrier.

Abstract

The invention relates to a method for casing integrated circuits, which makes possible the production of cased integrated circuits (ICs) in chip size packages, and can take place on wafer level. The method is characterized in that, first of all, a finish-processed semi-conducting substrate (1) and a finish-processed carrier substrate (4) are provided. The carrier substrate already has electric connection surfaces on the front and back sides, which are interconnected by means of throughplatings (9). Both substrates are brought together, whereby the mechanical attaching and the electric connection take place in one operational step. Finally, the entire system is separated into individual chips.

Description

VERFAHREN ZUR GEHÄUSUNG VON INTEGRIERTEN SCHALTKREISEN METHOD FOR HOUSING INTEGRATED CIRCUITS
Beschreibungdescription
Die vorliegende Erfindung betrifft ein Verfahren zur Gehäusung von integrierten Schaltkreisen (ICs), das die Herstellung von gehäusten integrierten Schaltkreisen in Chipgröße (Chip Size Package) ermöglicht.The present invention relates to a method for packaging integrated circuits (ICs) which enables the production of packaged integrated circuits in chip size (chip size package).
Integrierte Schaltkreise werden üblicherweise in Keramik- oder Plastikgehäusen auf den Markt gebracht. Dabei stellt sich der Flächenbedarf des Gehäuses im Verhältnis zur Chipgröße sehr ungünstig dar. Daher sind insbesondere bei hochpoligen ICs starke Bestrebungen vorhanden, die Gehäusegröße möglichst auf Chipgröße (Chip Size Package, Abkürzung: CSP) zu reduzieren.Integrated circuits are typically marketed in ceramic or plastic packages. The space requirement of the housing in relation to the chip size is very unfavorable. Therefore, in particular with multi-pole ICs, there are strong efforts to reduce the housing size to the chip size (chip size package, abbreviation: CSP).
Bisher werden in der Regel die fertig prozessierten Siliziumscheiben (Siliziumwafer) vor dem Gehäusen in einem ersten Schritt mit einer Säge in einzelne Chips zerteilt und dann chipweise weiter verarbeitet. Je nach Gehäusungsart unterscheiden sich die weiteren Arbeitsschritte.Up to now, the finished silicon wafers (silicon wafers) have generally been cut into individual chips in a first step using a saw and then further processed on a chip basis. The further work steps differ depending on the type of housing.
Beim Verpressen in Plastikgehäuse (Transfermolden) folgt das Befestigen der Chips auf einem Trägerrahmen (Lead Frame) mit einem Kleber. Die elektrischen Verbindungen vom Chip zum Trägerrahmen werden durch Drahtbonden hergestellt. Anschließend erhalten die Teile in einer Einspritzpresse eine Kunststoffumhüllung. Die letzten Schritte sind das Entgraten, Ausstanzen und Zurechtbiegen der Anschlußbeinchen, sowie das Beschriften.When pressing into plastic housings (transfer molds), the chips are attached to a lead frame with an adhesive. The electrical connections from the chip to the carrier frame are made by wire bonding. The parts are then given a plastic coating in an injection press. The final steps are deburring, punching and bending the connecting legs, as well as labeling.
Bei Verwendung von Keramikgehäusen ist das Gehäuse bereits vorgefertigt. Die Chips werden in einer dafür vorgesehenen Aussparung in der Regel eingeklebt. Die elektrische Kontaktierung erfolgt wiederum durch Drahtbonden. Als letzter Schritt wird ein Gehäusedeckel aufgelötet. Damit ist eine hermetisch dichte Gehäusung erreichtWhen using ceramic housings, the housing is already prefabricated. The chips are usually glued into a recess provided for this purpose. The electrical Contacting is again done by wire bonding. The last step is to solder a housing cover. A hermetically sealed housing is thus achieved
Ein weiteres, hermetisch dichtes Gehäuse stellt das Metallgehäuse dar. Die Arbeitsschritte sind ähnlich dem Verfahren für das Keramikgehäuse. Der Gehäusedeckel wird allerdings beim Metallgehäuse üblicherweise aufgeschweißt.Another, hermetically sealed housing is the metal housing. The working steps are similar to the procedure for the ceramic housing. However, the housing cover is usually welded onto the metal housing.
Aus der WO 96/02071 ist ein Verfahren zur Gehäusung von integrierten Schaltkreisen bekannt, das den Flächenbedarf der Gehäusung annähernd auf Chipgröße reduziert. Bei dem Verfahren wird zunächst ein Siliziumsubstrat mit integrierten Schaltkreisen und Anschlußflächen mit der Vorderseite eines Trägersubstrats verbunden. Nach dem Verbinden werden an der Rückseite des Trägersubstrats Löthöcker angebracht und elektrische Verbindungen zwischen den Löthöckern und den elektrischen Anschlüssen der integrierten Schaltungen durch das Trägersubstrat hindurch hergestellt.From WO 96/02071 a method for housing integrated circuits is known which reduces the area requirement of the housing approximately to chip size. In the method, a silicon substrate with integrated circuits and pads is first connected to the front of a carrier substrate. After the connection, solder bumps are attached to the back of the carrier substrate and electrical connections are made between the solder bumps and the electrical connections of the integrated circuits through the carrier substrate.
Diese Verfahrensweise hat jedoch den Nachteil, daß weitere Verfahrensschritte, wie z.B. eine Phototechnik, nach dem Verbinden von Silizium und Trägersubstrat erforderlich werden, um die elektrischen Verbindungen herzustellen. Dies erhöht die Gefahr von Beschädigungen der ICs und kann daher zu einer geringeren Ausbeute führen.However, this procedure has the disadvantage that further process steps, e.g. a photo technique after which silicon and carrier substrate have to be connected to make the electrical connections. This increases the risk of damage to the ICs and can therefore lead to a lower yield.
Aus US-A-5,535,101 ist ein Verfahren zum Verbinden eines einzelnen Chips mit einem Träger bekannt. Dabei ist der Träger vorzugsweise größer als der Chip. Auch bei dem aus US-A-5,578,874 bekannten Verfahren zum Verbinden eines einzelnen Chips mit einem Träger ist der Träger wesentlich größer als der Chip. Bei beiden verfahren wird also keine full- wafer-Verbindungstechnik angewendet.From US-A-5,535,101 a method for connecting a single chip to a carrier is known. The carrier is preferably larger than the chip. In the method known from US-A-5,578,874 for connecting an individual chip to a carrier, the carrier is also substantially larger than the chip. No full-wafer connection technology is therefore used in either method.
Ausgehend von dem genannten Stand der Technik liegt der Erfindung die Aufgabe zugrunde, ein Verfahren zur Gehäusung von ICs in Chipgröße bereitzustellen, das ohne die Gefahr einer Ausbeutereduzierung durchgeführt werden kann.Based on the prior art mentioned, the invention has for its object to provide a method for packaging ICs in chip size, which can be carried out without the risk of a reduction in yield.
Die Aufgabe wird erfindungsgemäß mit dem Verfahren nach Anspruch 1 gelöst. Vorteilhafte Ausgestaltungen des Verfahrens sind Gegenstand der Unteransprüche.The object is achieved with the method according to claim 1. Advantageous embodiments of the method are the subject of the dependent claims.
Die vorliegende Erfindung betrifft nunmehr ein Verfahren zur Gehäusung von integrierten Schaltkreisen mit den folgenden Verfahrensschritten:The present invention now relates to a method for housing integrated circuits with the following method steps:
- Bereitstellen eines Halbleiter-Wafers mit einer Vielzahl von integrierten Schaltkreisen, der auf einer vorderseitigen Hauptfläche elektrische Anschlußflächen aufweist, sowie; - Bereitstellen eines Trägersubstrats mit einer vorder- und einer rückseitigen Hauptfläche die elektrische Anschlußflächen aufweisen, wobei elektrische Anschlußflächen der vorderseitigen Hauptfläche mit elektrischen Anschlußflächen der rückseitigen Hauptfläche, über Durchkontaktierung elektrisch leitend verbunden sind;- Providing a semiconductor wafer with a plurality of integrated circuits, which has electrical connection areas on a front main surface, and; - Providing a carrier substrate with a front and a rear main surface having the electrical connection surfaces, electrical connection surfaces of the front main surface being electrically conductively connected to electrical connection surfaces of the rear main surface via vias;
- Justieren der vorderseitigen Hauptfläche des ganzen Halbleiter-Wafers zur vorderseitigen Hauptfläche des Trägersubstrats, so daß sich zu verbindende Anschlußflächen gegenüberliegen;- Adjusting the front main surface of the entire semiconductor wafer to the front main surface of the carrier substrate so that the connection surfaces to be connected face each other;
- Verbinden der beiden vorderseitigen Hauptflächen, so daß gleichzeitig eine mechanische Verbindung zwischen Halbleiter-Wafer und Trägersubstrat und eine elektrisch leitende Verbindung zwischen den zu verbindenden Anschlußflächen vorliegt;- Connecting the two front-side main surfaces, so that at the same time there is a mechanical connection between the semiconductor wafer and the carrier substrate and an electrically conductive connection between the connection surfaces to be connected;
- Vereinzeln des mit dem Trägersubstrat verbundenen Halbleiter-Wafers ingehäuste Chips.- Separating the semiconductor wafer connected to the carrier substrate into packaged chips.
Beim erfindungsgemäßen Verfahren wird zunächst ein fertigprozessiertes Halbleitersubstrat mit einem oder mehreren integrierten Schaltkreisen bereitgestellt. Dieses Halbleitersubstrat weist auf einer vorderseitigen Hauptfläche elektrische Anschlußflächen auf. Als vorderseitige Hauptfläche ist die Seite des Halbleitersubstrates zu verstehen, auf der sich die integrierten Schaltkreise befinden. Des weiteren wird ein Trägersubstrat bereitgestellt, das auf seiner vorder- und seiner rückseitigen Hauptfläche elektrische Anschlußflächen aufweist. Die elektrischen Anschlußflächen der Vorderseite sind mit den elektrischen Anschlußflächen der Rückseite bereits über Durchkontaktierungen elektrisch leitend verbunden. Mit Durchkontaktierungen wird vorliegend jede Art von elektrisch leitender Verbindung durch das Trägersubstrat hindurch bezeichnet. Die Durchkontaktierungen können daher direkt oder indirekt, z.B. über Metallisierungsebenen im Trägersubstrat, erfolgen. Die beiden bereitgestellten Substrate, Halbleitersubstrat und Trägersubstrat, werden schließlich mit ihrer jeweiligen vorderseitigen Hauptfläche so zueinander justiert, daß sich die Anschlußflächen gegenüberliegen, die miteinander verbunden werden müssen. Die vorderseitigen Anschluß- flächen des Halbleitersubstrates und des Trägersubstrates werden daher in der Regel spiegelbildlich zueinander passen. Nach der Justierung werden die beiden vorderseitigen Hauptflächen miteinander verbunden, sodaß sowohl eine mechanische Verbindung zwischen Halbleitersubstrat und Trägersubstrat, als auch eine elektrisch leitende Verbindung zwischen den aufeinander justierten Anschlußflächen vorliegt.In the method according to the invention, a completely processed semiconductor substrate with one or more integrated circuits is initially provided. This semiconductor substrate has electrical connection surfaces on a front main surface. The main surface on the front side is to be understood as the side of the semiconductor substrate on which the integrated circuits are located. Furthermore, a carrier substrate is provided which has electrical connection surfaces on its front and rear main surface. The electrical connection surfaces on the front side are already electrically conductively connected to the electrical connection surfaces on the rear side via vias. Vias refer to any type of electrically conductive connection through the carrier substrate. The vias can therefore be direct or indirect, e.g. over metallization levels in the carrier substrate. The two substrates provided, the semiconductor substrate and the carrier substrate, are finally adjusted with respect to one another with their respective front-side main surface in such a way that the connection surfaces which have to be connected lie opposite one another. The front connection surfaces of the semiconductor substrate and of the carrier substrate will therefore generally match each other in mirror image. After the adjustment, the two main surfaces on the front are connected to one another, so that there is both a mechanical connection between the semiconductor substrate and the carrier substrate, and also an electrically conductive connection between the mutually aligned connection surfaces.
Mit dem erfindungsgemäßen Verfahren läßt sich eine Gehäusegröße realisieren, die gleich der Chipgröße ist. Da die Verbindung von Haibleitersubstrat und Trägersubstrat erfolgt, nachdem beide Substrate unabhängig voneinander fertigprozessiert wurden, sind keine weiteren Prozeßschritte nach der Verbindung mehr notwendig, die die Ausbeute reduzieren könnten. Die Verbindung zwischen Halbleitersubstrat und Trägersubstrat, d.h. die mechanische Befestigung und die elektrische Verbindung, kann zudem, wie weiter unten beschrieben wird, in einem einzigen Arbeitsschritt erfolgen.With the method according to the invention, a housing size can be realized which is equal to the chip size. Since the semiconductor substrate and carrier substrate are connected, after both substrates have been processed independently of one another, no further process steps after the connection are necessary, which could reduce the yield. The connection between the semiconductor substrate and the carrier substrate, that is to say the mechanical fastening and the electrical connection, can moreover take place in a single work step, as will be described below.
Das Verfahren kann weiterhin in vorteilhafter Weise auf Waferebene durchgeführt werden. Da im Waferverbund gleichzeitig eine Vielzahl von Chips gehaust und die Prozeßschritte vereinfacht werden können, ermöglicht dies eine drastische Kostensenkung. Nach Durchführung des erfindungsgemäßen Verfahrens liegen somit fertig gehäuste Bauelemente vor.The method can also be carried out advantageously at the wafer level. Since a large number of chips can be housed in the wafer network and the process steps can be simplified, this enables a drastic reduction in costs. After the method according to the invention has been carried out, there are thus finished housed components.
Das Verfahren kann mit einem Halbleitersubstrat durchgeführt werden, dessen elektrische Anschlußflächen auf aktive Bereiche gelegt wurden, so daß eine weitere Flächeneinsparung (d.h. mehr ICs pro Wafer) und damit Kostenreduzierung erreicht wird. Als weiterer Vorteil stellt sich dar, daß aufgrund der Freiheiten bei der Herstellung des Trägersubstrats unterschiedliche Anschlußraster und Anschlußbelegungen auf Vorder- und Rückseite des Trägersubstrates realisierbar sind.The method can be carried out with a semiconductor substrate, the electrical connection areas of which have been placed on active areas, so that a further area saving (i.e. more ICs per wafer) and thus cost reduction is achieved. Another advantage is that, due to the freedom in the manufacture of the carrier substrate, different connection grids and pin assignments can be realized on the front and rear of the carrier substrate.
Das erfindungsgemäße Verfahren wird im folgenden anhand von Ausführungsbeispielen und den Zeichnungen näher erläutert.The method according to the invention is explained in more detail below on the basis of exemplary embodiments and the drawings.
Dabei zeigen schematisch:The following schematically show:
Figur 1 : ein Beispiel für die Seitenansicht einer nach dem erfindungsgemäßen Verfahren hergestellten Einheit aus Halbleiterwafer und Trägersubstrat;FIG. 1: an example of the side view of a unit made from the semiconductor wafer and carrier substrate produced by the method according to the invention;
Figur 2: die Seitenansicht eines Bereichs einer Einheit gemäß Figur 1, bei derFigure 2: the side view of a portion of a unit according to Figure 1, in which
Halbleiterwafer und Trägersubstrat über beidseitige metallische Höcker und einen nichtleitenden Kleber verbunden sind;Semiconductor wafers and carrier substrates are connected via double-sided metallic bumps and a non-conductive adhesive;
Figur 3: die Seitenansicht eines Bereichs einer Einheit gemäß Figur 1, bei der Halbleiterwafer und Trägersubstrat durch einen anisotropen Kleber miteinander verbunden sind;3 shows the side view of a region of a unit according to FIG. 1, in which the semiconductor wafer and carrier substrate are connected to one another by an anisotropic adhesive;
Figur 4a: die Seitenansicht eines Bereichs einer Einheit gemäß Figur 1, bei derFigure 4a: the side view of a portion of a unit according to Figure 1, in which
Halbleiterwafer und Trägersubstrat über Löthöcker und Lötrahmen verbunden sind; Figur 4b: eine Draufsicht auf einen vereinzelten Chip aus Figur 4a;Semiconductor wafers and carrier substrates are connected via solder bumps and solder frames; FIG. 4b: a top view of an isolated chip from FIG. 4a;
Figur 5: ein Beispiel für die Seitenansicht eines Bereichs eines Trägersubstrats, wie es im erfindungsgemäßen Verfahren eingesetzt wird.FIG. 5: an example of the side view of a region of a carrier substrate, as is used in the method according to the invention.
In den folgenden Ausführungsbeispielen wird als Halbleitersubstrat (1) ein Siliziumwafer eingesetzt. Die weiteren Verfahrensschritte werden auf Waferebene durchgeführt. Nach Beendigung der halbleiterspezifischen Verfahrensschritte (Fertigstellung der integrierten Schaltungen und der Metallisierung des Halbleiterwafers, Fertigstellung der Metallisierung des Trägersubstrats, usw.) erfolgt über ein Verbindungsmittel eine ganzflächige Verbindung vom Wafer (1) mit dem Träger (4). Dies ist in Figur 1 gezeigt. Hierbei werden die vorderseitige Hauptfläche (2) des Halbleiterwafers (1) und die vorderseitige Hauptfläche (5) des Trägersubstrates (4) mit den jeweiligen Anschlußflächen (3, 7), zueinander justiert und miteinander verbunden. Die Anschlußmuster, die durch die Anordnung der elektrischen Anschlußflächen (3, 7) auf den vorderseitigen Hauptflächen (2, 5) gebildet werden, passen spiegelbildlich zueinander. Bei der Verbindung werden gleichzeitig in einem Arbeitsschritt die mechanische Befestigung und die Herstellung der elektrischen Verbindungen vom Wafer zum Träger erreicht. Für die Gestaltung des Verbindungsmittels bieten sich die folgenden Möglichkeiten.In the following exemplary embodiments, a silicon wafer is used as the semiconductor substrate (1). The further process steps are carried out at the wafer level. After completion of the semiconductor-specific process steps (completion of the integrated circuits and the metallization of the semiconductor wafer, completion of the metallization of the carrier substrate, etc.), a connection of the entire surface of the wafer (1) to the carrier (4) is carried out. This is shown in Figure 1. The front main surface (2) of the semiconductor wafer (1) and the front main surface (5) of the carrier substrate (4) with the respective connection surfaces (3, 7) are adjusted to one another and connected to one another. The connection patterns which are formed by the arrangement of the electrical connection surfaces (3, 7) on the front main surfaces (2, 5) match each other in mirror image. During the connection, the mechanical fastening and the production of the electrical connections from the wafer to the carrier are achieved simultaneously in one work step. The following options are available for the design of the connecting means.
a) Wie in Figur 2 dargestellt, sind sowohl auf Wafer- (2) als auch auf Trägerseite (5) die elektrischen Anschlußflächen (Trägermetallisierung 7, Chipmetallisierung 3) durch elektrisch leitfähige, in der Regel metallische Höcker (Bumps 11) verstärkt. Ein elektrisch nichtleitender Kleber (12) wird ganzflächig (z.B. durch Auf schleudern odera) As shown in Figure 2, both on the wafer (2) and on the carrier side (5) the electrical connection surfaces (carrier metallization 7, chip metallization 3) are reinforced by electrically conductive, usually metallic bumps (bumps 11). An electrically non-conductive adhesive (12) is applied to the entire surface (e.g. by spinning or
Siebdrucken) auf einen oder beide Fügepartner aufgetragen. Anschließend werden Wafer und Träger zueinander justiert und unter Einwirkung von Druck und Temperatur so miteinander verklebt, daß zwischen den entsprechenden Bumps (11) von Wafer und Träger ein fixierter Druckkontakt entsteht.Screen printing) on one or both joining partners. The wafer and carrier are then adjusted to one another and bonded to one another under the action of pressure and temperature such that a fixed pressure contact is formed between the corresponding bumps (11) of the wafer and carrier.
b) Bei einer weiteren Gestaltungsmöglichkeit gemäß Figur 3 wird zur Verbindung ein anisotrop leitfähiger Kleber (13) verwendet. Anisotrop leitfähige Kleber sind mit Metall oder metallisierten Kunststoffkugeln so gefüllt, daß beim Kleben unter Druck nur in der Richtung senkrecht zur Fügefläche eine elektrisch leitfähige Verbindung (14) entsteht. Auch dieser Kleber wird ganzflächig auf einen oder beide Fügepartner aufgetragen. Neben den unter a) genannten Verfahren kann dies auch in Form einer auflaminiertenb) In a further design option according to FIG. 3, an anisotropically conductive adhesive (13) is used for the connection. Anisotropically conductive adhesives are filled with metal or metallized plastic balls in such a way that an electrically conductive connection (14) is formed only under pressure in the direction perpendicular to the joint surface. This adhesive is also applied over the entire surface to one or both joining partners. In addition to the methods mentioned under a), this can also be in the form of a laminated on
Klebefolie geschehen. Anschließend werden Wafer und Träger zueinander justiert und unter Einwirkung von Druck und Temperatur miteinander verklebt. Auch in diesem Fall können zusätzlich ein- oder beidseitig Bumps (11) auf den Anschlußflächen (3, 7) vorhanden sein.Adhesive film happen. Then the wafer and carrier are adjusted to each other and glued together under the influence of pressure and temperature. Also in this In addition, bumps (11) can be present on the connection surfaces (3, 7) on one or both sides.
c) Zur Verbindung von Wafer und Träger können auch die aus der Flip Chip Technik bekannten Verfahren zur Herstellung von Lötbumps und dazu passender Metallisierungen verwendet werden. Die Justierung und der Lötprozeß erfolgen hier ebenfalls auf Waferebene. Um beim anschließenden Vereinzeln zu Chips, das in derc) The methods known from flip chip technology for producing solder bumps and matching metallizations can also be used to connect the wafer and carrier. The adjustment and the soldering process also take place here at the wafer level. In order to separate the chips in the
Regel auf der Säge erfolgt, das Eindringen von Wasser oder Sägestaub zwischen Chip und Träger zu verhindern, ist eine Unterfüllung auf Kunststoffbasis (underfill) vorzusehen. Hierbei wird auf Waferebene beispielsweise ein sehr dünnflüssiges Epoxidharz verwendet, der durch Kapillarkräfte in die Zwischenräume zwischen Wafer und Träger gezogen wird. Diese Unterfüllung dient weiterhin dem Ausgleich von mechanischen Spannungen zwischen Wafer und Träger. Solche Spannungen entstehen insbesondere bei Verwendung von Trägermaterialien, die nicht an den thermischen Ausdehnungskoeffizienten des Siliziumwafers angepaßt sind (z.B. Leiterplatten oder Flexmaterialien).As a rule on the saw, to prevent water or saw dust from entering between the chip and carrier, an underfill on a plastic basis (underfill) must be provided. Here, for example, a very thin epoxy resin is used at the wafer level, which is drawn into the spaces between the wafer and the carrier by capillary forces. This underfilling also serves to compensate for mechanical stresses between the wafer and the carrier. Such stresses arise in particular when using carrier materials that are not adapted to the thermal expansion coefficient of the silicon wafer (e.g. printed circuit boards or flex materials).
d) Eine weitere, sehr vorteilhafte Gestaltung des Verbindungsmittels ist in den Figuren 4a und b dargestellt. Auch hier werden die aus der Flip Chip Technik bekannten Verfahren zur Herstellung von Lötbumps und dazu passender Metallisierungen verwendet. Die Lötbumps (15) können (wie bei c)) auf den Anschlußflächen (3, 7) auf einer oder beiden vorderseitigen Hauptflächen (2, 5) aufgebracht sein. Weiterhin werden Löthöcker (15), die sich nach dem späteren Vereinzeln auf einem gemeinsamen Chip (10) befinden, von einem Lötrahmen (16) umschlossen. Der Lötrahmen hat dabei in etwa die Umrisse des Chips. Die Form kann jedoch variieren, solange der Zweck des Lötrahmens, das Eindringen von Wasser oder Sägestaub zwischen Chip und Träger zu verhindern, erfüllt ist. Figur 4b zeigt eine Draufsicht auf einen vereinzelten Chip (10) mit Löthöckern (15) und Lötrahmen (16). Die Sägeschnitte (18) zum Vereinzeln der Chips (10) aus dem Wafer (1) sind in Figur 4a dargestellt. Die Herstellung der Lötrahmen kann bei der Prozessierung des Trägersubstrates oder des Siliziumwafers im gleichen Verfahrensschritt wie das Aufbringen der Lötbumps (z.B. durch Siebdruck oder Galvanik) erfolgen. Es ist lediglich eine andere Layout-Konfiguration erforderlich. Die Verbindung von Wafer und Träger erfolgt auch hier (wie bei c) durch ge- genseitige Justierung und anschließenden Lötprozeß auf Waferebene.d) A further, very advantageous design of the connecting means is shown in FIGS. 4a and b. The methods known from flip chip technology for producing solder bumps and matching metallizations are also used here. The solder bumps (15) can (as in c)) be applied to the connection surfaces (3, 7) on one or both front main surfaces (2, 5). Furthermore, soldering bumps (15), which are later on a common chip (10) after being separated, are enclosed by a soldering frame (16). The solder frame has roughly the outline of the chip. However, the shape can vary as long as the purpose of the soldering frame to prevent water or saw dust from entering between the chip and the carrier is fulfilled. FIG. 4b shows a top view of an isolated chip (10) with soldering bumps (15) and soldering frame (16). The saw cuts (18) for separating the chips (10) from the wafer (1) are shown in FIG. 4a. The soldering frames can be produced during the processing of the carrier substrate or the silicon wafer in the same process step as the application of the solder bumps (e.g. by screen printing or electroplating). Only a different layout configuration is required. Here, too, the wafer and carrier are connected (as in c) by mutual adjustment and subsequent soldering process at the wafer level.
Die Verwendung von Halbleiterwafem oder Trägersubstraten mit Lötrahmen hat den besonderen Vorteil, daß damit eine hermetisch dichte Gehäusung erreicht wird, wie dies mit Klebstoffen nicht möglich ist. Die vorgenannten Verfahren ermöglichen in vorteilhafter Weise die mechanische Befestigung zwischen Wafer und Träger sowie die elektrische Verbindung der Anschlußflächen in einem einzigen Arbeitsschritt.The use of semiconductor wafers or carrier substrates with solder frames has the particular advantage that a hermetically sealed housing is achieved, which is not possible with adhesives. The aforementioned methods advantageously enable mechanical attachment between the wafer and carrier and the electrical connection of the connection surfaces in a single work step.
Die elektrische Verbindung von der Vorder- (5) zur Rückseite (6) des Trägers ist über Durchkontaktierungen (9), die bereits vor der Verbindung mit dem Siliziumwafer erzeugt wurden, realisiert. Dabei können diese entweder direkt die Anschlu ßflächen (7, 8) aufThe electrical connection from the front (5) to the rear (6) of the carrier is implemented via plated-through holes (9) which were already produced before the connection to the silicon wafer. These can either directly on the connection surfaces (7, 8)
Vorder- und Rückseite verbinden, oder seitlich dazu geringfügig versetzt sein (vgl. z.B. Figur 5). Die Anschlußflächen sollten insbesondere im Fall d) zur gleichmäßigeren Verteilung der mechanischen Spannungen über die jeweiligen Hauptflächen verteilt sein. Da heutige ICs fast ausschließlich eine Anordnung der Anschlüsse an den Rändern haben, müssen diese vorher flächig umverteilt werden. In den Fällen a) und b) kann dies auch auf der Trägerseite realisiert werden, da dort mechanische Spannungen bereits durch den Kleber aufgefangen werden. Die Anschlußmuster auf den beiden Trägerseiten können, müssen jedoch nicht identisch sein. Für eine eindeutige Zuordnung der Anschlüsse bzw. eine seitenrichtige Verwendung des Trägers ist eine gewisse Unsymmetrie im Anschlußmuster von Vorteil, wie dies beipielsweise in Figur 4b angedeutet ist.Connect the front and back or be slightly offset to the side (see e.g. Figure 5). The connection surfaces should be distributed over the respective main surfaces in particular in case d) for a more uniform distribution of the mechanical stresses. Since today's ICs almost exclusively have an arrangement of the connections on the edges, these must be redistributed beforehand. In cases a) and b) this can also be achieved on the carrier side, since mechanical stresses are already absorbed by the adhesive. The connection patterns on the two carrier sides can, but do not have to be identical. A certain asymmetry in the connection pattern is advantageous for an unambiguous assignment of the connections or a right-sided use of the carrier, as is indicated, for example, in FIG. 4b.
Der Wafer mit dem verbundenen Trägersubstrat wird schließlich zu Chips vereinzelt, sodaß eine Gehäusung in Chipgröße erreicht ist. Dies kann durch Sägen erfolgen, wie es bereits mit den Sägeschnitten (18) in den Figuren 1 bis 4 angedeutet ist.The wafer with the connected carrier substrate is finally separated into chips, so that a package the size of a chip is achieved. This can be done by sawing, as already indicated with the saw cuts (18) in FIGS. 1 to 4.
Zur weiteren Befestigung und zum elektrischen Anschluß des fertigen Chips auf einem Systemträger oder zum Einstecken in einen Sockel sind die Anschlußflächen (8) des Trägers auf seiner Unterseite (6) mit μ-balls (17) versehen. Unter μ-balls sind metallische Höcker mit deutlich kleineren Abmessungen als bei Ball Grid Arrays zu verstehen. Durch geeignete Wahl der μ-ball-Metallisierung kann SMD-Fähigkeit sichergestellt werden (μ-ball grid array). Die Metallisierung kann beispielsweise aus einem Sn/Pb-Lot (als Löthöcker) oder aus einer Cu/Ni/Au-Legierung (als harter Steckkontakt) ausgeführt sein.For further fastening and for the electrical connection of the finished chip on a system carrier or for insertion into a base, the connection surfaces (8) of the carrier are provided on their underside (6) with μ-balls (17). Μ-balls are metallic bumps with significantly smaller dimensions than ball grid arrays. A suitable choice of the μ-ball metallization can ensure SMD capability (μ-ball grid array). The metallization can be carried out, for example, from a Sn / Pb solder (as a solder bump) or from a Cu / Ni / Au alloy (as a hard plug contact).
In Figur 5 ist beispielhaft die Ausführung eines Trägersubstrates (4) skizziert. Der Träger kann beispielsweise aus Materialien, wie Si, Glas, Keramik, Leiterplattenmateriaiien (z.B. FR4) oder Flexmaterialien, bestehen. Für die Bereitstellung eines derartigen Trägers werden im Träger zunächst die Öffnungen für die Durchkontaktierungen (9) erzeugt. Dies kann, je nach Trägermaterial, mit unterschiedlichen Verfahren, wie z.B. Standardbohren, Laserbohren, Ultraschallbohren oder Ätzen erfolgen. Im Fall von leitfähigen Trägermaterialien, wie z.B. Si, müssen die Oberflächen und Bohrwandungen isoliert werden. Die Metallisierungen werden in Standardverfahren wie stromlose Abscheidung, Galvanik, Sputtern, Aufdampfen oder Dickschichttechnik aufgebracht. Dies betrifft sämtliche zu metallisierenden Teile, also die Verbindung von den Bumps (15) bzw. μ-balls (17) zu den Durchkontaktierungen (9), die Durchkontaktierungen (9) und die Lötbumps (15) für die Verbindung zum Si-Chip (1) sowie die μ-balls (17) für die Verbindung zum Systemträger. Die Durchkontaktierungen sollten vollständig gefüllt sein. Entweder werden hierzu die Bohrungen so klein gewählt, daß sie bei der Metallisierung vollständig aufgefüllt werden können, oder sie müssen nachträglich, z.B. mit einem Kunstharztropfen, geschlossen werden. Im skizzierten Ausführungsbeispiel sind die Durchkontaktierungen (9) neben den beidseitigen Anschlüssen (15, 17) plaziert. Es ist aber auch denkbar, beide oder einen der beiden Anschlüsse (15, 17) auf die Durchkontaktierungen (9) zu setzen. Des weiteren ist es möglich, bei Verwendung eines mehriagigen Trägers mit einer Innenverdrahtungsebene (Multilayer-Leiterplatte oder Keramik) eine völlige Umverteilung der Chipanschlüsse (15) gegenüber den Außenanschlüssen (17) des Gehäuses vorzunehmen.FIG. 5 shows an example of a carrier substrate (4). The carrier can for example consist of materials such as Si, glass, ceramics, printed circuit board materials (eg FR4) or flex materials. To provide such a carrier, the openings for the plated-through holes (9) are first created in the carrier. Depending on the carrier material, this can be done using different methods, such as standard drilling, laser drilling, ultrasonic drilling or etching. In the case of conductive substrates, such as Si, the surfaces and drilling walls must be insulated. The metallizations are carried out in standard processes such as electroless deposition, electroplating, Sputtering, vapor deposition or thick film technology applied. This applies to all parts to be metallized, i.e. the connection from the bumps (15) or μ-balls (17) to the vias (9), the vias (9) and the solder bumps (15) for the connection to the Si chip ( 1) and the μ-balls (17) for the connection to the system carrier. The vias should be completely filled. Either the holes are so small that they can be completely filled during the metallization, or they have to be closed subsequently, for example with a synthetic resin drop. In the sketched embodiment, the plated-through holes (9) are placed next to the connections (15, 17) on both sides. However, it is also conceivable to place both or one of the two connections (15, 17) on the plated-through holes (9). Furthermore, when using a multi-layer carrier with an internal wiring level (multilayer circuit board or ceramic), it is possible to completely redistribute the chip connections (15) with respect to the external connections (17) of the housing.
Da Silizium ein sprödes Material ist, kann bei Bedarf der fertiggehäuste Chip zum mechanischen Schutz mit einem Kunststoffilm abgedeckt werden. Dies kann entweder vor der weiteren Montage auf Bauteilebene, oder nach der Montage ähnlich einem "globe-top" (z.B. Kunstharztropfen über dem Chip) bei der Chip-on-Board-Technik geschehen. Gleichzeitig wird mit dieser Maßnahme in den Fällen a, b und c ein besserer Schutz vor eindringender Feuchte in die Füge-stelle zwischen Si-Chip und Träger erreicht. Since silicon is a brittle material, the finished chip can be covered with a plastic film for mechanical protection if necessary. This can be done either before further assembly at component level, or after assembly similar to a "globe-top" (e.g. synthetic resin drops over the chip) in chip-on-board technology. At the same time, this measure in cases a, b and c provides better protection against moisture penetrating into the joint between the Si chip and the carrier.

Claims

PATENTANSPRÜCHE PATENT CLAIMS
1. Verfahren zur Gehäusung von integrierten Schaltkreisen mit folgenden Verfahrensschritten:1. Process for packaging integrated circuits with the following process steps:
- Bereitstellen eines Halbleiter-Wafers (1) mit einer Vielzahl von integrierten Schaltkreisen, der auf einer vorderseitigen Hauptfläche (2) elektrische Anschlußflächen (3) aufweist;- Providing a semiconductor wafer (1) with a plurality of integrated circuits, which has electrical connection surfaces (3) on a front main surface (2);
- Bereitstellen eines Trägersubstrates (4) mit einer vorder- (5) und einer rückseitigen Hauptfläche (6), die elektrische Anschlußflächen (7, 8) aufweisen, wobei elektrische- Providing a carrier substrate (4) with a front (5) and a rear main surface (6) which have electrical connection surfaces (7, 8), electrical
Anschlußflächen (7) der vorderseitigen Hauptfläche (5) mit elektrischen Anschlußflächen (8) der rückseitigen Hauptfläche (6) über Durchkontaktierungen (9) elektrisch leitend verbunden sind;Connection surfaces (7) of the front main surface (5) are electrically conductively connected to electrical connection surfaces (8) of the rear main surface (6) via vias (9);
- Justieren der vorderseitigen Hauptfläche (2) des ganzen Halbleiter-Wafers (1) zur vorderseitigen Hauptfläche (5) des Trägersubstrates (4), sodaß sich zu verbindende- Adjusting the front main surface (2) of the entire semiconductor wafer (1) to the front main surface (5) of the carrier substrate (4), so that to be connected
Anschlußflächen (3, 7) gegenüberliegen;Contact surfaces (3, 7) lie opposite one another;
- Verbinden der beiden vorderseitigen Hauptflächen (2, 5), sodaß gleichzeitig eine mechanische Verbindung zwischen Halbleiter- Wafer (1) und Trägersubstrat (4) und eine elektrisch leitende Verbindung zwischen den zu verbindenden Anschlußflächen (3, 7) vorliegt; und- Connecting the two front-side main surfaces (2, 5), so that at the same time there is a mechanical connection between the semiconductor wafer (1) and the carrier substrate (4) and an electrically conductive connection between the connection surfaces (3, 7) to be connected; and
- Vereinzeln des mit dem Trägersubstrat verbundenen Halbleiter-Wafers in gehäuste Chips (10). - Separating the semiconductor wafer connected to the carrier substrate into packaged chips (10).
2. Verfahren nach Anspruch 1 , dadurch gekennzeichnet, daß die elektrischen Anschlußflächen (3, 7) der vorderseitigen Hauptflächen (2, 5) elektrisch leitfähige Höcker (11) aufweisen, und daß das Verbinden der beiden vorderseitigen Hauptflächen folgende Verfahrensschritte beinhaltet: - Aufbringen eines elektrisch nicht leitenden Klebers (12) auf einen oder beide2. The method according to claim 1, characterized in that the electrical connection surfaces (3, 7) of the front main surfaces (2, 5) have electrically conductive bumps (11), and that the connection of the two front main surfaces includes the following method steps: - Application of a electrically non-conductive adhesive (12) on one or both
Hauptflächen (2, 5);Main surfaces (2, 5);
- Zusammenführen der vorderseitigen Hauptflächen (2, 5) unter Anwendung von Druck und Erhöhung der Temperatur, sodaß zwischen den elektrisch leitfähigen Höckern (11) ein fixierter Druckkontakt entsteht.- Merging the front main surfaces (2, 5) using pressure and increasing the temperature, so that a fixed pressure contact is formed between the electrically conductive bumps (11).
3. Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß das Verbinden der beiden vorderseitigen Hauptflächen (2, 5) folgende Verfahrensschritte beinhaltet:3. The method according to claim 1, characterized in that the connection of the two front main surfaces (2, 5) includes the following process steps:
- Aufbringen eines anisotrop leitfähigen Klebers (13) auf einen oder beide vorderseitigen Hauptflächen (2, 5);- Applying an anisotropically conductive adhesive (13) to one or both front main surfaces (2, 5);
- Zusammenführen der vorderseitigen Hauptflächen (2, 5) unter Anwendung von Druck und Erhöhung der Temperatur.- Merging the front main surfaces (2, 5) using pressure and increasing the temperature.
4. Verfahren nach Anspruch 3, dadurch gekennzeichnet, daß das Aufbringen des Klebers (13) durch Auflaminieren einer Klebefolie erfolgt.4. The method according to claim 3, characterized in that the application of the adhesive (13) is carried out by laminating an adhesive film.
5. Verfahren nach Anspruch 3 oder 4, dadurch gekennzeichnet, daß die elektrischen Anschlußflächen (3, 7) der vorderseitigen Hauptfläche (2) des Halbleiterwafers (1) und/oder der vorderseitigen Hauptfläche (5) des Trägersubstrates (4) elektrisch leitfähige Höcker aufweisen.5. The method according to claim 3 or 4, characterized in that the electrical connection surfaces (3, 7) of the front main surface (2) of the semiconductor wafer (1) and / or the front main surface (5) of the carrier substrate (4) have electrically conductive bumps .
6. Verfahren nach Anspruch 1 , dadurch gekennzeichnet, daß die elektrischen Anschlußflächen (3, 7) der vorderseitigen Hauptfläche (2) des Halbleiterwafers (1) und/oder der vorderseitigen Hauptfläche (5) des Trägersubstrates (4) Löthöcker (15) aufweisen, und daß das Verbinden der beiden vorderseitigen6. The method according to claim 1, characterized in that the electrical connection surfaces (3, 7) of the front main surface (2) of the semiconductor wafer (1) and / or the front main surface (5) of the carrier substrate (4) have solder bumps (15), and that connecting the two front
Hauptflächen folgende Verfahrensschritte beinhaltet:Main areas include the following process steps:
- Zusammenführen der vorderseitigen Hauptflächen (2, 5) unter Erhöhung der Temperatur;- Merging the front main surfaces (2, 5) while increasing the Temperature;
- Unterfüllung der Zwischenräume zwischen Halbleitersubstrat (1) und Trägersubstrat (4) mit einem Kunststoffmaterial.- Filling the gaps between the semiconductor substrate (1) and carrier substrate (4) with a plastic material.
7. Verfahren nach Anspruch 1 , dadurch gekennzeichnet, daß die elektrischen Anschlußflächen (3, 7) der vorderseitigen Hauptfläche (2) des7. The method according to claim 1, characterized in that the electrical connection surfaces (3, 7) of the front main surface (2) of the
Halbleitersubstrates (1) und/oder der vorderseitigen Hauptfläche (7) des Trägersubstrates (4) Löthöcker (15) aufweisen, daß Löthöcker (15), die jeweils einem Chip (10) zugeordnet sind, von einem Lötrahmen umschlossen sind, und daß das Verbinden der beiden vorderseitigen Hauptflächen (2, 5) durch Zusammenführen unter Erhöhung der Temperatur erfolgt.Semiconductor substrates (1) and / or the front main surface (7) of the carrier substrate (4) have solder bumps (15) that solder bumps (15), each associated with a chip (10), are enclosed by a solder frame, and that the connection of the two front main surfaces (2, 5) by merging while increasing the temperature.
8. Verfahren nach einem der Ansprüche 1 bis 7, dadurch gekennzeichnet, daß die Anschlußflächen (3, 7, 8) auf dem Halbleitersubstrat (1) und dem Trägersubstrat (4) in Form von Anschlußmustern über die jeweilige gesamte Hauptfläche (2, 5, 6) verteilt sind.8. The method according to any one of claims 1 to 7, characterized in that the connection surfaces (3, 7, 8) on the semiconductor substrate (1) and the carrier substrate (4) in the form of connection patterns over the respective entire main surface (2, 5, 6) are distributed.
9. Verfahren nach Anspruch 8, dadurch gekennzeichnet, daß die Anschlußmuster auf der vorderseitigen (5) und der rückseitigen Hauptfläche (6) des Trägersubstrates seitlich zueinander versetzt sind.9. The method according to claim 8, characterized in that the connection patterns on the front (5) and the rear main surface (6) of the carrier substrate are laterally offset from one another.
10. Verfahren nach Anspruch 8, dadurch gekennzeichnet, daß die Anschlußmuster der vorderseitigen (5) und der rückseitigen Hauptfläche (6) des Trägersubstrates nicht identisch sind.10. The method according to claim 8, characterized in that the connection pattern of the front (5) and the rear main surface (6) of the carrier substrate are not identical.
11. Verfahren nach einem der Ansprüche 8 bis 10, dadurch gekennzeichnet, daß die Anschlußmuster des Trägersubstrates (4) unsymmetrisch aufgebaut sind.11. The method according to any one of claims 8 to 10, characterized in that the connection pattern of the carrier substrate (4) are constructed asymmetrically.
12. Verfahren nach einem der Ansprüche 1 bis 11, dadurch gekennzeichnet, daß das Trägersubstrat (4) zumindest eine Innenverdrahtungsebene aufweist, über die die Durchkontaktierungen (9) erfolgen. 12. The method according to any one of claims 1 to 11, characterized in that the carrier substrate (4) has at least one internal wiring level, via which the plated-through holes (9) take place.
13. Verfahren nach einem der Ansprüche 1 bis 12, dadurch gekennzeichnet, daß die Anschlußflächen (8) auf der rückseitigen Hauptfläche (6) des Trägersubstrates μ- balls (17) tragen.13. The method according to any one of claims 1 to 12, characterized in that the connection surfaces (8) on the rear main surface (6) of the carrier substrate wear μ-balls (17).
14. Verfahren nach Anspruch 13, dadurch gekennzeichnet, daß die μ-balls (17) eine Metallisierung aufweisen, die für die SMD-Technik geeignet ist.14. The method according to claim 13, characterized in that the μ-balls (17) have a metallization which is suitable for the SMD technology.
15. Verfahren nach einem der Ansprüche 1 bis 14, dadurch gekennzeichnet, daß als Halbleitersubstrat (1) ein Si-Substrat eingesetzt wird.15. The method according to any one of claims 1 to 14, characterized in that an Si substrate is used as the semiconductor substrate (1).
16. Verfahren nach einem der Ansprüche 1 bis 15, dadurch gekennzeichnet, daß ein Halbleitersubstrat (1) eingesetzt wird, dessen elektrische Anschlußflächen (3) auf aktive Bereiche gelegt sind.16. The method according to any one of claims 1 to 15, characterized in that a semiconductor substrate (1) is used, the electrical connection surfaces (3) are placed on active areas.
17. Verfahren nach einem der Ansprüche 1 bis 16, dadurch gekennzeichnet, daß als Trägermaterial Si, Glas, Keramik, Leiterplattenmaterialien oder Flexmaterialien eingesetzt werden. 17. The method according to any one of claims 1 to 16, characterized in that Si, glass, ceramic, printed circuit board materials or flex materials are used as carrier material.
PCT/EP1998/000260 1997-01-23 1998-01-19 Method for casing integrated circuits WO1998033211A1 (en)

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