WO1998037584A1 - Solid state power-control device using group iii nitrides - Google Patents

Solid state power-control device using group iii nitrides Download PDF

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Publication number
WO1998037584A1
WO1998037584A1 PCT/US1998/002856 US9802856W WO9837584A1 WO 1998037584 A1 WO1998037584 A1 WO 1998037584A1 US 9802856 W US9802856 W US 9802856W WO 9837584 A1 WO9837584 A1 WO 9837584A1
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layer
doping level
semiconductor device
group iii
conductivity type
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PCT/US1998/002856
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French (fr)
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Krishna Shenai
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The Board Of Trustees Of The University Of Illinois
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Publication of WO1998037584A1 publication Critical patent/WO1998037584A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
    • H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
    • H01L29/66204—Diodes
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Definitions

  • the field of the invention relates to semiconductors and, more particularly, to power-control transistors.
  • Diodes silicon controlled rectifiers (SCRs) and power transistors, such as gate turn-off transistors (GTOs) and insulated gate bipolar transistors (IGBTs) , are generally known in the field of power control.
  • IGBTs are generally known to be high voltage (e.g., 500 volts, or more), high power devices (e.g., 1 kW, or more) that have a great deal of usefulness in a number of fields (e.g., motor controls, rectifiers, etc.) .
  • IGBTs are usually constructed in the form of a 4-layer device similar to a SCR. As is the case with SCRs, once early IGBTs were triggered into a conductive state, the presence of regenerative currents within the IGBT would tend to maintain the IGBT in a conductive state, resulting in a loss of gate control. This condition is generally referred to as "latch-up" . In an effort to improve the usefulness of IGBTs, recent advances have included the creation of punch- through IGBTs having a buffer layer in a drift region, adjacent the collector, which interferes with regenerative currents, thereby reducing the likelihood of latch-up. Where latch-up can be controlled, an IGBT can be created which has the ability of turning off under load.
  • IGBTs and diodes rely on a relatively thick drift region of doped silicon to resist electrical breakdown. With a generally accepted electrical breakdown voltage rating of 10 volt/ ⁇ m within the drift region of silicon, a 1000 volt device generally requires a drift region of the order of 100 ⁇ m . The relatively thick drift region for silicon and high bulk resistance of silicon limits the current handling capacity of devices made of silicon.
  • the relatively thick drift region also provides a significant charge reservoir during conduction and a source of difficulty in charge removal during turn-off.
  • charge carriers e.g., electrons and holes
  • the presence of charge carriers (e.g., electrons and holes) in the drift region is necessary for device conduction.
  • charge carriers e.g., electrons and holes
  • current continues to flow through the drift region and, consequently, through the IGBT.
  • charge depletion gradually occurs during turn-off, a voltage builds up across the IGBT, eventually resulting in turn-off of the device.
  • the power dissipated within the IGBT is determined by the product of current times voltage, according to well-known principles.
  • IGBTs have proven useful in inverters and elsewhere, their use is still limited to applications involving switching rates of less than 100 kHz. At frequencies above 100 kHz, the power dissipated during switching can result in overheating and, ultimately, device failure .
  • Carrier lifetime control refers to the creation of sites within the structure of the IGBT or diode that facilitates the re-combination of electrons and holes. Lifetime control may include the dispersion of an appropriate material (e.g., gold particles) through the silicon lattice of the substrate or irradiation. Irradiation of the substrate purposefully damages the crystal structure in such a way as to facilitate charge recombination. While lifetime control is effective to some degree in increasing the speed of turn-off, lifetime control also has the effect of increasing device resistance.
  • an appropriate material e.g., gold particles
  • an improved semiconductor charge-control device includes a first layer of a Periodic Table Group III nitride (such as GaN ⁇ of a first conductivity type and a first doping level which forms a drift region of the semiconductor charge-control device and a second layer of a second conductivity type and a second doping level, said second layer being disposed on a first side of the first layer.
  • the device also includes a third layer of the Periodic Table Group III nitride of the first conductivity type and a doping level of at least twice the doping level of the first layer, said third layer being disposed on the second side of the first layer.
  • FIG. 1 is a cut-away view of a GaN diode in accordance with an embodiment of the invention
  • FIG. 2 is a cut-away view of a hybrid GaN/SiC diode using a SiC substrate in accordance with an alternate embodiment of the invention
  • FIG. 3 is a cut-away view of the diode of FIG. 2 with an added buffer layer
  • FIG. 4 depicts electrical characteristics of the diode of FIG. 3 for varying layer thicknesses
  • FIG. 5 depicts electrical characteristics of the diode of FIG. 3 for varying doping levels
  • FIG. 6 depicts application ranges for the diodes of
  • FIG. 7 provides comparative I-V data for a GaN 4.5 kV diode of FIGs. 1 and 2 and similar SiC and Si diodes;
  • FIG. 8 provides comparative I-V data for a GaN 10 kV diode of FIGs. 1 and 2 and, a similar SiC diode, and a GaN/SiC diode of the type shown in Fig. 3;
  • FIG. 9 depicts a doping level distribution for a 4.5 kV GaN diode of- FIG. 1 and for SiC;
  • FIG. 10 depicts a doping level distribution for a 10 kV GaN diode such as those shown in of FIGs. 1 and 2, a GaN/SiC diode such as that shown in FIG. 3, and for a SiC diode;
  • FIG. 11 depicts reverse recovery characteristics for a 4.5 kV diode of FIG. 1;
  • FIG. 12 depicts reverse recovery characteristics for a 10 kV diodes of FIGs. 1, 2 and 3;
  • FIG. 13 depicts a MISFET in accordance with an alternate embodiment of the invention;
  • FIG. 14 depicts a hybrid MISFET in accordance with an alternate embodiment of the invention.
  • FIG. 15 depicts the hybrid MISFET of FIG. 14 with an added buffer layer
  • FIG. 16 depicts an IGBT in accordance with an alternate embodiment of the invention.
  • FIG. 17 depicts a hybrid IGBT in accordance with an alternate embodiment of the invention.
  • FIG. 18 depicts the hybrid IGBT of FIG. 17 with an added buffer layer.
  • FIG. 1 depicts a GaN diode under an embodiment of the invention.
  • the operative parts of the power control device e.g., the diode 10 of FIG. 1 are constructed of a material much better suited to adverse environments .
  • Table Group III nitride e.g., GaN
  • GaN Table Group III nitride
  • the use of GaN has been found to provide superior performance in the operation of semiconductor devices. For example, it has been found that the wide bandgap between valence and conduction bands of GaN allows a GaN device to be successfully used up to 600°C. Prior art silicon or GaAs devices cannot be used above 150°C due to the uncontrolled generation of intrinsic carriers.
  • GaN is mechanically and chemically resistant to most environmental conditions.
  • Table I provides a comparison of GaN with silicon and also with silicon-carbide (SiC) . As shown GaN has a breakdown dielectric field strength E M which is more than an order of magnitude higher than Si.
  • the breakdown voltage is much higher for GaN than silicon (or SiC) , it is possible to make the drift region 12 of FIG. 1 much thinner than a comparable silicon device. Further, since the conductance ⁇ A is also much larger for GaN than silicon, an allowable current density can be much higher for GaN than silicon (or SiC) .
  • GaN has a relatively short carrier lifetime.
  • the low lifetime of GaN makes it a somewhat inefficient semiconductor for the construction of bipolar power switching devices since it is somewhat difficult to obtain high-level injection or high conductivity modulation.
  • the GaN diode 10 of FIG. 1 may be fabricated under any of a number of techniques including both diffusion and deposition steps (e.g., metalorganic chemical vapor deposition (MOCVD) , molecular beam epitaxy (MBE) , chemical vapor deposition (CVD) , HVPE, etc.).
  • MOCVD metalorganic chemical vapor deposition
  • MBE molecular beam epitaxy
  • CVD chemical vapor deposition
  • HVPE HVPE
  • an n+ substrate 14 of GaN may be deposed on sapphire (Al 2 0 3 ) using an epitaxial process (e.g., HVPE).
  • N-type dopants may be added as a dopant (e.g., to n+ doping level of lel9/cm-3) during the deposition process.
  • the sapphire may be etched away in later processing steps to leave the structure 14 shown in FIG. 1.
  • n+ substrate 14 of FIG. 1 may also be deposited on sapphire over an intermediate layer of ZnO using HVPE. Even though ZnO is somewhat unstable at high temperatures, the rapid coverage by GaN prevents decomposition of the ZnO. After growing a GaN layer about
  • the sapphire substrate may be removed either chemically or mechanically.
  • the sapphire substrate is removed because of a lattice mismatch in the structure of the GaN and sapphire.
  • Growing the GaN to a greater thickness may result in the accumulation of stress, which may result in cracking during the epitaxial process.
  • a second n-type epitaxial layer 12 is created on top of the first layer 14.
  • the second layer forms a drift region of GaN of a second doping level (e.g., lel6/c ⁇ T 3 ).
  • the residual doping level of the GaN must be carefully controlled. Residual n-type doping in GaN has been recognized to arise from both native defects (nitrogen vacancies and interstitial gallium) and impurities (0 and Si) introduced by the carrier and the active gases. It has been found that the residual doping level can be reduced by carefully regulating the control of the carrier and active gases using the process recipe. The density of native defects can also be reduced by careful attention to the stoichiometry of the gas phase (ratio of partial pressure of NH3 to partial pressure of GaCl, V/III). Within growth conditions necessary for maintaining good surface morphology, the ratio V/III can be used to achieve the lowest residual native defect density.
  • an additional Mg source is added to compensate for a portion of the residual n-type doping. This is at the expense of carrier mobility, but since Mg is one of the shallowest p- type impurity, this decrease is limited. Furthermore, low Mg doping does not introduce deep states. Both carrier mobility and lifetime are strongly dependent upon the crystalline quality (i.e., defect density) of the semiconductor from which the device is fabricated. In wide bandgap materials, the defect density may determine whether carrier transport is due to an insulator-like hopping mechanism or to a more conventional continuous band-like transport mechanism associated with metals and semiconductors .
  • the device 10 may be masked and a p+ anode 16 created by diffusion.
  • the p+ anode 16 may be created by diffusing a p-type material into a selected area to an appropriate doping level (e.g., lel9 cm "3 ) .
  • This p+ region can also be formed by deposition techniques such as MOCVD and MBE .
  • the surface of the device 10 may be masked again and an insulating layer 18 of aluminum-nitrite (AlN) or a dielectric deposited around the p+ diffusion location 16.
  • AlN aluminum-nitrite
  • a metal or suicide connection 20 may then be deposited over the p+ material 16 to form the anode 20 of the diode 10.
  • a metal or suicide cathode 22 may be deposed over the lower surface of the device 10.
  • FIG. 2 shows a diode 20 under another embodiment of the invention.
  • a substrate 34 of silicon- carbide is provided to further enhance the performance of the diode 30.
  • the SiC substrate 34 may be created using known techniques.
  • the GaN drift region 32 may then be epitaxially deposited on the substrate 34 either directly or through the use of interfacial layers as described above. Other interfacial layers such as SiTe may also be worked to obtain an improved lattice match.
  • the SiC substrate 32 may be thermally etched and additional SiC layers may be epitaxially deposited to improve the surface roughness prior to heteroepitaxy of GaN. An interfacial layer of SiTe may then be added to improve lattice matching.
  • control of the interface is also important in terms of reducing the trap density at the interface.
  • Several unique Al and Te precursors may be useful in reducing the trap at the SiC/GaN interface.
  • SiC/SiTe 2 is believed to be the most useful in the epitaxial growth of GaN.
  • a GaN epilayer covalently bonded to the uppermost Te atomic layer of the substrate 34 is then able to grow with its natural lattice constant. This is believed to be due to the graphite-like structure between any adjacent pair of Te atomic layers resulting in relatively weak Van der Waals bonding between them.
  • the lattice mismatch between GaN and Si is full compensated for by the sliding of one Te layer relative to another.
  • In situ photoemission measurements have been found to be useful in studying the band offset at the interface.
  • the GaN layer provides high electrical conductivity, high avalanche field strength, and superior optical characteristics.
  • the n-type SiC layer can be used either as a buffer layer (thin layer) 26, as in FIG. 3, to control the injection efficiency and carrier recombination or to also support the electric field and provide low electrical resistance in the high-level injection regime when sufficiently thick.
  • the SiC material further improves the overall thermal performance of this structure.
  • the SiC has a thermal conductivity 3-4 times that of GaN and when combined with GaN functions to lower an overall operating temperature of the GaN.
  • the buffer layer 26 may also be subject to certain additional steps to facilitate recombination. Lifetime control may include a dispersion of an appropriate material (e.g., gold particles) within the buffer region 26. Irradiation of the buffer layer 26 may be used to facilitate recombination by purposely damaging the structure of the region 26.
  • FIG. 4 shows the relationship of specific on-state resistance to diode breakdown voltage V BD . Also plotted is the fractional voltage that may be supported by a thin GaN layer.
  • FIG. 5 illustrates how the doping of the SiC layer may be changed to support the required voltage and also the GaN layer thickness.
  • FIG. 6 shows the ratio of on-state resistance R 0N of a hybrid GaN/SiC diode 30 to that of the SiC diode with identical voltage ratings. Also illustrated is a range of V BD that can be achieved with a GaN/SiC device 30 with at least 50% lower resistance R 0N compared to a diode of SiC alone, based on a GaN doping density of lxl0 16 cm "3 .
  • FIG. 7 shows forward voltage drop of the GaN diode 10 of FIG. 1 compared to a Si diode and a SiC diode. As shown, the 4.5 kV GaN diode 10 provides a dramatic forward voltage drop reduction over Si and SiC.
  • FIG. 8 shows forward voltage drop for a 10 kV diode of FIGs. 1-3.
  • FIGs. 9 and 10 show carrier concentrations for the 4.5 and 10 kV diodes, respectively .
  • Table I indicates that a net carrier lifetime ⁇ of GaN is three orders of magnitude lower than silicon.
  • the effect of the faster carrier lifetime can be seen in the turn-off time of the 4.5 kV diodes in FIG. 11.
  • the turn-off times of the 10 kV diodes can be seen in FIG. 12.
  • Table II shows electrical loss for a 4.5 kV diode. As shown SiC has a lower turn-on loss than GaN, but a higher total loss . This is because although SiC has a lower reverse current peak than Si, it has a much longer current tail. This shows up as a large turn-off loss.
  • Table III is a compilation of losses for a 10 kV diode. As should be * noted, even though GaN has a lower overall loss, it still has a higher conduction loss than the hybrid of GaN and SiC.
  • GaN has higher carrier mobility and breakdown field strength than SiC. However, it has poor thermal conductivity. Moreover, the lowest achievable doping presently available for GaN is in the range of lel ⁇ cm "3 , which corresponds to a breakdown voltage of 4.5 kV.
  • the hybrid device 30 exploits the superior properties of both GaN and SiC devices . In order to achieve higher breakdown voltage levels, SiC of appropriate doping and thickness is placed underneath a GaN layer . GaN leads to improved switching performance of the device, while SiC accounts for the required breakdown voltage and heat dissipation. Static and switching performance of the 10 kV hybrid device 30 is shown in FIGs. 8, 10 and 12 and can be compared with static and switching performance of 4.5 kV devices 10 in FIGs. 7, 9 and 11.
  • the hybrid device 30 shows a kink in its forward I-V characteristics (FIG. 10) which has no influence on its performance. This kink is attributed to the delay in the onset of high-level injection in the drift region due to noticeable differences in carrier lifetime and mobility across the heterojunction. Table III shows the energy losses associated with switching of the hybrid device 30. The hybrid device 30, thus, achieves a compromise between the low switching losses of GaN and high thermal conductivity of SiC.
  • FIG. 13 depicts a metal insulated semiconductor field effect transistor (MISFET) 50 constructed in accordance with another embodiment of the invention.
  • MISFET metal insulated semiconductor field effect transistor
  • the n+ type substrate 54 of GaN and n-type drift region 52 are fabricated using an epitaxial process described above for the diode 10 with doping levels of 2el6 and lel ⁇ cm "3 , respectively.
  • the p-type layer 56 may also be fabricated using an epitaxial process.
  • the doping level of the p-type layer would be on the level of lel7 cm "3 .
  • the MISFET 50 is completed using mainly a combination of etching and diffusion steps.
  • the p-type layer 56 is masked •and etched to expose the region over the n+ type 58.
  • a - material may be implanted over the exposed area .
  • the material may then be heated to diffuse the n material into the base creating the n+ area 58 with a doping level of approximately lel9 cm "3 .
  • the surface may again be masked and exposed in the area over the trench. Once exposed, the trench may be etched to the proper depth. The surface may again be masked to expose the area surrounding the trench.
  • the AlN insulating layer ⁇ O may then be laid down over the exposed area using sputtering or an epitaxial process . Once more, the area may be masked to create the gate 62 and external- connections to the gate 62.
  • the trench may then be refilled with polysilicon or amorphous silicon.
  • the trench refill step may also be performed using an epitaxial deposition of alternate materials.
  • a dielectric 64 (e.g., AlN) may be laid down over the area again using an epitaxial process. The process may be completed by laying down a metal layer 66, 68 to create the source and drain connections.
  • a n+ type SiC substrate 78 is used as shown in FIG. 14 to control injection efficiency and improve heat transfer.
  • the substrate 78 and drift region may be created as described for the diode 30 of FIG. 2.
  • the channel region 76 and n+ region 88, insulator 80 and gate 82 may be laid down as described for the MISFET of FIG. 13.
  • the n+ type SiC substrate 78 would be expected to have a doping level of lel9 cm “3 .
  • the n-type GaN drift region 72 would have a doping level of lel ⁇ cm "3 .
  • the p-type GaN channel region 76 would have a doping level of lel7 cm “3 .
  • the n+ type GaN region 88 would have a doping level of lel9 cm “3 .
  • a n-type SiC buffer region 93 is provided in the MISFET 90 of FIG. 15 to further improve injection efficiency and improve the reverse recovery of the parasitic pn junction diode.
  • the device 90 would be fabricated substantially the same as the device 70 of FIG. 14, but with the addition of an extra step of growing the buffer layer 93.
  • the buffer layer 93 would be grown epitaxially or by CVD and would be expected to have a doping level of 2el7 cm "3 .
  • an IGBT 120 (FIG. 16) is provided using GaN as a charge control material.
  • the IGBT 120 may be fabricated as described for FIG. 13.
  • One exception, however, is that the substrate 124 becomes a p+ layer 124 instead of the n+ layer 54 described in FIG. 13.
  • an IGBT 140 is provided with a GaN drift region 142 on a SiC substrate 144.
  • the device 140 may be fabricated using the process described in conjunction with FIG. 14, with the exception of substituting a p+ substrate 144 as a starting material.
  • an IGBT 160 is provided with a GaN drift region 62, a buffer layer 164 fabricated on a SiC substrate 165.
  • the device 160 may be fabricated using the process described in conjunction with FIG. 15, with the exception of substituting a p+ substrate 168 as a starting material .
  • the MISFETs 50, 70, 90 of FIGs. 13, 14, 15 and IGBTs 120, 140 and 160 of FIGs. 16, 17, 18 have exposed channel regions 56, 76, 96, 126, 146 and 166 for optical triggering. While it is anticipated that any bright photon source would trigger the devices, it is anticipated that the devices would be especially susceptible to laser triggering. Such a device would be especially useful in high voltage applications

Abstract

A semiconductor charge-control device (10) is provided. The device includes a first layer (12) of a Periodic Table Group III nitride of a first conductivity type and a first doping level which forms a drift region of the semiconductor charge-control device and a second layer (16) of the Periodic Table Group III nitride of a second conductivity type and a second doping level at least one order of magnitude above the first doping level, said second layer being disposed on a first side of the first layer. The device also includes a third layer (14) of the Periodic Table Group III nitride of the first conductivity tye and a doping level of at least twice the doping level of the first layer, said third layer being disposed on the second side of the first layer.

Description

SOLID STATE POWER-CONTROL DEVICE USING GROUP III NITRIDES
Field of the Invention The field of the invention relates to semiconductors and, more particularly, to power-control transistors.
Background of the Invention
Diodes, silicon controlled rectifiers (SCRs) and power transistors, such as gate turn-off transistors (GTOs) and insulated gate bipolar transistors (IGBTs) , are generally known in the field of power control. IGBTs are generally known to be high voltage (e.g., 500 volts, or more), high power devices (e.g., 1 kW, or more) that have a great deal of usefulness in a number of fields (e.g., motor controls, rectifiers, etc.) .
IGBTs are usually constructed in the form of a 4-layer device similar to a SCR. As is the case with SCRs, once early IGBTs were triggered into a conductive state, the presence of regenerative currents within the IGBT would tend to maintain the IGBT in a conductive state, resulting in a loss of gate control. This condition is generally referred to as "latch-up" . In an effort to improve the usefulness of IGBTs, recent advances have included the creation of punch- through IGBTs having a buffer layer in a drift region, adjacent the collector, which interferes with regenerative currents, thereby reducing the likelihood of latch-up. Where latch-up can be controlled, an IGBT can be created which has the ability of turning off under load. The ability to turn off under load makes an IGBT much more useful as a power control unit in such devices as inverters or power controllers . While latch-up can generally be controlled, one of the remaining difficulties with the use of IGBTs is the inefficiencies of IGBTs associated with their slow turn-off times and internal resistance. IGBTs and diodes rely on a relatively thick drift region of doped silicon to resist electrical breakdown. With a generally accepted electrical breakdown voltage rating of 10 volt/μm within the drift region of silicon, a 1000 volt device generally requires a drift region of the order of 100 μm . The relatively thick drift region for silicon and high bulk resistance of silicon limits the current handling capacity of devices made of silicon. The relatively thick drift region also provides a significant charge reservoir during conduction and a source of difficulty in charge removal during turn-off. The presence of charge carriers (e.g., electrons and holes) in the drift region is necessary for device conduction. When charge remains in the drift region after removal of control voltage from an IGBT gate connection, current continues to flow through the drift region and, consequently, through the IGBT. As charge depletion gradually occurs during turn-off, a voltage builds up across the IGBT, eventually resulting in turn-off of the device. During turn-off, the power dissipated within the IGBT is determined by the product of current times voltage, according to well-known principles.
While IGBTs have proven useful in inverters and elsewhere, their use is still limited to applications involving switching rates of less than 100 kHz. At frequencies above 100 kHz, the power dissipated during switching can result in overheating and, ultimately, device failure .
Efforts to improve device turn-off times have included the use of carrier lifetime control within the drift region. Carrier lifetime control, as that term is used in the art, refers to the creation of sites within the structure of the IGBT or diode that facilitates the re-combination of electrons and holes. Lifetime control may include the dispersion of an appropriate material (e.g., gold particles) through the silicon lattice of the substrate or irradiation. Irradiation of the substrate purposefully damages the crystal structure in such a way as to facilitate charge recombination. While lifetime control is effective to some degree in increasing the speed of turn-off, lifetime control also has the effect of increasing device resistance. Increasing device resistance also causes heat generation and heat build-up within the IGBT or diode during normal current flow. Increasing the lifetime control through metallic dispersions or irradiation, while allowing for an increase in maximum switching speeds, results in a trade-off which can cause an overall decrease in device efficiency.
Accordingly, it is an object of the invention to provide a semiconductor structure with improved breakdown strength, reduced electrical and heat flow resistance and faster turn-off times.
It is a further object of the invention to provide a mechanism for rapid charge depletion within the drift region after turn-off of the device that does not result in an overall increase in device resistance.
It is a further object of the invention to provide a structure for IGBTs that is applicable for punch through IGBTs and non-punch through IGBTs .
Summary In one embodiment of the invention, an improved semiconductor charge-control device is provided. The device includes a first layer of a Periodic Table Group III nitride (such as GaN} of a first conductivity type and a first doping level which forms a drift region of the semiconductor charge-control device and a second layer of a second conductivity type and a second doping level, said second layer being disposed on a first side of the first layer. The device also includes a third layer of the Periodic Table Group III nitride of the first conductivity type and a doping level of at least twice the doping level of the first layer, said third layer being disposed on the second side of the first layer.
Brief Description of the Drawings FIG. 1 is a cut-away view of a GaN diode in accordance with an embodiment of the invention;
FIG. 2 is a cut-away view of a hybrid GaN/SiC diode using a SiC substrate in accordance with an alternate embodiment of the invention;
FIG. 3 is a cut-away view of the diode of FIG. 2 with an added buffer layer;
FIG. 4 depicts electrical characteristics of the diode of FIG. 3 for varying layer thicknesses;
FIG. 5 depicts electrical characteristics of the diode of FIG. 3 for varying doping levels; FIG. 6 depicts application ranges for the diodes of
FIGs . 1 and 3 with a minimum Group Ill-nitride doping level of lxlO16 cm"3 ;
FIG. 7 provides comparative I-V data for a GaN 4.5 kV diode of FIGs. 1 and 2 and similar SiC and Si diodes;
FIG. 8 provides comparative I-V data for a GaN 10 kV diode of FIGs. 1 and 2 and, a similar SiC diode, and a GaN/SiC diode of the type shown in Fig. 3; FIG. 9 depicts a doping level distribution for a 4.5 kV GaN diode of- FIG. 1 and for SiC;
FIG. 10 depicts a doping level distribution for a 10 kV GaN diode such as those shown in of FIGs. 1 and 2, a GaN/SiC diode such as that shown in FIG. 3, and for a SiC diode;
FIG. 11 depicts reverse recovery characteristics for a 4.5 kV diode of FIG. 1;
FIG. 12 depicts reverse recovery characteristics for a 10 kV diodes of FIGs. 1, 2 and 3; FIG. 13 depicts a MISFET in accordance with an alternate embodiment of the invention;
FIG. 14 depicts a hybrid MISFET in accordance with an alternate embodiment of the invention;
FIG. 15 depicts the hybrid MISFET of FIG. 14 with an added buffer layer;
FIG. 16 depicts an IGBT in accordance with an alternate embodiment of the invention;
FIG. 17 depicts a hybrid IGBT in accordance with an alternate embodiment of the invention; and FIG. 18 depicts the hybrid IGBT of FIG. 17 with an added buffer layer.
Detailed Description of the Invention FIG. 1 depicts a GaN diode under an embodiment of the invention. Under the embodiment, the operative parts of the power control device (e.g., the diode 10 of FIG. 1) are constructed of a material much better suited to adverse environments .
Under the embodiment, device efficiency and reliability is significantly increased through the use of a Periodic
Table Group III nitride (e.g., GaN) at the charge-control junction. The use of GaN has been found to provide superior performance in the operation of semiconductor devices. For example, it has been found that the wide bandgap between valence and conduction bands of GaN allows a GaN device to be successfully used up to 600°C. Prior art silicon or GaAs devices cannot be used above 150°C due to the uncontrolled generation of intrinsic carriers.
Further silicon and GaAs cannot tolerate chemically hostile environments. In contrast, GaN is mechanically and chemically resistant to most environmental conditions.
Table I provides a comparison of GaN with silicon and also with silicon-carbide (SiC) . As shown GaN has a breakdown dielectric field strength EM which is more than an order of magnitude higher than Si.
Table I
Figure imgf000008_0001
Since the breakdown voltage is much higher for GaN than silicon (or SiC) , it is possible to make the drift region 12 of FIG. 1 much thinner than a comparable silicon device. Further, since the conductance σA is also much larger for GaN than silicon, an allowable current density can be much higher for GaN than silicon (or SiC) .
GaN has a relatively short carrier lifetime. The low lifetime of GaN makes it a somewhat inefficient semiconductor for the construction of bipolar power switching devices since it is somewhat difficult to obtain high-level injection or high conductivity modulation.
However, high carrier mobility and high breakdown field strength (compared to Si or SiC) allows GaN to be a much better switching device than Si or SiC. Further, the method described be'low for creating an electrically transparent GaN/SiC heterojunction allows the benefits of both materials to be available in the same hybrid device. Turning now to FIG. 1, the GaN diode 10 of FIG. 1 may be fabricated under any of a number of techniques including both diffusion and deposition steps (e.g., metalorganic chemical vapor deposition (MOCVD) , molecular beam epitaxy (MBE) , chemical vapor deposition (CVD) , HVPE, etc.). Under one embodiment, an n+ substrate 14 of GaN may be deposed on sapphire (Al203) using an epitaxial process (e.g., HVPE). N-type dopants may be added as a dopant (e.g., to n+ doping level of lel9/cm-3) during the deposition process. The sapphire may be etched away in later processing steps to leave the structure 14 shown in FIG. 1.
Under the embodiment the n+ substrate 14 of FIG. 1 may also be deposited on sapphire over an intermediate layer of ZnO using HVPE. Even though ZnO is somewhat unstable at high temperatures, the rapid coverage by GaN prevents decomposition of the ZnO. After growing a GaN layer about
300 μm thick, the sapphire substrate may be removed either chemically or mechanically.
The sapphire substrate is removed because of a lattice mismatch in the structure of the GaN and sapphire. Growing the GaN to a greater thickness may result in the accumulation of stress, which may result in cracking during the epitaxial process.
Following creation of the substrate 14, a second n-type epitaxial layer 12 is created on top of the first layer 14. The second layer forms a drift region of GaN of a second doping level (e.g., lel6/cπT3).
To achieve a set of desirable characteristics for the GaN drift region 12, it has been found that the residual doping level of the GaN must be carefully controlled. Residual n-type doping in GaN has been recognized to arise from both native defects (nitrogen vacancies and interstitial gallium) and impurities (0 and Si) introduced by the carrier and the active gases. It has been found that the residual doping level can be reduced by carefully regulating the control of the carrier and active gases using the process recipe. The density of native defects can also be reduced by careful attention to the stoichiometry of the gas phase (ratio of partial pressure of NH3 to partial pressure of GaCl, V/III). Within growth conditions necessary for maintaining good surface morphology, the ratio V/III can be used to achieve the lowest residual native defect density. To further reduce the free carrier concentration, an additional Mg source is added to compensate for a portion of the residual n-type doping. This is at the expense of carrier mobility, but since Mg is one of the shallowest p- type impurity, this decrease is limited. Furthermore, low Mg doping does not introduce deep states. Both carrier mobility and lifetime are strongly dependent upon the crystalline quality (i.e., defect density) of the semiconductor from which the device is fabricated. In wide bandgap materials, the defect density may determine whether carrier transport is due to an insulator-like hopping mechanism or to a more conventional continuous band-like transport mechanism associated with metals and semiconductors .
Following creation of the drift region, the device 10 may be masked and a p+ anode 16 created by diffusion. The p+ anode 16 may be created by diffusing a p-type material into a selected area to an appropriate doping level (e.g., lel9 cm"3) . This p+ region can also be formed by deposition techniques such as MOCVD and MBE .
Following deposition of the drift region 12 and p+ anode 16, the surface of the device 10 may be masked again and an insulating layer 18 of aluminum-nitrite (AlN) or a dielectric deposited around the p+ diffusion location 16. A metal or suicide connection 20 may then be deposited over the p+ material 16 to form the anode 20 of the diode 10. As a final step a metal or suicide cathode 22 may be deposed over the lower surface of the device 10.
FIG. 2 shows a diode 20 under another embodiment of the invention. Under the embodiment, a substrate 34 of silicon- carbide is provided to further enhance the performance of the diode 30. The SiC substrate 34 may be created using known techniques. The GaN drift region 32 may then be epitaxially deposited on the substrate 34 either directly or through the use of interfacial layers as described above. Other interfacial layers such as SiTe may also be worked to obtain an improved lattice match. Further, the SiC substrate 32 may be thermally etched and additional SiC layers may be epitaxially deposited to improve the surface roughness prior to heteroepitaxy of GaN. An interfacial layer of SiTe may then be added to improve lattice matching. In addition to lattice matching, control of the interface is also important in terms of reducing the trap density at the interface. Several unique Al and Te precursors may be useful in reducing the trap at the SiC/GaN interface. SiC/SiTe2 is believed to be the most useful in the epitaxial growth of GaN. A GaN epilayer covalently bonded to the uppermost Te atomic layer of the substrate 34 is then able to grow with its natural lattice constant. This is believed to be due to the graphite-like structure between any adjacent pair of Te atomic layers resulting in relatively weak Van der Waals bonding between them. Hence, the lattice mismatch between GaN and Si is full compensated for by the sliding of one Te layer relative to another. In situ photoemission measurements have been found to be useful in studying the band offset at the interface.
The GaN layer provides high electrical conductivity, high avalanche field strength, and superior optical characteristics. The n-type SiC layer can be used either as a buffer layer (thin layer) 26, as in FIG. 3, to control the injection efficiency and carrier recombination or to also support the electric field and provide low electrical resistance in the high-level injection regime when sufficiently thick. The SiC material further improves the overall thermal performance of this structure. The SiC has a thermal conductivity 3-4 times that of GaN and when combined with GaN functions to lower an overall operating temperature of the GaN. Where SiC is used as a buffer layer 26 (FIG. 3) to control carrier recombination, the buffer layer 26 may also be subject to certain additional steps to facilitate recombination. Lifetime control may include a dispersion of an appropriate material (e.g., gold particles) within the buffer region 26. Irradiation of the buffer layer 26 may be used to facilitate recombination by purposely damaging the structure of the region 26.
FIG. 4 shows the relationship of specific on-state resistance to diode breakdown voltage VBD. Also plotted is the fractional voltage that may be supported by a thin GaN layer. FIG. 5 illustrates how the doping of the SiC layer may be changed to support the required voltage and also the GaN layer thickness. FIG. 6 shows the ratio of on-state resistance R0N of a hybrid GaN/SiC diode 30 to that of the SiC diode with identical voltage ratings. Also illustrated is a range of VBD that can be achieved with a GaN/SiC device 30 with at least 50% lower resistance R0N compared to a diode of SiC alone, based on a GaN doping density of lxl016 cm"3.
FIG. 7 shows forward voltage drop of the GaN diode 10 of FIG. 1 compared to a Si diode and a SiC diode. As shown, the 4.5 kV GaN diode 10 provides a dramatic forward voltage drop reduction over Si and SiC. FIG. 8 shows forward voltage drop for a 10 kV diode of FIGs. 1-3. FIGs. 9 and 10 show carrier concentrations for the 4.5 and 10 kV diodes, respectively .
Table I indicates that a net carrier lifetime τ of GaN is three orders of magnitude lower than silicon. The effect of the faster carrier lifetime can be seen in the turn-off time of the 4.5 kV diodes in FIG. 11. The turn-off times of the 10 kV diodes can be seen in FIG. 12.
Table II shows electrical loss for a 4.5 kV diode. As shown SiC has a lower turn-on loss than GaN, but a higher total loss . This is because although SiC has a lower reverse current peak than Si, it has a much longer current tail. This shows up as a large turn-off loss.
TABLE II
Figure imgf000013_0001
Table III is a compilation of losses for a 10 kV diode. As should be* noted, even though GaN has a lower overall loss, it still has a higher conduction loss than the hybrid of GaN and SiC.
TABLE III
Figure imgf000014_0001
GaN has higher carrier mobility and breakdown field strength than SiC. However, it has poor thermal conductivity. Moreover, the lowest achievable doping presently available for GaN is in the range of lelβ cm"3, which corresponds to a breakdown voltage of 4.5 kV. The hybrid device 30 exploits the superior properties of both GaN and SiC devices . In order to achieve higher breakdown voltage levels, SiC of appropriate doping and thickness is placed underneath a GaN layer . GaN leads to improved switching performance of the device, while SiC accounts for the required breakdown voltage and heat dissipation. Static and switching performance of the 10 kV hybrid device 30 is shown in FIGs. 8, 10 and 12 and can be compared with static and switching performance of 4.5 kV devices 10 in FIGs. 7, 9 and 11. The hybrid device 30 shows a kink in its forward I-V characteristics (FIG. 10) which has no influence on its performance. This kink is attributed to the delay in the onset of high-level injection in the drift region due to noticeable differences in carrier lifetime and mobility across the heterojunction. Table III shows the energy losses associated with switching of the hybrid device 30. The hybrid device 30, thus, achieves a compromise between the low switching losses of GaN and high thermal conductivity of SiC.
FIG. 13 depicts a metal insulated semiconductor field effect transistor (MISFET) 50 constructed in accordance with another embodiment of the invention. Under the embodiment, the n+ type substrate 54 of GaN and n-type drift region 52 are fabricated using an epitaxial process described above for the diode 10 with doping levels of 2el6 and lelβ cm"3, respectively.
The p-type layer 56 may also be fabricated using an epitaxial process. The doping level of the p-type layer would be on the level of lel7 cm"3.
Following the creation of the p-type layer 56, the MISFET 50 is completed using mainly a combination of etching and diffusion steps. First, the p-type layer 56 is masked •and etched to expose the region over the n+ type 58. A - material may be implanted over the exposed area . The material may then be heated to diffuse the n material into the base creating the n+ area 58 with a doping level of approximately lel9 cm"3.
Next, the surface may again be masked and exposed in the area over the trench. Once exposed, the trench may be etched to the proper depth. The surface may again be masked to expose the area surrounding the trench. The AlN insulating layer βO may then be laid down over the exposed area using sputtering or an epitaxial process . Once more, the area may be masked to create the gate 62 and external- connections to the gate 62. The trench may then be refilled with polysilicon or amorphous silicon. The trench refill step may also be performed using an epitaxial deposition of alternate materials.
Following the trench refill, the device must again be masked and exposed to reveal a somewhat larger area around the gate 62. A dielectric 64 (e.g., AlN) may be laid down over the area again using an epitaxial process. The process may be completed by laying down a metal layer 66, 68 to create the source and drain connections.
In another embodiment, a n+ type SiC substrate 78 is used as shown in FIG. 14 to control injection efficiency and improve heat transfer. The substrate 78 and drift region may be created as described for the diode 30 of FIG. 2. The channel region 76 and n+ region 88, insulator 80 and gate 82 may be laid down as described for the MISFET of FIG. 13.
The n+ type SiC substrate 78 would be expected to have a doping level of lel9 cm"3. The n-type GaN drift region 72 would have a doping level of lelβ cm"3. The p-type GaN channel region 76 would have a doping level of lel7 cm"3. The n+ type GaN region 88 would have a doping level of lel9 cm"3.
In another embodiment of the invention, a n-type SiC buffer region 93 is provided in the MISFET 90 of FIG. 15 to further improve injection efficiency and improve the reverse recovery of the parasitic pn junction diode. The device 90 would be fabricated substantially the same as the device 70 of FIG. 14, but with the addition of an extra step of growing the buffer layer 93. The buffer layer 93 would be grown epitaxially or by CVD and would be expected to have a doping level of 2el7 cm"3. In another embodiment of the invention, an IGBT 120 (FIG. 16) is provided using GaN as a charge control material. The IGBT 120 may be fabricated as described for FIG. 13. One exception, however, is that the substrate 124 becomes a p+ layer 124 instead of the n+ layer 54 described in FIG. 13.
In another embodiment, an IGBT 140 is provided with a GaN drift region 142 on a SiC substrate 144. The device 140 may be fabricated using the process described in conjunction with FIG. 14, with the exception of substituting a p+ substrate 144 as a starting material.
In another embodiment, an IGBT 160 is provided with a GaN drift region 62, a buffer layer 164 fabricated on a SiC substrate 165. The device 160 may be fabricated using the process described in conjunction with FIG. 15, with the exception of substituting a p+ substrate 168 as a starting material .
In another embodiment of the invention, the MISFETs 50, 70, 90 of FIGs. 13, 14, 15 and IGBTs 120, 140 and 160 of FIGs. 16, 17, 18 have exposed channel regions 56, 76, 96, 126, 146 and 166 for optical triggering. While it is anticipated that any bright photon source would trigger the devices, it is anticipated that the devices would be especially susceptible to laser triggering. Such a device would be especially useful in high voltage applications
(e.g., the power generating industry) where isolation of the gate lead is difficult or impossible.
Specific embodiments of novel apparatus for fabricating high voltage, low-loss semiconductors using Periodic Table Group III nitrides according to the present invention have been described for the purpose of illustrating the manner in which the invention is made and used. It should be understood that the implementation of other variations and modifications of the invention and its various aspects will be apparent -to one skilled in the art, and that the invention is not limited by the specific embodiments described. Therefore, it is contemplated to cover the present invention any and all modifications, variations, or equivalents that fall within the true spirit and scope of the basic underlying principles disclosed and claimed herein.

Claims

CLAIMS 1. A semiconductor charge-control device comprising: a first layer of a Periodic Table Group III nitride of a first conductivity type and a first doping level which forms a drift region of the semiconductor charge-control device; a second layer of the Periodic Table Group III nitride of a second conductivity type and a second doping level at least one order of magnitude above the first doping level said second layer being disposed on a first side of the first layer; and a third layer of the Periodic Table Group III nitride of the first conductivity type and a doping level of at least twice the doping level of the first layer, said third layer being disposed on the second side of the first layer.
2. The semiconductor device as in claim 1 wherein the Periodic Table Group III nitride further comprises gallium nitride.
3. The semiconductor device as in claim 1 wherein the third layer further comprises a device cathode.
4. The semiconductor device as in claim 1 wherein the second layer comprises an anode.
5. The semiconductor device as in claim 1 further comprising a fourth layer of the Periodic Table Group III nitride of the first conductivity type and a doping level at least two orders of magnitude higher than the doping level of the second layer, said fourth layer being disposed over the second layer.
6. The semiconductor device as in claim 1 further comprising a trench gate at least partially disposed over the fourth layer and penetrating the third and fourth layers and at least partially penetrating the first layer.
7. The semiconductor device as in claim 1 further comprising an aluminum nitride layer insulating the trench gate from the first, third and fourth layers.
8. The semiconductor device as in claim 1 further comprising a conductive metallic layer disposed over a portion of the fourth layer.
9. A semiconductor device comprising: a first layer of a Periodic Table Group III nitride of a first conductivity type and a first doping level which forms a drift region of the semiconductor device; a second layer of the Periodic Table Group III nitride of a second conductivity type and a second doping level at least one order of magnitude above the first doping level said second layer being disposed on a first side of the first layer; and a third layer of silicon carbide of the first conductivity type and a different doping level, said third layer being disposed on the second side of the first layer.
10. The semiconductor device as in claim 9 wherein the Periodic Table Group III nitride further comprises gallium nitride.
11. The semiconductor device as in claim 9 wherein the third layer further comprises a device cathode.
12. The semiconductor device as in claim 9 wherein the second layer comprises an anode.
13. The semiconductor device as in claim 9 further comprising a fourth layer of the Periodic Table Group III nitride of the first conductivity type and a doping level at least two orders of magnitude higher than the doping level of the second layer, said fourth layer being disposed over the second layer.
14. The semiconductor device as in claim 9 further comprising a trench gate at least partially disposed over the fourth layer and penetrating the third and fourth layers and at least partially penetrating the first layer.
15. The semiconductor device as in claim 9 further comprising an aluminum nitride layer insulating the trench gate from the first, third and fourth layers.
16. The semiconductor device as in claim 9 further comprising a conductive metallic layer disposed over a portion of the fourth layer.
17. An insulated gate bipolar transistor comprising: a first layer of Galium nitride of a first conductivity type and a first doping level which forms a portion of the drift region of the bipolar transistor; a second layer of the Galium nitride of a second conductivity type and a second doping level at least one order of magnitude above the first doping level said second layer being disposed on a first side of the first layer; a third layer of silicon carbide of the first conductivity type and a doping level different from the first layer, said third layer being disposed on the second side of the -first layer; a fourth layer of the Periodic Table Group III nitride of the first conductivity type and a doping level at least two orders of magnitude higher than the doping level of the second layer, said fourth layer being disposed over the second layer; a trench gate at least partially disposed over the fourth layer and penetrating the third and fourth layers and at least partially penetrating the first layer; an aluminum nitride layer insulating the trench gate from the first, third and fourth layers; and a conductive metallic layer disposed over a portion of the fourth layer.
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