WO1999000839A1

WO1999000839A1 - Dual damascene etch process

Info

Publication number: WO1999000839A1
Application number: PCT/US1998/006828
Authority: WO
Inventors: Basab Bandyopadhyay; Michael J. Gatto
Original assignee: Advanced Micro Devices, Inc.
Priority date: 1997-06-26
Filing date: 1998-04-07
Publication date: 1999-01-07
Also published as: EP0995228A1

Abstract

A semiconductor process in which a semiconductor substrate (104) including a first interconnect level (108) is provided. An interlevel dielectric layer (110) is formed on the semiconductor substrate and a contact masking layer (122) is formed on the interlevel dielectric (110). A pattern of the contact masking layer (122) is aligned over a contact region (112) of the interlevel dielectric (110). An interconnect masking (130) layer is then formed on the contact masking layer (122). A pattern of the interconnect masking layer (130) is aligned over an interconnect region (136) of the interlevel dielectric layer (110). Portions of the contact region (112) are then selectively removed to form a contact tunnel (140). Portions of the interconnect region (136) are then selectively removed to form an interconnect trench (150). The contact tunnel (140) and the interconnect trench (150) are then filled with a conductive material (160). In the preferred embodiment, the contact masking layer (122) comprises a silicon nitride layer. The interconnect masking layer (130) is preferably a patterned photoresist layer formed on the contact masking layer (122). The formation of the interconnect masking layer (130) preferably precedes the step of selectively removing portions of the contact region (112) such that the interconnect masking layer (130) and the contact masking layer (122) are simultaneously present upon the interlevel dielectric layer (110) prior to the formation of the contact tunnels (140). In one embodiment, the filling of the contact tunnel and the filling of the interconnect trench are accomplished simultaneously. Ideally, selective removal of portions of the interconnect region vertically translates the contact tunnel within the interlevel dielectric such that the contact tunnel extends to an upper surface of the first interconnect level.

Description

TITLE: DUAL DAMASCENE ETCH PROCESS

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the field of semiconductor processing and more particularly to a method of forming a second or subsequent interconnect layer and a contact to first or a previously formed interconnect layer.

2. Description of the Relevant Art

Modern integrated circuits typically include a plurality of interconnect levels. Multiple interconnect levels are needed in high density integrated circuits to alleviate the density of interconnects within a given interconnect level. Typically, a multiple interconnect level integrated circuit process includes the initial steps of forming a transistor level, which includes a plurality of transistors within a silicon wafer substrate. The plurality of transistors are isolated from one another by isolation structures also formed within or upon the silicon substrate. After the completion of the transistor level, typical semiconductor processes include a series of process steps designed to produce multiple interconnect levels. In a typical sequence, an oxide layer is deposited upon the previous interconnect level. The oxide layer is then selectively etched to produce contact tunnels at desired locations within the oxide layer. The contact tunnels terminate on portions of a previous interconnect level.

After the contact tunnels have been formed, it is necessary to fill the contacts with a conductive material such as aluminum to provide a conductive path from the preceding interconnect level to the subsequently formed interconnect level. In older technologies (i.e.. technologies in which the minimum feature size of the transistors was greater than approximately 1 micron), the contact tunnels were typically filled during the same deposition process used to deposit the metal used for the subsequent interconnect level. In these older technologies, a single, aluminum sputtering process could be used to fill the contact tunnels and to form the subsequent metal layer. In submicron. multiple interconnect level semiconductor processes, however, the aspect ratio of typical contact tunnels has increased to the point where aluminum sputtering techniques are now typically inadequate to completely fill the contact tunnel with a aluminum. In these newer technologies, the filling of the contact tunnel typically required a dedicated processing step such as a CVD or tungsten deposition step to fill the contact tunnels with a conductive material prior to forming the interconnect layer. After the contact tunnels had been filled, a metal layer could then be deposited with a sputtering technique and the metal layer patterned with a conventional photolithography process.

Processing interconnect layers in this manner undesirably requires separate deposition processes for the deposition of the contacts and the deposition of the interconnect level. In addition, the deposition of the contact is typically followed by a planarization process such as a chemical mechanical polish that is frequently required to produce a substantially planar upper surface prior to the deposition of the subsequent interconnect level. These additional processing steps consume valuable resources of the fabrication facility and increase the overall cost of the process. In addition, increased wafer handling required by each additional wafer process increases the probability of introducing defects onto the wafer surface that may ultimately cause a reduction in the number of functional devices produced on each silicon substrate.

In addition to the problems noted above, the typical technique of forming the subsequent interconnect level by sputter depositing a metal layer, covering the metal layer with a patterned photoresist mask, and etching the metal, frequently produces inadequate results in semiconductor processes in which the metal pitch is less than approximately 1 micron because of the difficulty in achieving substantially vertical interconnect sidewalls and in subsequently filling the spaces between adjacent interconnects with an insulating dielectric. In these high density processes, damascene processes have been developed to improve the profiles of the metal interconnect. In a damascene process, metal is deposited into a trench previously formed within a dielectric layer trench. The trench is typically etched into a dielectric layer. A metal is then blanket deposited over the dielectric layer to fill the trenches. Thereafter, portions of the deposited metal exterior to the trenches can be removed with a chemical mechanical polish or other planarization process. The damascene process is desirable because the sidewalls profile of each interconnect is defined by patterning and etching a dielectric layer such as a CVD oxide rather than through the patterning of the metal itself. The difficulty of achieving substantially vertical interconnect sidewalls through the use of a metal etch process are well known in the field of semiconductor processing. In addition, a damascene process results in a substantially planar semiconductor surface upon which a subsequent interconnect level may be readily fabricated. In a non-damascene process, the interconnect level forms a non-planar topography with the dielectric layer upon which it sits. To produce a planar surface for subsequent processing, it is typically necessary to deposit a dielectric layer on the interconnect level and polish back the dielectric layer. In addition to the added processing required for this planarization. adequate filling of the spaces between adjacent interconnects within an interconnect level becomes difficult as the metal pitch decreases below 1 micron.

To accommodate the requirements of a separate deposition process for filling the contact tunnels and the desire to implement a damascene metal interconnect process, conventional, submicron type processes included by depositing an interlevel dielectric layer over a first interconnect level, etching contact tunnels into the interlevel dielectric layer, filling the dielectric layers with a conductive material, polishing back the conductive material, depositing a second dielectric layer, etching interconnect trenches into the second dielectric layer, depositing the second interconnect material into the trenches, and planarizing the interconnect metal. Although this process sequence achieves the desired result in high density, submicron, multiple interconnect level semiconductor processes, the processing sequence is unduly complicated and costly, especially if it must be repeated two or more times to accommodate three, four, or more levels of interconnect. It is therefore desirable to implement an interconnect processing sequence that reduces the complexity and costs of multiple deposition, multiple planarization interconnect sequences. SUMMARY OF THE INVENTION

The problems identified above are in large part addressed by a dual damascene process in which the pattern for the contacts and the pattern for the subsequent interconnect level are simultaneously present prior to the deposition of the appropriate conductive material. The subsequent interconnect level is fabricated with a damascene process eliminating the undesirable etch processes of previous semiconductor technologies. In addition, preferred embodiments of the present invention contemplate the integration of the process steps required to form the contact tunnels and the interconnect trenches and further contemplates the integration of the metal deposition process. In these embodiments, the reduced processing typically results in a lower cost and higher yield per wafer.

Broadly speaking, the present invention contemplates a semiconductor process in which a semiconductor substrate is provided. The semiconductor substrate includes a first interconnect level. An interlevel dielectric layer is formed on the semiconductor substrate and a contact masking layer is formed on the interlevel dielectric. A pattern of the contact masking layer is aligned over a contact region of the interlevel dielectric. An interconnect masking layer is then formed on the contact masking layer. A pattern of the interconnect masking layer is aligned over an interconnect region of the interlevel dielectric layer. Portions within the contact region of the interlevel dielectric layer are then selectively removed using the contact masking layer as a mask. Portions of the contact masking layer exposed by the pattern of the interconnect masking layer are then removed to expose an upper surface of the interconnect region of the interlevel dielectric layer. Portions of the interconnect region of the interlevel dielectric layer are then selectively removed using the interconnect masking layer as a mask to form an interconnect trench. The interconnect masking layer and any remaining portions of the contact masking layer are then removed. The contact tunnel and the interconnect trench are then filled with a conductive material.

Preferably, the formation of the interlevel dielectric layer is accomplished by decomposing TEOS in a chemical vapor deposition reactor chamber that is maintained at a temperature of less than approximately 650°C at a pressure of less than approximately 2 torrs. In the preferred embodiment, the formation of the contact masking layer includes depositing a silicon nitride layer on the interlevel dielectric layer and patterning the silicon nitride layer to remove portions of the silicon nitride layer over the contact region of the interlevel dielectric level. Depositing silicon nitride is preferably accomplished by decomposing silane and NH₃ in a ^• chemical vapor deposition reactor chamber maintained at a temperature in the range of approximately 600°C to 900°C and a pressure of less than approximately 2 torrs. Removing the portions of the contact masking layer exposed by the pattern of the interconnect masking layer and removing the remaining portions of the contact masking layer both comprise, in one embodiment, immersing the semiconductor substrate into an 85% phosphoric acid solution maintained at a temperature of approximately 100°C. The formation of the interconnect masking layer is preferably accomplished by depositing a photoresist layer on the contact masking layer and selectively removing portions of the photoresist layer that are aligned over the interconnect regions of the interlevel dielectric layer. The step of selectively removing portions of the contact region preferably comprises the anisotropic etch of the interlevel dielectric layer in a reactive ion etcher. The formation of the interconnect masking layer, in a presently preferred embodiment, precedes the step of selectively removing portions of the contact region. In this manner, the interconnect masking layer and the contact masking layer are simultaneously present upon the interlevel dielectric layer prior to the formation of the contact tunnels. The selective removal of portions of the interconnect region is ideally accomplished with an anisotropic etch of the interlevel dielectric layer in a reactive ion etcher. The boundaries of the contact tunnel region of the interlevel dielectric layer are suitably displaced between boundaries of the interconnect region of the interlevel dielectric layer. In one embodiment, the steps of selectively removing portions of the contact region, removing portions of the contact masking layer, and selectively removing portions of the interconnect region are all accomplished in a single reactive ion etcher using a single pump down cycle. In one embodiment, the filling of the contact tunnel and the filling of the interconnect trench are accomplished simultaneously. In this embodiment, the filling of the contact tunnel and the interconnect trench, in a preferred embodiment, include depositing a metal of aluminum, copper, tungsten, titanium, or an alloy thereof. The depositing of the metal into the contact tunnel and the interconnect trench is preferably accomplished in a chemical vapor deposition reactor chamber. In one embodiment, the depositing of the metal is preceded by depositing an adhesion layer on sidewalls of the contact tunnel and the interconnect trench.

Ideally, the selective removal of portions of the interconnect region has the effect of vertically translating the contact tunnel within the interlevel dielectric such that the contact tunnel extends to an upper surface of the first interconnect level of the semiconductor substrate.

The present invention still further contemplates a semiconductor process in which a semiconductor substrate is provided and an interlevel dielectric level is deposited on an upper surface of the semiconductor substrate. A contact tunnel is then formed within a contact region of the interlevel dielectric layer. A depth of the contact tunnel is less than a thickness of the interlevel dielectric layer. An interconnect trench is then formed within an interconnect region of the interlevel dielectric layer. The forming of the interconnect trench has the effect of vertically translating the contact tunnel within the interlevel dielectric layer such that the contact tunnel extends to an upper surface of the semiconductor substrate. Tliereafter, the contact tunnel and the interconnect trench are filled with a conductive material. In one embodiment, the semiconductor substrate includes a silicon substrate and a first interconnect level formed above the silicon substrate. The deposition of the interlevel dielectric layer preferably comprises decomposing TEOS in a C VD reactor chamber maintained at a temperature of less than approximately 650°C and a pressure of less than approximately two torrs. The formation of the contact tunnel, in a preferred embodiment, includes forming a contact masking layer on the interlevel dielectric layer. The contact masking layer is aligned over a contact region of the interlevel dielectric layer such that an upper surface of the contact region is exposed by the contact masking layer. Thereafter, portions of the contact region of the interlevel dielectric layer are removed with a reactive ion etcher. The formation of the contact masking layer preferably includes the steps of depositing a silicon nitride layer on an upper surface of the interlevel dielectric layer, forming a patterned photoresist mask on an upper surface of the silicon nitride layer, and removing portions of the silicon nitride layer exposed by the photoresist mask with a silicon nitride etch process. In one embodiment, the process further includes the step of forming an interconnect masking layer on an upper surface of the contact masking layer after the contact mask has been formed but prior to the formation of the interconnect trench. The etching of the interconnect trench preferably includes the steps of forming an interconnect mask layer above the semiconductor substrate. The interconnect masking layer exposes an upper surface of the interconnect region of the interlevel dielectric layer. Exposed portions of the interconnect region of the interlevel dielectric layer are then anisotropically removed using a reactive ion etcher. The formation of the interconnect masking layer suitably occurs before the etching of the contact tunnel. In this manner the interconnect masking layer is formed on an upper surface of a contact masking layer that is formed on an upper surface of the interlevel dielectric layer. The filling of the contact tunnel and the interconnect trench are accomplished simultaneously in the presently preferred embodiment. The filling of the contact tunnel and the interconnect trench is preferably accomplished by depositing a metal such as aluminum, copper, tungsten, titanium, or alloys thereof. The deposition is ideally accomplished in a chemical vapor deposition reactor chamber. The deposition step is preceded, in one embodiment, by depositing an adhesion layer on sidewalls of the contact tunnel and the interconnect trench.

The present invention still further contemplates a semiconductor process in which a semiconductor substrate is provided, an interlevel dielectric layer is deposited on an upper surface of the semiconductor substrate, an interconnect/contact opening is formed in the interlevel dielectric, and the interconnect/contact opening is filled with a conductive material. The interconnect/contact opening includes an interconnect trench formed within an upper region of the upper level dielectric layer and further includes a contact tunnel that communicates an upper surface of the semiconductor substrate with the interconnect trench. The filling of the interconnect/contact opening is accomplished with a single deposition step in a preferred embodiment. In one embodiment, a width of the interconnect trench is greater than a width of the contact tunnel such that sidewalls of the contact tunnel are laterally displaced between sidewalls of the interconnect trench.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which:

Fig. 1 is a partial cross-sectional view of the semiconductor substrate including a first interconnect level:

Fig. 2 is a processing step subsequent to Fig. 1 in which an interlevel dielectric layer has been formed on the semiconductor substrate:

Fig. 3 is a processing step subsequent to Fig. 2 in which a contact masking layer has been formed on the interlevel dielectric layer aligned over a contact region of the interlevel dielectric layer,

Fig. 4 is processing step subsequent to Fig. 3 in which an interconnect masking layer has been formed on the contract masking layer. Fig. 5 is a processing step subsequent to Fig. 4 in which the interconnect masking layer has been patterned and aligned over an interconnect region of the interlevel dielectric layer;

Fig. 6 is processing step subsequent to Fig. 5 in which portions of the interlevel dielectric layer within the contact region have been removed;

Fig. 7 is a processing step subsequent to Fig. 6 in which portions of the contact masking layer exposed by the pattern of the interconnect masking layer have been removed to expose an upper surface of the interconnect region of the interlevel dielectric layer;

Fig. 8 is a processing step subsequent to Fig. 7 in which portions of the interconnect region of the interlevel dielectric layer are then selectively removed using the interconnect masking layer as a mask to form an interconnect trench: and

Fig. 9 is a processing step subsequent to Fig. 8 in which the interconnect trench is filled with a conductive material.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.

DETAILED DESCRIPTION OF THE DRAWINGS

Turning now to the drawings, Fig. 1 through 9 disclose a processing sequence for f πning a second interconnect level and connecting the second interconnect level with a first interconnect level according to the present invention. In Fig. 1, semiconductor substrate 102 is provided. Semiconductor substrate 102 preferably includes a silicon substrate 104 upon which a first interconnect level 108 is formed within upper region 106 of semiconductor substrate 102. A suitable starting material for silicon substrate 104 useful in the fabrication of CMOS integrated circuits includes a p-type epitaxial layer formed over a p+ silicon bulk. A preferred resistivity of the p-type epitaxial layer is in the range of approximately 10 to 15 Ω-cm. The ρ+ silicon bulk includes a concentration of a semiconductor impurity such as boron in a peak concentration greater than approximately 10¹⁹ atoms/cm³. In the embodiment shown in Fig. 1, first interconnect level 108 is a metal or metal alloy interconnect level as are well known in the field of semiconductor processing. It is to be understood, however, that the first interconnect level may comprise a plurality of transistors fabricated within silicon substrate 104. The significance of the present invention does not lie in the composition of the preceding interconnect level but rather in the method of fabricating a subsequent interconnect level and a contact structure to the preceding interconnect level. The specific embodiment of first interconnect level 108 as shown in Fig. 1 is of the metal interconnect variety because this is a common form of a preceding interconnect level in a multiple interconnect level semiconductor process. Such multiple level interconnect processes are rapidly becoming more prevalent in the semiconductor industry. Four and five layer metal processes are not uncommon in semiconductor processes used to fabricate, for example, CMOS integrated circuits such as microprocessors and other complex logic devices.

Turning to Fig. 2, an interlevel dielectric layer 110 is formed on an upper surface 101 of semiconductor substrate 102. Interconnect dielectric layer 110 includes a contact region 112 bounded by first and second contact region boundaries 112a and 1 12b respectively. Interlevel dielectric layer 110 further includes an interconnect region 114 bounded by first and second interconnect region boundaries 114a and 114b. First and second contact region boundaries 112a and 1 12b are laterally displaced between first and second interconnect region boundaries 1 14a and 114b. A preferred method of fabricating interlevel dielectric layer 110 includes the steps of decomposing TEOS in a chemical vapor deposition reactor chamber maintained at a temperature of less than approximately 650°C and a pressure of less than approximately two torrs. A preferred thickness of interlevel dielectric layer 1 10 is equal to a first displacement d, (shown in greater detail and described with respect to Fig. 6) and a second displacement d_; (shown in greater detail and described with respect to Fig. 8) which represent the height of the contact structure and a thickness of the second interconnect level respectively. In a preferred embodiment a thickness of interlevel dielectric layer 110 is in the range of approximately 5000 to 1500 angstroms.

In Fig. 3. an interconnect masking layer 120 is fabricated on an upper surface 111 of interlevel dielectric layer 1 10. Interconnect masking layer 120 includes an interconnect masking material 122 and an interconnect mask opening 124. Interconnect mask opening 124 is bounded by first and second interconnect mask opening sidewalls 124a and 124b respectively. Interconnect masking layer 120 is aligned over contact region 1 12 of interlevel dielectric layer 1 10. In other words, first sidewall 124a of interconnect mask opening 124 is laterally aligned with first contact region boundary 1 12a and second interconnect mask opening sidewall 124b is laterally aligned with second contact boundary 112b. In a presently preferred embodiment, a preferred method of forming contact masking layer 120 includes depositing silicon nitride on upper surface 111 of interlevel dielectric layer 110 and thereafter patterning the silicon nitride layer with a conventional photolithography/etch process sequence. In such an embodiment, the preferred process for depositing sihcon nitride on interlevel dielectric layer 110 includes decomposing silane and NH₃ in a chemical vapor deposition reactor chamber maintained at a temperature in the range of approximately 600°C to 900°C at a pressure of less than approximately two torrs. In one embodiment, the removal of portions of the silicon nitride layer is accomplished with an 85% phosphoric acid solution maintained at a temperature of approximately 100°C. Ideally, a thickness of contact masking layer 120 is in the range of approximately 100 to 500 angstroms. This relatively thin masking layer can be adequately covered by a subsequent photoreist as will be described below. Although contact masking layer 120 is patterned in the processing sequence shown in Fig. 3. it is noted that the contact etch is not executed at this point in the presently preferred process. Instead, the contact etch will be performed at a subsequent point in the process and, ideally, may be combined with the etch process required to form an interconnect trench that will define the second interconnect level.

Turning to Fig. 4, an interconnect masking layer material 130 is deposited over contact masking layer 120 and interlevel dielectric layer 1 10. Interconnect masking layer material 130, in a presently preferred embodiment, is formed by spin depositing photoresist over contact masking layer 120. The specific compositions of contact masking layer 120 and interconnect masking layer material 130 is not typically critical. It is important, however, that a process exists for selectively removing contact masking layer 120 without selectively removing interconnect masking layer material 130. This restriction requires that contact masking layer 120 and interconnect masking layer material 130 be of dissimilar material. In addition, it must be possible in the present invention to selectively remove portions of interlevel dielectric layer 110 without removing significant portions of contact masking layer 120 or interconnect masking layer material 130. Thus, the material used for interlevel dielectric layer 1 10. contact masking layer 120, and interconnect masking layer material 130 must typically all be different. These requirements are all met in an embodiment of the present invention in which interlevel dielectric layer 1 10 is CVD oxide as described above, contact masking layer 120 is silicon nitride, and interconnect masking layer material 130 is photoresist. It is noted that first interconnect level 108 is not shown in each of the figures. The absence of first interconnect level 108 occurs only in those figures in which the presence of first interconnect level 108 in the figure is not required for an understanding of the process being described with respect to the particular figure and may unduly complicate the diagram. It is to be understood, however, that first interconnect level 108 is, nevertheless, included within semiconductor substrate 102 in all of the figures.

Turning now to Fig 5. interconnect masking layer 132 is fabricated from interconnect masking layer material 130. In an embodiment of the present invention in which interconnect masking layer material 130 comprises photoresist, the formation of interconnect masking layer 132 is accomplished with a photolithographic exposure/develop cycle as is well known in the field of photolithography. Interconnect masking layer 132 includes interconnect mask opening 136 is defined by first and second interconnect mask opening sidewalls 136a and 136b Interconnect masking layer 132 is aligned over interconnect region 114 of interlevel dielectric layer 1 10 h a manner similar to the alignment of contact masking layer 120 to contact region 112. the alignment of interconnect masking layer 132 to interconnect region 114 requires that first interconnect mask opening sidewall 136a is laterally aligned over first interconnect region boundary 114a of ^■ interconnect region 114 and second interconnect mask opening sidewall 136b is laterally aligned over second interconnect region boundary 114b. It will be appreciated that the formation of interconnect masking layer 132 does not substantially alter interlevel dielectric 1 10 or contact masking layer 120. It is appreciated, therefore, that, as shown in Fig. 5, the present invention contemplates the simultaneous presence upon interlevel dielectric level 110 of contact masking layer 120 and an interconnect masking layer 132. Once the contact masking layer 120 and the interconnect masking layer 132 have been formed over the interlevel dielectric layer 110, then an etch process may be initiated to fabricate an opening to first interconnect level 108. By forming dual masking layers over interlevel dielectric layer 110. one embodiment of the present invention contemplates combining the etch process used to fabricate a contact tunnel with the etch process used to fabricate a second interconnect level trench. It is noted that the formation of interconnect masking layer 132 results in the exposure of exposed portions 138 of contact masking layer 120.

Turning now to Fig. 6, portions of interlevel dielectric layer 110 within contact region 112 are selectively removed to form a contact tunnel 140 extending a first displacement d, below upper surface 111 of interlevel dielectric layer 110. First displacement d_b in a presently preferred embodiment, is less than a thickness t_iw of interlevel dielectric layer 110. In one embodiment, the thickness t_iId of interlevel dielectric layer 110 is approximately equal to first displacement d, and a second displacement d₂ where the second displacement d₂ is approximately equal to a thickness of an interconnect trench used for the formation of a second interconnect level as shown and described below with respect to Fig. 8. In an embodiment in which interlevel dielectric layer 110 comprises a CVD or other oxide, a preferred process of forming contact tunnel 140 comprises anisotropically etching interlevel dielectric layer 110 in a reactive ion etcher using a fluorine bearing plasma as is well known in the field of semiconductor processing. The presence of contact masking layer 120 during the formation of contact 140 prevents significant removal of interlevel dielectric layer 110 from regions exterior to contact region 112. Turning now to Fig. 7. exposed portions 138 of contact masking layer 120 are removed so that upper surface 1 15 of interconnect region 114 is exposed. In the preferred embodiment in which contact masking layer 120 comprises a silicon nitride material, the removal of exposed portions 138 of contact masking layer 120 may be accomplished with a heated phosphoric solution as is well known. In another embodiment, it is contemplated that the process steps shown in Figs. 6 - 8 may be accomplished in a single etch apparatus using a single pump down cycle. In such an embodiment, a three stage etch process would be executed. During the first stage, contact tunnel 140 would be formed. During the second stage, exposed portions 138 of contact masking layer 120 would be removed while, during the third stage, an interconnect trench 150 ( shown an described in Fig. 8) would be formed. In this embodiment, the removal of exposed portions 138 of contact masking layer 120 could be suitably achieved with a conventional, dry, silicon nitride etch process. Combining the process steps required to form contact tunnel 140. removed exposed portions 138 of contact masking layer 120. and form interconnect trench 150 advantageously reduces the amount of handling to which semiconductor substrate 102 is subjected.

Turning now to Fig. 8. interconnect trench 150 is formed by selectively removing portions of interlevel dielectric layer 110 within interconnect region 114. Ideally, the etch process used to form interconnect trench 150 is substantially similar to the etch process used to form contact tunnel 140. Specifically, it is contemplated in a presently preferred embodiment that the formation of interconnect 150 comprises an anisotropic oxide etch process. As will be appreciated to those skilled in the art of semiconductor etch processes, performing an anisotropic etch process on the topography of interlevel dielectric layer 110 shown in Fig. 7 will result in an effective vertical translation of contact tunnel 140 wherein the amount of translation is approximately equal to the second depth d₂ of interconnect trench 150. It will be further appreciated that if a floor 140c of contact tunnel 140 (shown in Fig. 6) was vertically displaced above upper surface 101 of semiconductor substrate 102 prior to the formation of interconnect trench 150, then contact tunnel 140 will extend to upper surface 101 of semiconductor substrate 102 after the formation of interconnect trench 150. In this manner, an interconnect/contact opening 152 is fabricated within interlevel dielectric layer 110. Interconnect/contact opening 152 extends from an upper surface 111 of interlevel dielectric layer 110 to an upper surface 101 of semiconductor substrate 102. In an embodiment of semiconductor substrate 102 in which a first interconnect level 108 occupies upper region 106 of semiconductor substrate 102 including upper surface 101 of semiconductor substrate 102. then it will be appreciated that interconnect/contact opening 152 extends to first interconnect level 108. Interconnect/contact opening 152 includes an interconnect trench 150 and a contact tunnel 140. Contact tunnel 140 communicates between first interconnect level 108 within semiconductor substrate 102 and a lower surface 150c of interconnect trench 150. In a presently preferred embodiment, a width of interconnect trench 150 is greater than the width of contact tunnel 140 and sidewalls 140a and 140b of contact tunnel 140 are laterally displaced between sidewalls 150a and 150b of interconnect trench 150. Turning now to Fig. 9. interconnect/contact opening 152 is filled with a conductive material to form a contact/interconnect structure 160. In the embodiment shown in Fig. 9, contact structure 160 includes an adhesion layer 160a and an interior layer 160b. In this embodiment, adhesion layer 160 may be desired in certain applications to improve the adhesion of contact/interconnect structure 160 to interlevel dielectric layer 1 10. In embodiments of contact/interconnect structure 160 utilizing an adhesion layer 160a, a filling of interconnect/contact opening 152 is initiated by blanket depositing an adhesion material onto the sidewalls of interconnect/contact opening 152. Suitable adhesion materials include titanium (Ti), titanium-tungsten (Ti:W), titanium nitride (Ti:N), or tungsten suicides (WSi_x). Adhesion layers are typically required in those cases where the material used for central portion 160b of contact/interconnect structure 160 adhere poorly to the material of interlevel dielectric layer 1 10. Adhesion layers are typically required, for example, to compensate for the poor adhesion characteristics of tungsten and some tungsten alloys to silicon/oxide dielectric films. After adhesion layer 160a has been deposited, a core material 160 is then deposited on adhesion layer 160. In this damascene process, the interconnect portion of contact/interconnect structure 160 is defined by interconnect trench 150. After the deposition of core material 160b, a mechanical planarization process such as a chemical mechanical polish is required to remove portions of the deposited film from regions exterior to interconnect trench 150. The use of a damascene process to form an interconnect is desirable because the interconnect sidewalls are defined by an oxide etch process. It is well known to those in the field of semiconductor processing that achieving substantially vertical interconnect sidewalls with an oxide etched trench is preferable to using a metal etch process. In addition, after the chemical mechanical polish typically used in a damascene process, an upper surface 161 of the interconnect structure is substantially planar with an upper surface 111 of interlevel dielectric 110. The inherently planar topography produced by damascene processes faciUtates subsequent interconnect processing because no additional planarization is typically required. Beginning with the structure shown in Fig. 9, for example, a subsequent interconnect level may be fabricated by essentially repeating the processing sequence shown in Figs. 2 through 9. In this manner, multiple levels of interconnect may be fabricated upon a semiconductor substrate. It is to be understood that although the specific embodiment shown in Fig. 9 discloses an adhesion layer 160a, an alternative embodiment may eliminate the need for a separate adhesion layer. In such an embodiment, the formation of contact interconnect structure 160 is accomplished with a single deposition step in which a conductive material such as aluminum, copper, tungsten, titanium, or appropriate alloys thereof are deposited into interconnect/contact opening 152 and thereafter planarized as described above. In a presently preferred embodiment, adhesion layer 160a may be suitably eliminated in conjunction with a CVD aluminum process. A CVD aluminum process is desirable because (1) the resistivity of CVD aluminum is typically significantly lower than the resistivity of other CVD metals such as tungsten, (2) CVD aluminum exhibits excellent adhesion to silicon and typical dielectric materials such as CVD oxide, and (3) excellent conformal coverage of the underlying structure can be achieved with CVD alurninum processes. In one embodiment, aluminum is chemically vapor deposited by the pyrolisis of triisobutyl aluminum (TIBA) in a reactor chamber maintained at a temperature of approximately 250°C and a pressure less than approximately 1 torr.

It will be appreciated to those skilled in the art that the present invention contemplates the simplified formation of an interconnect/contact structure for used in multiple level interconnect technologies. Various modifications and changes may be made to each and every processing step as would be obvious to a person skilled in the art having the benefit of this disclosure. It is intended that the following claims be interpreted to embrace all such modifications and changes and. accordingly, the specification and drawings are to regarded in an illustrative rather than a restrictive sense

Claims

WHAT IS CLAIMED IS:

1. A semiconductor process, comprising:

providing a semiconductor substrate, wherein said semiconductor substrate includes a first interconnect level;

forming an interlevel dielectric layer on said semiconductor substrate;

forming a contact masking layer on said interlevel dielectric, wherein a pattern of said contact masking layer is aligned over a contact region of said interlevel dielectric;

forming an interconnect masking layer on said contact masking layer, wherein a pattern of said interconnect masking layer is aligned over an interconnect region of said interlevel dielectric layer;

using said contact masking layer as a mask, selectively removing portions of said contact region of said interlevel dielectric layer to form a contact tunnel:

removing portions of said contact masking layer exposed by said pattern of said interconnect masking layer to expose an upper surface of said interconnect region of said interlevel dielectric;

using said interconnect masking layer as a mask, selectively removing portions of said interconnect region of said interlevel dielectric layer to form an interconnect trench;

removing said interconnect masking layer:

removing any remaining portions of said contact masking layer; and

tilling said contact tunnel and said interconnect trench with a conductive material.

2. The process of claim 1 wherein the step of tb╧Çning said interlevel dielectric comprising decomposing TEOS in a CVD reactor chamber maintained a temperature of less than approximately 650┬░ C and a pressure of less than approximately 2 torrs.

3. The process of claim 1, wherein the step of forming a contact masking layer comprises:

depositing a silicon nitride layer on said interlevel dielectric; and patterning said silicon nitride layer to remove portions of said silicon nitride layer over said contact region of said interlevel dielectric.

4. The process of claim 3, wherein the step of depositing silicon nitride comprising decomposing silane and NH₃ in a CVD reactor chamber maintained at a temperature in the range of approximately 600 to 900 ┬░C and a pressure of less than approximately 2 torrs.

5. The process of claim 3, wherein the steps of removing said portions of said contact masking layer exposed by said pattern of said interconnect masking layer and removing said remaining portions of said contact masking layer comprise immersing said semiconductor substrate into a 85% phosphoric acid solution maintained at a temperature of approximately 100 ┬░C.

6. The process of claim 1 , wherein the step of forming said interconnect masking layer comprises:

depositing a photoresist layer on said contact masking layer, and

selectively removing portions of said photoresist layer aligned over said interconnect regions of said interlevel dielectric.

7. The process of claim 1, wherein the step of selectively removing portions of said contact region comprises anisotropically etching said interlevel dielectric in a reactive ion etcher.

8. The process of claim 1 , wherein the step of forming said interconnect masking layer precedes the step of selectively removing portions of said contact region, such that said interconnect masking layer and said contact masking layer are simultaneously present:

9. The process of claim 1. wherein the step of selectively removing portions of said interconnect region comprises anisotropically etching said interlevel dielectric in a reactive ion etcher.

10. The process of claim 1. wherein boundaries of said contact tunnel region of said interlevel dielectric are laterally displaced between boundaries of said interconnect region of said interlevel dielectric.

1 1. The process of claim 1 , wherein the steps of selectively removing said portion of said contact region, removing portions of said contact masking layer, and selectively removing portions of said interconnect region are accomplished in a single reactive ion etcher with a single pump down cycle.

12. The process of claim 1. wherein the step of filling said contact tunnel and said interconnect trench are accomplished simultaneously.

13. The process of claim 12, wherein the step of filling said contact tunnel and said interconnect trench comprise depositing a metal selected from the group consisting of aluminum, copper, tungsten, titanium, and alloys thereof.

14. The process of claim 13. wherein said depositing is accomplished in a CVD reactor chamber.

15. The process of claim 13, wherein said depositing is preceded by a depositing of an adhesion layer on sidewalls of said contact tunnel and said interconnect trench.

16. The process of claim 1 , wherein the step of selectively removing said portions of said interconnect region simultaneously effects a vertical translation of said contact tunnel within said interlevel dielectric whereby said contact tunnel extends to an upper surface of said first interconnect level of the semiconductor substrate.

17. A semiconductor process comprising:

providing a semiconductor substrate;

depositing an interlevel dielectric layer on an upper surface of said semiconductor substrate;

forming a contact tunnel within a contact region of said interlevel dielectric layer, wherein a depth of said contact tunnel is less than a thickness of said interlevel dielectric:

forming an interconnect trench within an interconnect region of said interlevel dielectric wherein said forming of said interconnect trench effects a vertical translation of said contact tunnel within said interlevel dielectric such that said contact tunnel extends to an upper surface of said semiconductor substrate: and

filling said contact tunnel and said interconnect trench with a conductive material.

18. The process of claim 17. wherein said semiconductor substrate, includes a sihcon substrate and a first interconnect level formed above said semiconductor substrate.

19. The process of claim 17, wherein the step of depositing said interlevel dielectric comprises, decomposing TEOS in a CVD reactor chamber maintained at a temperature of less than approximately 650 ┬░C and a pressure of less than approximately 2 torrs.

20. The process of claim 17, wherein the step of forming said contact tunnel comprises:

forming a contact masking layer on said interlevel dielectric, wherein said contact masking layer is aligned over a contact region of said interlevel dielectric such that an upper surface of said contact region is exposed by said contact masking layer; and

removing portions of said contact region of said interlevel dielectric with a reactive ion etcher.

21. The process of claim 20. wherein the step of forming said contact masking layer comprises:

depositing a silicon nitride layer on an upper surface of said interlevel dielectric;

forming a patterned photoresist mask on an upper surface of said silicon nitride layer, and

removing portions of the silicon nitride layer exposed by said photoresist mask with a silicon nitride etch process.

22. The process of claim 20. further comprising, after the step of forming said contact masking layer and prior to the step of etching said interconnect trench, forming an interconnect masking layer on an upper surface of said contact masking layer.

23. The process of claim 17. wherein the step of etching said interconnect trench comprises:

forming an interconnect masking layer above said semiconductor substrate, wherein said interconnect masking layer exposes an upper surface of said interconnect region of said interlevel dielectric: and

anisotropically removing portions of said interconnect region of said interlevel dielectric using a reactive ion etcher.

24. The process of claim 23 wherein the step of forming said interconnect masking layer occurs before the step of etching said contact tunnel such that said interconnect masking layer is formed on an upper surface of a contact masking layer formed on an upper surface of said interlevel dielectric.

25. The process of claim 17, wherein the step of filling said contact tunnel and said interconnect trench are accomplished simultaneously.

26. The process of claim 25, wherein the step of filling said contact tunnel and said interconnect trench comprise depositing a metal selected from the group consisting of aluminum, copper, tungsten, titanium, and alloys thereof.

27. The process of claim 26. wherein said depositing is accomplished in a CVD reactor chamber.

28. The process of claim 26, wherein said depositing is preceded by a depositing of an adhesion layer on sidewalls of said contact tunnel and said interconnect trench.

29. A semiconductor process comprising:

providing a semiconductor substrate;

depositing an interlevel dielectric layer on an upper surface of said semiconductor substrate, wherein said semiconductor substrate includes a first interconnect level;

forming an interconnect/contact opening in said interlevel dielectric , wherein said interconnect contact opening extends from an upper surface of said interlevel dielectric to an said first interconnect level, and wherein said interconnect/contact opening includes an interconnect trench formed within an upper region of said interlevel dielectric and a contact tunnel communicating between a first material interconnect level and said interconnect trench; and

filling said interconnect/contact opening with a conductive material, wherein the process of filling said contact tunnel and said interconnect trench is accomplished with a single deposition step.

30. The process of claim 29. wherein a width of said interconnect trench is greater than a width of said contact tunnel and wherein sidewalls of said contact tunnel are laterally displaced between sidewalls of said interconnect trench.