WO1999000959A1

WO1999000959A1 - Communications network end station

Info

Publication number: WO1999000959A1
Application number: PCT/GB1998/001871
Authority: WO
Inventors: Trevor Edward Willis; Simon Benham; Christopher Aston
Original assignee: Madge Networks Limited
Priority date: 1997-06-26
Filing date: 1998-06-26
Publication date: 1999-01-07
Also published as: GB9713539D0; EP0992144A1

Abstract

The present invention relates to an interface device (6) for connecting a communications network end station (1) to a communications network (2). The end station includes a number data handling devices (4, 5) which transfer sets of data to the communications network via the interface device. This transfer occurs via two interface connections (A, B), each of which may be coupled to any of the data handling devices (4, 5). Transfer is controlled by a scheduler (11) to ensure that the transfer of each set of data satisfies respective transfer criteria.

Description

COMMUNICATIONS NETWORK END STATION

The present invention relates to an interface device for connecting a communications network end station to a communications network where the end station has a plurality of data handling devices programmed to cooperate with the interface device to transfer data between each data handling device and the communications network.

Data communication networks are provided to enable the transfer of data between end stations such as personal computers, file servers and other communication networks. Data is transmitted around such networks in accordance with standard protocols such as token ring, ethernet, FDDI or ATM. Conventionally, an end station will be coupled to a network through a connecting device, such as a network interface card, installed in the end station. The host processor of the end station is then programmed to cooperate with the network interface card so as to provide data for the network in a format compatible with the network protocol. The network interface card will also convert data received from the network into a format compatible with the end station.

In recent years there has been a vast improvement in the processing speed of network end stations and also in the data transmission speeds of communications networks. This allows large amounts of data to be transferred over communications networks. However, the ability of the interface device to transfer data from the host processor to the communications network can still, at times, be limited. As a consequence, the interface device now often forms a bottle neck slowing down the flow of data from the end station to the network. This is particularly important for multi-media voice and video communications and the like which require a high bandwidth and/or low latency for data transfer.

Some network interface cards, such as ATM interface cards, transfer data from the end station to the communications network by assigning particular sets of data to respective virtual channel connections between the network interface card and the communications network. All the virtual channels are provided along a single physical connection between the network interface card and the communications network and it is therefore necessary to multiplex the data on this physical channel. This can be achieved by assigning each channel to a respective timer and then transferring data along the channel when the timer generates an indication that data should be transferred. These timers will generally be prioritised such that should two timers indicate that data from different sets of data be sent along the respective virtual channels simultaneously, one virtual channel will be chosen in preference to another.

Unfortunately, this suffers from the limitation that a timer is required for each virtual channel connection from the communications network to the interface card. Furthermore, the prioritising of different virtual channels can often lead to periods where no data is being sent between the communications network and the network interface card or, worse still, that data is sent on only a few of the channels along which data needs to be sent. This reduces the efficiency of the data transfer system and leads to an effective reduction in the bandwidth available for data transfer.

In accordance with a first aspect of the present invention, we provide an interface device for connecting a communications network end station to a communications network, the end station having at least two data handling devices programmed to cooperate with the interface device to transfer sets of data between each data handling device and the communications network in accordance with respective transfer criteria, wherein the interface device comprises: at least two interface connections, each interface connection being adapted for coupling to any of the data handling devices; and a scheduler, coupled to the interface connections, which controls the transfer of each set of data to the network in accordance with the respective transfer criteria.

In accordance with a second aspect of the invention, we provide a method of connecting a communications network end station to a communications network using an interface device, the end station having a plurality of data handling devices programmed to cooperate with the interface device to transfer a set of data between each data handling device and a communications network in accordance with respective transfer criteria, the interface device including a plurality of interface connections, for coupling to any of the data handling devices, the method comprising causing the interface connections to receive data from any one of the data handling devices, and controlling the transfer of each set of data to the network in accordance with the predetermined transfer criteria.

The present invention provides a method and apparatus for connecting at least two data handling devices of a network end station to a network. The connection is achieved using a single interface device by providing at least two connections between the end station and the interface device, thereby allowing the simultaneous transfer of data between each data handling device and the interface device. Transfer of the data to the network is then controlled by a scheduler to ensure the data is transferred in accordance with respective transfer criteria .

This invention is particularly useful for an end station which is operating a voice or video communications link that requires a constant bandwidth connection to the network, as the communications link can be maintained on one connection whilst any other data to be sent to the network can be maintained on the other connection. For example, an MVIP card having an ATM network interface and an interface connection to a PCI bus supporting conventional LAN data as well as a separate MVIP interface to a multimedia device such as a phonecard.

Typically, the interface device of the network end station further comprises, a transmit/receive interface for coupling the interface device to the network, wherein the transmit/receive interface modifies the data prior to transfer to the network and wherein the transmit/receive interface is coupled to the scheduler such that the scheduler controls the transfer of data to and from the transmit/receive interface. The transmit/receive interface is used to ensure that the data is in the correct format for transfer over the network, for example by adding or removing headers .

In the preferred case, the interface device further comprises a store or stores coupled to the interface connections, wherein the store (s) store data for transfer to or from the interface connections. This allows data to be stored on the card prior to transfer to the network whilst other data is transferred. This prevents the loss of any data and allows data to be stored until a later time when there is less data for transfer. Typically the scheduler includes a number of timers for controlling the transfer of each set of data from the interface connections to the network, each timer having a respective priority status and generating a respective transfer ready signal at a respective transfer ready frequency. In this case the scheduler also advantageously includes a processor which associates each set of data with at least one timer in accordance with the transfer criteria. This allows the data to be associated with one of the timers depending on the transfer criteria, such that data will be transferred upon generation of a transfer ready signal. Accordingly, if the data has a high bandwidth requirement it will be associated with a timer having a high transfer ready frequency, thus ensuring the data is sent more often than any data associated with a timer having a lower transfer ready signal.

Preferably, each interface connection comprises an adaptor for segmenting each set of data received from a data handling device into a number of discrete data packets. When a store is provided, the data packets are stored in the store. The adaptors also reassemble discrete data packets received from the network into a data stream for transfer to the data handling devices. It is easier for the scheduler to control the flow of two sets of data if each set of data is segmented into discrete packets as the packets of data from different sets of data can be more easily interspersed than data from continuous streams. The segmentation of the data stream received from the data handling devices also allows for easier storage of the data prior to transfer to the network, if a store is provided.

Typically each set of data is transferred from the interface device to the communications network via a respective virtual channel, the virtual channel being established by a transfer of initialization data from the end station to the communications network, the initialization data including the transfer criteria of the respective set of data, wherein each adaptor is adapted to detect and transfer the transfer criteria to the scheduler. The use of a number of different channels is already standard practice in some communication protocols such as ATM. By utilising this, a channel can be assigned to one of the connections allowing each interface connection to have a dedicated channel for transferring data.

Alternatively however, there may be provided a direct connection from the host processor of the end station to the scheduler so the information can be transferred directly. A further alternative is for each set of data transferred from each data handling device to include a criteria indicator indicating the respective transfer criteria of the set of data, and wherein the adaptor includes a detector which detects and transfers the criteria indicator to the scheduler. It will be realised that the method used will be influenced by the nature of the data to be transferred. Typically, each adaptor comprises a frame receiver for coupling to a respective data handling device, wherein the frame receiver receives data packets and reassembles the discrete data packets into a data stream for transfer to the data handling device; and a frame transmitter for coupling to a respective data handling device, the frame transmitter receiving the data stream from the respective data handling device and segmenting the data stream into

^' discrete data packets. However, any suitable device for segmenting and reassembling the data streams could be used. Typically, the frame transmitter and the frame receiver of each adaptor are also coupled to the scheduler, the scheduler monitoring the transfer of data to and from the frame transmitter and receiver.

Preferably, when the interface device is connected to an end station, the end station comprises a host processor and/or a DMA controller coupled to the interface connections. This enables the host processor of the computer or the DMA controller to oversee the data transfer. One host processor may oversee the data transfer associated with each interface connection or individual processors may oversee the data transfer for each individual interface connection.

An example of the present invention will now be described with reference to the accompanying drawing, in which :-

Figure 1 shows a schematic diagram representing an end station;

Figure 2 shows in more detail the scheduler of Figure

1; Figure 3 is a representation of the link-list of one of the timers of the scheduler of Figure 2; Figure 4 is a diagram showing the header of a set of data associated with a virtual channel assigned to the link-list of Figure 3; and,

Figures 5a to 5e show a representation of the transfer of data from the interface device to the network.

Figure 1 shows an end station 1 connected to a communications network 2. The end station 1 comprises a host processor 3 connected to an input device 4, such as a keyboard or the like, and to a communication device 5 such as a telephone handset or the like.

The host processor 3 is coupled to the network 2 via a network interface card 6. The network interface card 6 has two segmentation and reassembly adaptors A,B which are connected to a memory interface 7 and the host processor 3 of the end station 1. The two adaptors A,B act to segment a stream of data to be transmitted into ATM cells or reassemble a stream of data from a number of received cells .

The memory interface 7 which is connected to a buffer memory 8 , may be segmented into two memory interface segments 7A,7B, each segment being connected to a respective adapter A,B. Similarly the memory 8 may be segmented into memory segments 8A, 8B for connection to the respective memory interface segments 7A,7B. This allows data for transfer to or from adapters A,B to be stored separately as will be understood by a person skilled in the art. For simplicity the remainder of the description will refer only to the memory interface 7 and memory 8 as a whole. It should also be understood that in some cases a memory is not necessary.

The memory interface 7 is also connected to a transmit interface 9 and a receive interface 10 as shown. Both the receive and transmit interfaces 9,10 are coupled to a scheduler 11 which controls the manner in which data is transferred to the transmit interface 9 from the memory interface 7 and from the receive interface 10 to the memory interface 7. Any data to be transmitted which is not transferred immediately is temporarily stored in the buffer memory 8. The receive and transmit interfaces 9,10 are coupled to the network 2 via the network interface 12.

Each adaptor A,B consists of a bus 20A,20B which is connected to the host processor 3. Also coupled to the bus 20A,20B is a transmit FIFO memory 21A,21B and a receive FIFO memory 22A,22B. These are coupled to respective frame transmitters 23A,23B and frame receivers 24A,24B which are connected to the memory interface 7. Operation of the end station 1 will now be described for the transmission of data from the host processor 3 to the network 2.

Data from the host processor 3 is transferred to the network 2 via the interface card 6. This data will generally include at least two types of data. High priority data, which is data such as voice or video communication data generated by the communication device 5 which requires a high bandwidth and/or low latency for transmission and other lower priority data, which is data requiring a lower latency for transmission that may be generated for example by applications operated by the host processor 3. Each type of data will generally be designated to one of the two adaptors A,B by the host processor 3 such that the high priority data is designated to one adapter whilst the remaining adapter is used for any other lower priority data, as will be explained in more detail below.

Operation of one of the adaptors A,B will now be explained, both of the adaptors operating in the same manner.

In transmit mode, data is transferred from the host processor 3 via the bus 20A to the transmit FIFO 21A. The FIFO 21A is a first in/first out memory that acts as a buffer to temporarily store data before it is transferred to the frame transmitter 23A. The frame transmitter 23A and the FIFO 21A act in conjunction to segment the data stream received from the host processor 3 into discrete packets or cells of a size suitable for transmission over the communications network 2, e.g. 48 byte data cells in support of ATM transmission.

This is done by having the frame transmitter 23A gradually build up a data cell as the data is transferred from the FIFO 21A. When the cell is completed, transfer of data from the FIFO 21A is halted while the frame transmitter 23A transfers the cell to the memory interface 7. Once this has been completed, the FIFO 21A will resume the data transfer and the frame transmitter will begin forming the next cell.

Simultaneously, the frame transmitter 23A sends a

^" signal to the scheduler 11 indicating that data for transmission is being passed to the memory interface 7. The scheduler 11 then prioritises the data received from the adaptors A,B at the memory interface 7. This is done such that the high priority data, such as voice or video communications data which requires a high bandwidth and/or low latency for transmission will be transmitted to the network interface 2 in preference to any lower priority data. The lower priority data received by the memory interface 7 will be temporarily stored in the memory 8 until such time as there is sufficient bandwidth available to transmit the data to the communications network 2 without affecting the transmission of the high priority data.

The memory interface 7 will transfer the data to be transmitted to the communications network 2 from either the adaptor A,B or the memory 8 to the transmit interface 9. The transmit interface 9 then adds on any necessary headers etc that are required for the data to be transmitted over the communications network 2 in accordance with the relevant network protocol and forwards the data via the network interface 12 to the network. The receive operation of the network will now be described. Data is received from the communications network 2 and is passed via the network interface 12 to the receive interface 10. The receive interface 10 removes the appropriate headers etc. from the incoming data packets to leave the data in a format suitable for the host processor 3. The data, which is now in the form of headerless cells is transferred to the memory interface 7.

The receive interface 10 also detects the type of data that is received from the communications network 2 and passes this information to the scheduler 11. This allows the scheduler to control the flow of data through the memory interface 7 to prevent the interface becoming overloaded.

The memory interface 7 will then pass the data to the respective adaptor A,B depending on the nature of the data. Thus if the data is voice or video communication data it will be passed to, for example, adaptor A, whilst if it is other non-communication data it will be passed to, for example, the adaptor B. Once received by one of the adaptors A,B the data is passed to the frame receiver 24A,24B. This acts in conjunction with the receive FIFO 22A,22B to reassemble the data packets into a stream of data which is then transferred to the host processor 3 via the bus 20A,20B. Operation of the scheduler 11 will now be described in more detail. As mentioned above, the data for transfer to the network is generally designated to one of the two adapters A,B by the host processor 3. This may be achieved in a number of ways and will depend on the protocol being implemented in the communications network.

Thus, in the case of ATM networks for example, this is achieved by assigning each set of data being transferred to a respective virtual channel. This virtual channel, which may be assigned by the host processor 3 or the respective device 4, 5 which generates the data, is created by an exchange of initialisation data packets which are transferred over the network between the end station 1, and an end station which is to receive the data (not shown) . The initialisation data packets include an indication that a virtual channel is to be set up, along with an indication of the transfer parameters that must be satisfied in order to obtain the desired quality of service (QoS) for the data transfer. These transfer parameters will usually include information concerning the transfer bit rate, latency and bandwidth required by the data, along with an indication of the traffic class and the transfer priority of the data. Examples of traffic classes are Unspecified Bit Rate (UBR) , Constant Bit Rate (CBR) , Variable Bit Rate (VBR) and Available Bit Rate (ABR) . Typically, CBR has highest priority.

The frame transmitter 23A detects the initialization data packet that confirms the establishment of a virtual channel. This will also include an indication of the transfer parameters which are to be used and this information is passed on from the frame transmitter 23A,23B to the scheduler 11. The transfer of data is then achieved by providing an indication of the virtual channel which the data is associated with, within the data to be transferred. Upon transfer of a data packet from the frame transmitter 23A,23B to the memory interface 7 the indication of the respective virtual channel associated with the data is transferred to the scheduler 11 which enables the scheduler to determine the transfer parameters of the data.

Alternatively, the host processor 3 could simply assign the data to be transferred to a respective adapter A,B. An indication of the transfer parameters for each respective connection A,B is then sent to the scheduler 11, either via a direct connection from the host processor the scheduler 11 or alternatively via a data packet which is transferred by the respective frame transmitter 23A,23B. A further alternative is for each data packet to be transferred to include a separate set of transfer criteria. The remainder of the description will focus on the use of virtual channels but it will be appreciated that the apparatus configuration could be adapted to operate according to any of the methods described above. As mentioned above, sets of data from the host processor 3 are transferred to one of the adaptors A,B in the form of a data stream. The frame transmitter 23A,23B and the FIFO 21A,21B cooperate to segment the data stream into a series of packets or ATM cells for transfer over the network 2. These packets or cells are then transferred via the memory interface 7 into the buffer memory 8. In the case of ATM, for example, these would generally comprise 48 byte cells. As the packets are transferred to the memory interface 7, the frame transmitter 23A,23B sends a signal to the scheduler 11 indicating that data to be sent is currently stored in the memory 8, along with an indication of the virtual channel (VC) on which the data is to be sent .

The scheduler 11 uses the virtual channel information to associate the data with the respective transfer parameters required for the data transfer, including the transfer priority and traffic class of the data that was defined by the quality of service information.

The scheduler 11 will then schedule the data for transfer to the communications network 2. When the appropriate time arrives, the scheduler 11 will send an indication to the transmit interface 9 to download the data from the memory 8 via the memory interface 7. A 5 byte ATM header and check sum field will then be added to the data by the transmit interface 9 and the complete cell is then transferred via the network interface 12 to the communications network 2.

Figure 2 shows, in more detail, the arrangement of the scheduler 11. As shown, the scheduler 11 comprises a processor 13 and eight timers or "tickers" 15₀ to 15₇. Each ticker 15 is a counter which repeatedly counts down at a certain rate. The configuration of the external memory 8 is shown in more detail in Figure 4. A region 50 is provided for storing data cells for transmission, a region 51 for storing received data cells prior to transmission to the host, and a region 52 for storing channel descriptors. The format of the channel descriptors will be described in more detail below.

The memory 8 also stores the 5 byte ATM headers which are to be appended to each cell by the transmit interface 9. When a virtual channel is initially set up, the processor 13 within the scheduler 12 determines from the transfer parameters, to which ticker 15 the channel on which the data is to be sent should be allocated.

Each of the eight tickers 15₀ to 15₇ has a respective priority status indicated by a priority number ranging from 0 to 7 inclusive, with 0 representing the lowest priority status and 7 the highest. Each ticker also generates a transfer ready signal at a fixable frequency, which may be altered by the host processor 3. This is used to initiate transfer of data associated with that particular ticker. Typically, the higher the ticker frequency, the higher its priority status.

The scheduler 11 assigns each virtual channel to one of the tickers 15₀ to 15₇ on the basis of the predetermined frequency and the priority status associated with the ticker and the transfer parameters of the data to be transmitted on that channel. Thus, for example, if the data to be sent has a high bandwidth requirement, the corresponding channel will be allocated to a ticker with a high priority number and a high predetermined frequency. This means that the data from this ticker will be sent in preference to data from a lower priority ticker and that the ticker will generate signals for initiating data transfer more frequently than tickers with a lower predetermined frequency. The assignment of data to a particular ticker will also depend on the current utilisation of the remaining tickers and the relative priority of the remaining data to be sent.

In this invention, more than one channel can be allocated to a single ticker 15, and in this case a link- list is generated for that ticker defining the order in which the channels should be transmitted.

An example of such a link-list is shown in Figure 3. The link-list is simply a list of all the virtual channels assigned to any particular ticker 15. Thus, as shown in Figure 3, the ticker 15₀ has assigned to it the channels A, B, C, D and E. The ticker 15₀ will include a pointer represented by the arrow PTR indicating the virtual channel on the link- list from which data was last sent.

The link-list is maintained by storing per channel information in the memory portion 52. The format of this information is shown in Figure 4. For each channel there are two pointer fields, namely a forward pointer field 40 and a backward pointer field 41, a first channel field 42, and a spare field 43. The forward pointer field 40 provides an indication of the virtual channel preceding the respective channel on the link-list. Thus, for example, the channel information associated with virtual channel c would have a forward pointer field 40 indicating virtual channel B. In the case of channel A, the forward pointer field 40 would indicate virtual channel E.

The backward pointer 41 similarly indicates the virtual channel following the respective virtual channel of the link-list. In the case of virtual channel C the backward pointer 41 would indicate virtual channel D.

The first channel field 42 merely indicates whether the virtual channel is the first virtual channel on the link- list. Thus, only the set of data associated with virtual channel A would have an indication entered in the first channel field 42.

In order to add a virtual channel to the link-list, it is merely necessary to up date the channel information of the channels on either side of where the new channel is to be added. Thus, for example, if a new channel X were to be added between channels A and B, the processor 13 of the scheduler 11 would change the backward pointer field 41 of the information associated with the virtual channel A to indicate the virtual channel X as opposed to the virtual channel B. The forward pointer field 40 of the information associated with the virtual channel B would be changed to indicate channel X as opposed to virtual channel A. The information associated with virtual channel X would then be created having a forward pointer field 40 and a backward pointer field 41 indicating virtual channels A and B respectively.

In general, any new channel will be added to the link- list immediately after the current position of the pointer PTR. Alternatively, however, it is also possible to add the channel into the link-list directly after the first channel, as shown in the example in Figure 3.

The operation for removing a virtual channel from the link-list is simply the reverse process in that the forward and backward pointer fields 40,41 of the channel information associated with virtual channels A and B would be amended to no longer refer to virtual channel X but to the respective virtual channels B or A. The only complication to this is when the first channel on the link-list is removed in which case the second channel on the link-list has its information amended to indicate that it is now the first channel. Thus, for example, if the virtual channel A was removed from the link-list, the first field 42 of the channel information of virtual channel B would be amended to include an indication that the channel is now the first on the link-list.

It will now be understood that during normal operation of the scheduler 11 one or more tickers 15 will have associated therewith a respective link-list defining virtual channels to which data is assigned for transfer. Any channels to which no data are assigned, are not included on any of the link-lists. This prevents time when data could be sent being wasted by allocating time to a virtual channel along which no data is to be sent .

As mentioned above, each of the eight tickers 15₀ to 15₇ will periodically generate transfer ready signals which place the ticker in a transfer ready state. The frequency at which this occurs is generally controlled by the host processor 3.

In operation, the tickers 15 repeatedly count down to zero and when reaching zero issue a transfer ready signal which, in practice, involves setting an expire bit to "1".

The timing is selected such that some data (at least an ATM cell, for example) for all channels allocated to a ticker can be transmitted during the count down period of that ticker. The processor 13 constantly monitors all the tickers 15₀ to 15₇ to detect which tickers are currently in a transfer ready state. It will then select the ticker with the highest priority number i.e. the ticker with the highest priority status (for example the ticker 15₇) , and initiate the transfer of a data cell frame each set of data cells associated with the virtual channels assigned to the selected ticker.

To transfer data, the processor 13 determines the next channel in the appropriate link- list and sends a signal to the transmit interface 9. The transmit interface 9 then causes the memory interface 7 to download from the memory

8 a predetermined quantity of data allocated to the selected channel and indicated as the next data to send on that channel. This data is transferred to the transmit interface 9. This predetermined quantity of data will usually be a single cell or packet for transfer to the communications network 2. The transmit interface 9 will then add the appropriate ATM header to the packet of data and transfer the packet of data to the communications network 2.

Whilst the transmit interface 9 is performing this operation, the processor 13 will use the channel information associated with the virtual channel along which data has been sent to determine which is the next virtual channel on the link-list. It will then proceed to transfer a predetermined quantity of data on this virtual channel from the set of data associated with this virtual channel. In this manner the processor 13 attempts to sent at least some data from all the virtual channels associated with the selected ticker which has the highest priority number and is in a transfer ready state. Once a complete set of channels within the link- list has been accessed and the appropriate data sent, the scheduler 11 will reset the expired bit of that ticker to "0" constituting the generation of a transfer complete signal . If, while data is being transmitted under the control of the ticker 15, another ticker, e.g. the ticker 15₀ counts down to zero and sets its expired bit to "1", this will be ignored by the processor 13 since the priority status of the ticker 15₇ is greater than that of the ticker 15₀.

On the other hand, if a ticker having a higher priority than that of the ticker currently transmitting counts down to zero, then the processor 13 will stop sending data associated with the first ticker and start sending data associated with the second ticker. When the predetermined quantity of data has been sent for each of the virtual channels associated with the second ticker, the second ticker will generate a transfer complete signal causing the ticker to exit the transfer ready state. The processor 13 will then return to transmitting the data of the virtual channels remaining on the link-list associated with the first ticker. It will detect from the position of the pointer the channel from which data was last sent and it will then resume sending data from subsequent channels on the link-list.

In such circumstances, it is quite possible that some of the low priority tickers may not get the opportunity to send data because the higher priority tickers have too much data to send. This may occur, for example, if a ticker 15 has a frequency such that a transfer ready signal is generated within a time period less than that taken to send all the data associated with a single pass through the link-list of the ticker. If this ticker is the ticker with the highest priority, this would result in data being transferred from the ticker constantly with no data being transferred from any other ticker. In order to overcome this, when a ticker is currently in the transfer ready state and then attempts to generate a further transfer ready signal, it will enter a second transfer ready state. Typically, an "expired twice" bit will be set for that ticker. This indicates that the ticker has generated at least two transfer ready signals without having generated a transfer complete signal . When the ticker enters the second transfer ready state, the priority number of the ticker is increased such that the priority number is higher than for any other ticker that is not in the second transfer ready state. As a consequence, should for example, the ticker 15₀ enter the second transfer ready state it will then be allocated a priority higher than any other ticker thus causing the processor 13 to transfer data from the ticker 15₀ in preference to any other. An example of the operation of the tickers will now be explained with reference to Table 1 which shows examples of the priority numbers, time periods between generation of transfer ready signals, and the associated link-list for each of the eight tickers 15₀ to 15₇. In the example shown in Table 1, the time period is expressed in terms of T, where T is a notional time period. Each ticker 15 counts down through a certain period of time denoted as a multiple of "T" in Table 1. In this example, ticker 15₇ has the highest priority 7 while ticker 15₀ has the lowest priority 0. Channels have only been allocated to tickers 15_Q, 15₃ and 15₇, the channels being labelled A-N respectively. Table 1

Some examples of the operation of the tickers will now be described with reference to Figures 5a to 5e . These diagrams are a temporal representation of the transmission of data from the interface device, with each block indicating the transmission of the predetermined quantity of data on the respective virtual channel .

The simplest example is shown in Figure 5a, in which only the ticker 15₀ has any virtual channels assigned to it. The ticker 15₀ generates a transfer ready signal at time t=0 and enters the transfer ready state, the expired bit being set to "1". This causes a predetermined quantity of data to be transferred from each set of data assigned to each of the channels A, B, C, D and E. This predetermined quantity is dependent on the communications protocol operated by the network but will in general be a single packet or cell that is stored in the memory 8.

Thus, with only the ticker 15_Q having channels assigned thereto, it will send data every time the ticker generates a transfer ready signal and enters the transfer ready state. When all the data has been sent following a single pass through the link-list, the ticker will generate a transfer complete signal which causes the ticker to exit the transfer ready state and reset the expired bit to "O" . The countdown restarts as soon as the ticker has counted down to zero and the rate of counting and the initial value of the count are chosen so that the next time at which the count reaches zero is at t=4T. Figure 5b shows the equivalent situation in which only the ticker 15₃ has any virtual channels assigned to it.

Figure 5c shows the case where both the tickers 15₀ and 15₃ have the channels assigned to them shown in Table 1. It is assumed that at time t=0, both tickers 15₀ and 15₃ have counted down to zero and set their expired bits to "1". Since the ticker 15₃ has a higher priority than the ticker 15₀, initially the scheduler 11 causes channels F, G and H to be transmitted. Once those channels have been transmitted, the expired bit for the ticker 15₃ is reset. Immediately after transmitting the channels associated with the ticker 15₃, the channels associated with ticker 15₀ are transmitted following which the expired bit for the ticker

15₀ is reset to "0" .

Since the time period of the ticker 15₃ is shorter than the time period for the ticker 15₀, the expired bit of the ticker 15₃ will be set to "1" when t=3T and immediately the three channels F, G and H will be transmitted as shown in Figure 5c. The expired bit of the ticker 15₃ will then be reset to zero. When t=4T, the ticker 15₀ will have counted down to zero again and will set its expired bit to "1" following which the channels A-E will be sent.

Figure 5d shows the situation in which only the ticker 15₇ has virtual channels assigned to it, i.e. channels I-N. As can be seen from Table 1, the ticker 15₇ generates transfer ready signals separated by a time period T. As it takes time T to send the predetermined quantity of data from each channel associated with the ticker, the ticker will generate the transfer complete signal at substantially the same time that the subsequent transfer ready signal is generated. Consequently, the ticker is substantially always in the transfer ready state and data is therefore constantly being sent to the network from the channels associated with the ticker 15₇.

In the example shown in Figure 5e, each of the tickers 15₀, 15₃ and 15₇ has channels assigned thereto, as set out in Table 1.

Initially at time t=0, each of the tickers will generate a transfer ready signal and enter the transfer ready state. As the ticker 15₇ has the highest priority, data will be sent from the sets of data associated with this ticker. As explained with reference to Figure 5d, the ticker 15₇ will generate the transfer complete signal at substantially the same time that the subsequent transfer ready signal is generated. The ticker 15₇ thus remains in the transfer ready state and as it has a higher priority than either of the other tickers, data will again be transferred from the channels associated with the ticker 15₇. The same will occur periodically at intervals of t-T (ie. at t=T, t=2T, t=3T...).

However, at time t=3T, the ticker 15₃, whose expire bit has already been set to "1", will generate a second transfer ready signal and enter the second transfer ready state by setting its expired twice bit to "1". The priority number of the ticker is then increased by the processor 13 to a value greater than that of any other ticker not in the second transfer ready state (e.g. priority number increased to ten) . As a consequence, ticker 15₃ now has the greatest priority number, and data on channels F,G,H is therefore transferred from the sets of data associated with this ticker in preference to all others, as shown. When this data transfer is complete, the ticker 15₃ generates the transfer complete signal and returns to the transfer ready state. The priority number therefore also returns to it's previous value i.e. three. As a consequence, the ticker 15₇ now has the highest priority and will begin to transfer data.

At time t=4T, both tickers 15₀ and 15₇ will generate transfer ready signals and enter the second transfer ready state, their expired twice tickers being set to "1". In this case, both the tickers have their respective priority numbers increased to the same value. As the data associated with the ticker 15₇ was being sent prior to the generation of the signals and the tickers have equal priority afterwards, the scheduler 11 will continue to send data associated with the ticker 15₇

When the timer 15₇ has sent the predetermined quantity of data associated with each virtual channel following a further pass through its link-list, the ticker 15₇ will generate a transfer complete signal and re-enter the transfer ready state. The priority number of the ticker 15₇ is returned to its original value and is then lower than that of ticker 15₀. The data associated with ticker 15₀ will then be sent, as shown.

In circumstances where a ticker, for example ticker 15₇, is in the second transfer ready state and it generates a further transfer ready signal, before the predetermined quantity of data has been sent, it will remain in the second transfer ready state when the transfer complete signal is generated. In order to prevent the transmission of data becoming limited to ticker 15₇ only, upon generation of the transfer complete signal by the ticker 15₇, the processor 13 will determine whether any alternative tickers 15₀ to 15₆ are in the second transfer ready state. If any of the alternative tickers 15₀ to 15₆ are in the second transfer ready state, the processor 13 will select one of the alternative tickers 15₀ to 15₆ for data transfer, in preference to ticker 15₇. The overall effect of this is that the processor will round-robin through all the tickers that are in the second transfer ready state to ensure that data will be sent, at some stage, from all the tickers.

Thus, whilst there are tickers 15 in the transfer ready state and not the second transfer ready state, the processor 13 will select the ticker with the highest priority from those in the transfer ready state. When one ticker only is in the second transfer ready state, the processor will select that ticker. Finally, when more than one ticker is in the second transfer ready state, the processor will round-robin through those tickers to ensure that data associated with all the tickers will be transferred to the communications network 2.

Claims

1. An interface device for connecting a communications network end station to a communications network, the end station having a plurality of data handling devices programmed to cooperate with the interface device to transfer sets of data between each data handling device and the communications network in accordance with respective transfer criteria, wherein the interface device comprises: at least two interface connections, each interface connection being adapted for coupling to any of the data handling devices; and a scheduler, coupled to the interface connections, which controls the transfer of each set of data to the network in accordance with the respective transfer criteria.

2. An interface device according to claim 1, the interface device further comprising a transmit/receive interface for coupling the interface device to the network, wherein the transmit/receive interface modifies the data prior to transfer to the network, and wherein the scheduler controls the transfer of data between the interface connections and the transmit/receive interface.

3. An interface device according to claim 2, the interface device further comprising a store or stores coupled to the interface connections and the transmit/receive interface, wherein the store (s) store data for transfer to or from the interface connections.

4. An interface device according to any of the preceding claims, wherein the scheduler includes a number of timers for controlling the transfer of each set of data from the interface connections to the network, each timer having a respective priority status and a respective transfer ready frequency.

5. An interface device according to claim 4, the scheduler further comprising a processor which associates each set of data with at least one timer in accordance with the transfer criteria.

6. An interface device according to any of the preceding claims, wherein each interface connection comprises an adaptor for segmenting each set of data received from a data handling device into a number of discrete data packets.

7. An interface device according to claim 6, when connected to a communications network, each set of data being transferred from the interface device to the communications network via a respective virtual channel, the virtual channel being established by a transfer of initialization data from the end station to the communications network, the initialization data including the transfer criteria of the respective set of data, wherein each adaptor is adapted to detect and transfer the transfer criteria to the scheduler.

8. An interface device according to claim 7, each set of data being transferred from each data handling device including a channel indicator indicating the virtual channel via which the respective set of data is to be sent, and wherein the adaptor is adapted to detect and transfer the channel indicator to the scheduler.

9. An interface device according to claim 8, when dependent on claim 5, wherein the processor associates each set of data with at least one timer by assigning each virtual channel to a respective timer and associating the each set of data with the respective virtual channel using the channel indicator.

10. An interface device according to claim 6, wherein each set of data transferred from each data handling device includes a criteria indicator indicating the respective transfer criteria of the set of data, and wherein each adaptor includes a detector which detects and transfers the criteria indicator to the scheduler.

11. An interface device according to any of claims 6 to 10, wherein each adaptor comprises a frame receiver for coupling to a respective data handling device, wherein the frame receiver receives data packets and reassembles the discrete data packets into a data stream for transfer to the data handling devices; and a frame transmitter for coupling to a respective data handling device, the frame transmitter receiving the data stream from the respective data handling device and segmenting the data stream into discrete data packets.

12. An interface device according to claim 4, wherein the adaptors reassemble discrete data packets received from the network into a data stream for transfer to the data handling devices.

13. An interface device according to any of the preceding claims, when connected to an end station, the end station comprising a host processor coupled to the interface connections, wherein each data handling device is coupled to the respective interface connection via the host processor.

14. A method of connecting a communications network end station to a communications network using an interface device, the end station having a plurality of data handling devices programmed to cooperate with the interface device to transfer a set of data between each data handling device and a communications network in accordance with respective transfer criteria, the interface device including a plurality of interface connections, for coupling to any of the data handling devices, the method comprising causing the interface connections to receive data from any one of the data handling devices, and controlling the transfer of each set of data to the network in accordance with the predetermined transfer criteria.

15. A method according to claim 14, the method further comprising segmenting each set of data received from a data handling device into a number of discrete data packets.

16. A method according to claim 14 or claim 15, wherein the interface device includes a scheduler having a number of timers for controlling the transfer of data, each timer having a respective priority status and a respective transfer ready frequency, the method further comprising associating each set of data to at least one of the timers in accordance with the transfer criteria.

17. A method according to any of claim 16, wherein when the interface device is connected to a communications network, each set of data is transferred from the interface device to the communications network via a respective virtual channel, the method further comprising establishing a virtual channel by transferring initialization data from the end station to the communications network, the initialization data including the transfer criteria of the respective set of data, and causing the interface device to detect and transfer the transfer criteria to the scheduler.

18. A method according to claim 17, wherein each set of data being transferred from each data handling device includes a channel indicator indicating the virtual channel via which the respective set of data is to be sent, the method further comprising causing the interface device to detect and transfer the channel indicator to the scheduler.

19. A method according to claim 18, wherein the method of associating each set of data with at least one timer comprises assigning each virtual channel to a respective timer and associating the each set of data with the respective virtual channel using the channel indicator.