WO1999010923B1 - Method for selective plasma etch - Google Patents

Method for selective plasma etch

Info

Publication number
WO1999010923B1
WO1999010923B1 PCT/US1998/017607 US9817607W WO9910923B1 WO 1999010923 B1 WO1999010923 B1 WO 1999010923B1 US 9817607 W US9817607 W US 9817607W WO 9910923 B1 WO9910923 B1 WO 9910923B1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
gas
dielectric layer
selectivity
seem
Prior art date
Application number
PCT/US1998/017607
Other languages
French (fr)
Other versions
WO1999010923A1 (en
Inventor
Helen H Zhu
George A Mueller
Thomas D Nguyen
Lumin Li
Original Assignee
Lam Res Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lam Res Corp filed Critical Lam Res Corp
Priority to EP98944527A priority Critical patent/EP1012877A1/en
Priority to KR1020007002106A priority patent/KR100563969B1/en
Priority to JP2000508137A priority patent/JP2001514447A/en
Publication of WO1999010923A1 publication Critical patent/WO1999010923A1/en
Publication of WO1999010923B1 publication Critical patent/WO1999010923B1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching

Abstract

Disclosed is a method for improving the selectivity of dielectric layers to photoresist layers and base layers. The method is performed in a plasma processing chamber, and the photoresist layer is coated over the dielectric layer. The method includes introducing an etchant source gas into the plasma processing chamber, which consists essentially of a CxFy gas and an N2 gas. The method further includes striking a plasma in the plasma processing chamber from the etchant source gas. The method additionally includes etching at least a portion of the dielectric layer with the plasma through to a base layer that underlies the dielectric layer. The method is also well suited for anisotropically etching an oxide layer with very high selectivities to Si, Si3N4, TiN, and metal silicides.

Claims

AMENDED CLAIMS[received by the International Bureau on 8 March 1999 (08.03.99); original claims 1-28 replaced by amended claims 1-18 (6 pages)]
1. In a plasma processing chamber, a method for etching through a selected portion of a dielectric layer of a wafer, comprising:
introducing an etchant source gas into the plasma processing chamber, the etchant source gas consisting essentially of a CxFy gas and an N2 gas;
striking a plasma in the plasma processing chamber from the etchant source gas;
etching at least partially through the dielectric layer with said plasma; and
selecting one of the following gas flow rates: flowing the C2F6 gas at a flow rate of between about 2 and about 20 standard cubic centimeters per minute (seem); flowing the
C4F8 gas at a flow rate of between about 2 and about 15 standard cubic centimeters per minute (seem); and flowing the C3F6 gas at a flow rate of between about 2 and about 15 standard cubic centimeters per minute (seem).
2. A method for etching as recited in claim 1, further comprising:
flowing the N2 gas at a flow rate of between about 10 and about 100 standard cubic centimeters per minute (seem).
3. A method for etching as recited in claim 2, wherein the dielectric layer is one of a doped and undoped dielectric material that is selected from the group consisting of a silicon dioxide (SiO2) layer, a borophosphosilicate glass (BPSG) layer, a phosphosilicate glass (PSG), a tetra-ethyl-otho-silicate (TEOS).
28
4. A method for etching as recited in claim 3, further comprising:
flowing an argon (Ar) gas having a flow rate of between about 0 and 400 standard cubic centimeters per minute (seem) into the plasma processing chamber.
5. A method for etching as recited in claim 4, wherein a chamber pressure within said plasma processing chamber is between about 15 mTorr and about 100 mTorr during the etching.
6. A method for etching as recited in claim 4, wherein a chamber temperature within the plasma processing chamber is between about 10 degrees Celsius and about 50 degrees Celsius.
7. In a plasma processing chamber, a method for improving a selectivity of a dielectric layer to a photoresist layer and to a base layer, wherein the photoresist layer is coated over the dielectric layer, comprising:
introducing an etchant source gas into the plasma processing chamber, the etchant gas consists essentially of a CxFy gas and an N2 gas;
striking a plasma in the plasma processing chamber from the etchant source gas;
etching at least a portion of the dielectric layer with the plasma through to the base layer that underlies the dielectric layer; and
selecting one of the following gas flow rates: flowing the C2F6 gas at a flow rate of between about 2 and about 20 standard cubic centimeters per minute (seem); flowing the C4Fg gas at a flow rate of between about 2 and about 15 standard cubic centimeters per
29 minute (seem); and flowing the C3F6 gas at a flow rate of between about 2 and about 15 standard cubic centimeters per minute (seem).
8. A method for etching as recited in claim 7, further comprising:
flowing the N2 gas at a flow rate of between about 10 and about 100 standard cubic centimeters per minute (seem).
9. The method for improving a selectivity of a dielectric layer to a photoresist layer and to a base layer as recited in claim 8, further comprising:
flowing an argon (Ar) gas having a flow rate of between about 0 and 400 standard cubic centimeters per minute (seem) into the plasma processing chamber.
10. The method for improving a selectivity of a dielectric layer to a photoresist layer and to a base layer as recited in claim 9, further comprising:
producing an etch ratio selectivity of at least about (7:1) for the dielectric layer to the photoresist layer.
11. The method for improving a selectivity of a dielectric layer to a photoresist layer and to a base layer as recited in claim 10, wherein the base layer that underlies the dielectric layer is selected from the group consisting of a titanium-silicide (TSi2) layer, a titanium-nitride (TiN) layer, a tungsten-silicide (WSi2) layer, a silicon layer, a polysilicon layer, a silicon-nitride (Si3N4) layer, and an aluminum/copper (Al/Cu) layer.
30
12. The method for improving a selectivity of a dielectric layer to a photoresist layer and to a base layer as recited in claim 11 , wherein the plasma further improves a selectivity of the dielectric to the base layer.
13. The method for improving a selectivity of a dielectric layer to a photoresist layer and to a base layer as recited in claim 12, further comprising one of the following operations:
producing an etch ratio selectivity of at least about (40:1) for the dielectric layer to the titanium-silicide layer;
producing an etch ratio selectivity of at least about (40: 1) for the dielectric layer to the tungsten-silicide layer;
producing an etch ratio selectivity of at least about (50:1) for the dielectric layer to the silicon layer;
producing an etch ratio selectivity of at least about (50:1) for the dielectric layer to the polysilicon layer;
producing an etch ratio selectivity of at least about (20: 1) for the dielectric layer to the silicon-nitride layer; and
producing an etch ratio selectivity of at least about (50:1) for the dielectric layer to the aluminum/copper layer.
14. The method for improving a selectivity of a dielectric layer to a photoresist layer and to a base layer as recited in claim 13, wherein holes selected form the group
31 consisting of via holes and contact holes are defined through the dielectric layer without excessively removing the photoresist layer or the base layer.
15. In a plasma processing chamber, a method for improving a selectivity of a dielectric layer to a photoresist layer and a base layer, wherein the photoresist layer is coated over the dielectric layer, comprising:
introducing an etchant source gas into the plasma processing chamber, the etchant gas being selected from a group consisting of a C2F6 gas, a C4F8 gas, or a C3F6 gas, and an N2 gas and an Ar gas;
striking a plasma in the plasma processing chamber from the etchant source gas;
etching a high aspect ratio via hole through the dielectric layer with the plasma down to the base layer that underlies the dielectric layer; and
selecting one of the following gas flow rates: flowing the C2F6 gas at a flow rate of between about 2 and about 20 standard cubic centimeters per minute (seem); flowing the C4F8 gas at a flow rate of between about 2 and about 15 standard cubic centimeters per minute (seem); and flowing the C3F6 gas at a flow rate of between about 2 and about 15 standard cubic centimeters per minute (seem).
16. The method for improving a selectivity of a dielectric layer to a photoresist layer and a base layer as recited in claim 15, further comprising:
producing an etch ratio selectivity of at least about (7:1) for the dielectric layer to the photoresist layer.
32
17. The method for improving a selectivity of a dielectric layer to a photoresist layer and a base layer as recited in claim 16, further comprising:
flowing the N2 gas at a flow rate of between about 10 and about 100 standard cubic centimeters per minute (seem).
18. The method for improving a selectivity of a dielectric layer to a photoresist layer and a base layer as recited in claim 17, further comprising:
flowing the argon (Ar) gas to a flow rate of between about 0 and 400 standard cubic centimeters per minute (seem) into the plasma processing chamber.
33
PCT/US1998/017607 1997-08-28 1998-08-25 Method for selective plasma etch WO1999010923A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP98944527A EP1012877A1 (en) 1997-08-28 1998-08-25 Method for selective plasma etch
KR1020007002106A KR100563969B1 (en) 1997-08-28 1998-08-25 Method for selective plasma etch
JP2000508137A JP2001514447A (en) 1997-08-28 1998-08-25 Method for selective plasma etching

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/919,659 US6090304A (en) 1997-08-28 1997-08-28 Methods for selective plasma etch
US08/919,659 1997-08-28

Publications (2)

Publication Number Publication Date
WO1999010923A1 WO1999010923A1 (en) 1999-03-04
WO1999010923B1 true WO1999010923B1 (en) 1999-05-14

Family

ID=25442429

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1998/017607 WO1999010923A1 (en) 1997-08-28 1998-08-25 Method for selective plasma etch

Country Status (6)

Country Link
US (1) US6090304A (en)
EP (1) EP1012877A1 (en)
JP (1) JP2001514447A (en)
KR (1) KR100563969B1 (en)
TW (1) TW538479B (en)
WO (1) WO1999010923A1 (en)

Families Citing this family (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6423646B1 (en) * 1998-06-04 2002-07-23 Vanguard International Semiconductor Corporation Method for removing etch-induced polymer film and damaged silicon layer from a silicon surface
JP3241020B2 (en) * 1999-03-26 2001-12-25 日本電気株式会社 Method for manufacturing semiconductor device
JP2002270586A (en) * 2001-03-08 2002-09-20 Tokyo Electron Ltd Etching method of organic based insulating film and dual damascene process
US6630407B2 (en) 2001-03-30 2003-10-07 Lam Research Corporation Plasma etching of organic antireflective coating
US6962879B2 (en) * 2001-03-30 2005-11-08 Lam Research Corporation Method of plasma etching silicon nitride
US6617257B2 (en) 2001-03-30 2003-09-09 Lam Research Corporation Method of plasma etching organic antireflective coating
US6670278B2 (en) 2001-03-30 2003-12-30 Lam Research Corporation Method of plasma etching of silicon carbide
US7311852B2 (en) * 2001-03-30 2007-12-25 Lam Research Corporation Method of plasma etching low-k dielectric materials
US20020177321A1 (en) * 2001-03-30 2002-11-28 Li Si Yi Plasma etching of silicon carbide
US7084070B1 (en) 2001-03-30 2006-08-01 Lam Research Corporation Treatment for corrosion in substrate processing
JP2002319551A (en) * 2001-04-23 2002-10-31 Nec Corp Semiconductor device and its manufacturing method
US6746961B2 (en) 2001-06-19 2004-06-08 Lam Research Corporation Plasma etching of dielectric layer with etch profile control
TW567554B (en) * 2001-08-08 2003-12-21 Lam Res Corp All dual damascene oxide etch process steps in one confined plasma chamber
US6686293B2 (en) 2002-05-10 2004-02-03 Applied Materials, Inc Method of etching a trench in a silicon-containing dielectric material
KR20030096832A (en) * 2002-06-18 2003-12-31 동부전자 주식회사 Method for etching insulator film of semiconductor device
US7541270B2 (en) * 2002-08-13 2009-06-02 Micron Technology, Inc. Methods for forming openings in doped silicon dioxide
US6838012B2 (en) 2002-10-31 2005-01-04 Lam Research Corporation Methods for etching dielectric materials
US20040118344A1 (en) * 2002-12-20 2004-06-24 Lam Research Corporation System and method for controlling plasma with an adjustable coupling to ground circuit
US7098141B1 (en) 2003-03-03 2006-08-29 Lam Research Corporation Use of silicon containing gas for CD and profile feature enhancements of gate and shallow trench structures
JP2004296835A (en) * 2003-03-27 2004-10-21 Applied Materials Inc Method for constructing damascene structure
US6949460B2 (en) * 2003-11-12 2005-09-27 Lam Research Corporation Line edge roughness reduction for trench etch
US7517801B1 (en) 2003-12-23 2009-04-14 Lam Research Corporation Method for selectivity control in a plasma processing system
US7521362B2 (en) * 2003-12-23 2009-04-21 Lam Research Corporation Methods for the optimization of ion energy control in a plasma processing system
US20050153563A1 (en) * 2004-01-14 2005-07-14 Lam Research Corporation Selective etch of films with high dielectric constant
US8222155B2 (en) * 2004-06-29 2012-07-17 Lam Research Corporation Selectivity control in a plasma processing system
US20060043066A1 (en) * 2004-08-26 2006-03-02 Kamp Thomas A Processes for pre-tapering silicon or silicon-germanium prior to etching shallow trenches
US7244311B2 (en) * 2004-10-13 2007-07-17 Lam Research Corporation Heat transfer system for improved semiconductor processing uniformity
US7226869B2 (en) * 2004-10-29 2007-06-05 Lam Research Corporation Methods for protecting silicon or silicon carbide electrode surfaces from morphological modification during plasma etch processing
US7291286B2 (en) * 2004-12-23 2007-11-06 Lam Research Corporation Methods for removing black silicon and black silicon carbide from surfaces of silicon and silicon carbide electrodes for plasma processing apparatuses
US7480974B2 (en) * 2005-02-15 2009-01-27 Lam Research Corporation Methods of making gas distribution members for plasma processing apparatuses
US7430986B2 (en) 2005-03-18 2008-10-07 Lam Research Corporation Plasma confinement ring assemblies having reduced polymer deposition characteristics
WO2006114976A1 (en) * 2005-03-30 2006-11-02 Matsushita Electric Industrial Co., Ltd. Plasma doping method and plasma processing equipment
US7713379B2 (en) 2005-06-20 2010-05-11 Lam Research Corporation Plasma confinement rings including RF absorbing material for reducing polymer deposition
US20070032081A1 (en) * 2005-08-08 2007-02-08 Jeremy Chang Edge ring assembly with dielectric spacer ring
US8263498B2 (en) * 2006-03-28 2012-09-11 Tokyo Electron Limited Semiconductor device fabricating method, plasma processing system and storage medium
US8635971B2 (en) * 2006-03-31 2014-01-28 Lam Research Corporation Tunable uniformity in a plasma processing system
US7829468B2 (en) * 2006-06-07 2010-11-09 Lam Research Corporation Method and apparatus to detect fault conditions of plasma processing reactor
US7517804B2 (en) * 2006-08-31 2009-04-14 Micron Technologies, Inc. Selective etch chemistries for forming high aspect ratio features and associated structures
US8313612B2 (en) * 2009-03-24 2012-11-20 Lam Research Corporation Method and apparatus for reduction of voltage potential spike during dechucking
DE202010015933U1 (en) * 2009-12-01 2011-03-31 Lam Research Corp.(N.D.Ges.D.Staates Delaware), Fremont An edge ring arrangement for plasma etching chambers
US8249900B2 (en) * 2010-02-10 2012-08-21 Morgan Stanley & Co. Llc System and method for termination of pension plan through mutual annuitization
US8826855B2 (en) 2010-06-30 2014-09-09 Lam Research Corporation C-shaped confinement ring for a plasma processing chamber
US8485128B2 (en) 2010-06-30 2013-07-16 Lam Research Corporation Movable ground ring for a plasma processing chamber
US9171702B2 (en) 2010-06-30 2015-10-27 Lam Research Corporation Consumable isolation ring for movable substrate support assembly of a plasma processing chamber
US9728429B2 (en) 2010-07-27 2017-08-08 Lam Research Corporation Parasitic plasma prevention in plasma processing chambers
US9859142B2 (en) 2011-10-20 2018-01-02 Lam Research Corporation Edge seal for lower electrode assembly
US9869392B2 (en) 2011-10-20 2018-01-16 Lam Research Corporation Edge seal for lower electrode assembly
US8844106B2 (en) 2011-11-10 2014-09-30 Lam Research Corporation Installation fixture for elastomer bands and methods of using the same
US8677586B2 (en) 2012-04-04 2014-03-25 Lam Research Corporation Installation fixture for elastomer bands and methods of using the same
DE102012106518A1 (en) * 2012-07-18 2014-01-23 H2 Solar Gmbh Coating of substrates with silicides and their oxides
US9018022B2 (en) 2012-09-24 2015-04-28 Lam Research Corporation Showerhead electrode assembly in a capacitively coupled plasma processing apparatus
US9502279B2 (en) 2013-06-28 2016-11-22 Lam Research Corporation Installation fixture having a micro-grooved non-stick surface
US9123661B2 (en) 2013-08-07 2015-09-01 Lam Research Corporation Silicon containing confinement ring for plasma processing apparatus and method of forming thereof
US9583377B2 (en) 2013-12-17 2017-02-28 Lam Research Corporation Installation fixture for elastomer bands
US10090211B2 (en) 2013-12-26 2018-10-02 Lam Research Corporation Edge seal for lower electrode assembly
WO2017123423A1 (en) * 2016-01-13 2017-07-20 Applied Materials, Inc. Hydrogen plasma based cleaning process for etch hardware
JP7228989B2 (en) * 2018-11-05 2023-02-27 東京エレクトロン株式会社 PLACE, EDGE RING POSITIONING METHOD, AND SUBSTRATE PROCESSING APPARATUS
WO2021217056A1 (en) * 2020-04-23 2021-10-28 Akash Systems, Inc. High-efficiency structures for improved wireless communications

Family Cites Families (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54125979A (en) * 1978-03-24 1979-09-29 Hitachi Ltd Manufacture of semiconductor device
US4267012A (en) * 1979-04-30 1981-05-12 Fairchild Camera & Instrument Corp. Process for patterning metal connections on a semiconductor structure by using a tungsten-titanium etch resistant layer
JPS56111222A (en) * 1980-01-31 1981-09-02 Chiyou Lsi Gijutsu Kenkyu Kumiai Dry etching method on silicon nitride film
JPS5860611A (en) * 1981-10-06 1983-04-11 Canon Inc Dry etching of amorphous hydrogenated silicon
US4412885A (en) * 1982-11-03 1983-11-01 Applied Materials, Inc. Materials and methods for plasma etching of aluminum and aluminum alloys
US4740485A (en) * 1986-07-22 1988-04-26 Monolithic Memories, Inc. Method for forming a fuse
JPS63230889A (en) * 1987-03-20 1988-09-27 Toshiba Corp Production of substrate
US4878994A (en) * 1987-07-16 1989-11-07 Texas Instruments Incorporated Method for etching titanium nitride local interconnects
JPH01214025A (en) * 1988-02-22 1989-08-28 Nec Yamagata Ltd Manufacture of semiconductor device
DE3842758A1 (en) * 1988-12-19 1990-06-21 Siemens Ag Process for etching a three-layer interconnection level in the production of integrated semiconductor circuits
JP2528962B2 (en) * 1989-02-27 1996-08-28 株式会社日立製作所 Sample processing method and device
US5429070A (en) * 1989-06-13 1995-07-04 Plasma & Materials Technologies, Inc. High density plasma deposition and etching apparatus
US4980018A (en) * 1989-11-14 1990-12-25 Intel Corporation Plasma etching process for refractory metal vias
JP2519364B2 (en) * 1990-12-03 1996-07-31 アプライド マテリアルズ インコーポレイテッド Plasma reactor using UHF / VHF resonant antenna source
US5217570A (en) * 1991-01-31 1993-06-08 Sony Corporation Dry etching method
US5269879A (en) * 1991-10-16 1993-12-14 Lam Research Corporation Method of etching vias without sputtering of underlying electrically conductive layer
US5296094A (en) * 1992-06-12 1994-03-22 Intel Corporation Process for etching silicon dioxide layer without micro masking effect
KR100293830B1 (en) * 1992-06-22 2001-09-17 리차드 에이치. 로브그렌 Plasma Purification Method for Removing Residues in Plasma Treatment Chamber
US5256245A (en) * 1992-08-11 1993-10-26 Micron Semiconductor, Inc. Use of a clean up step to form more vertical profiles of polycrystalline silicon sidewalls during the manufacture of a semiconductor device
US5326427A (en) * 1992-09-11 1994-07-05 Lsi Logic Corporation Method of selectively etching titanium-containing materials on a semiconductor wafer using remote plasma generation
US5468339A (en) * 1992-10-09 1995-11-21 Advanced Micro Devices, Inc. Plasma etch process
JPH06151382A (en) * 1992-11-11 1994-05-31 Toshiba Corp Dry etching method
US5387556A (en) * 1993-02-24 1995-02-07 Applied Materials, Inc. Etching aluminum and its alloys using HC1, C1-containing etchant and N.sub.2
US5770098A (en) * 1993-03-19 1998-06-23 Tokyo Electron Kabushiki Kaisha Etching process
US5384009A (en) * 1993-06-16 1995-01-24 Applied Materials, Inc. Plasma etching using xenon
JPH0774156A (en) * 1993-08-31 1995-03-17 Nec Corp Manufacture of semiconductor device
US5505816A (en) * 1993-12-16 1996-04-09 International Business Machines Corporation Etching of silicon dioxide selectively to silicon nitride and polysilicon
US5545289A (en) * 1994-02-03 1996-08-13 Applied Materials, Inc. Passivating, stripping and corrosion inhibition of semiconductor substrates
JP2809087B2 (en) * 1994-02-15 1998-10-08 日本電気株式会社 Wiring formation method
US5562801A (en) * 1994-04-28 1996-10-08 Cypress Semiconductor Corporation Method of etching an oxide layer
US5620615A (en) * 1994-05-13 1997-04-15 Micron Technology, Inc. Method of etching or removing W and WSix films
US5496762A (en) * 1994-06-02 1996-03-05 Micron Semiconductor, Inc. Highly resistive structures for integrated circuits and method of manufacturing the same
US5514247A (en) * 1994-07-08 1996-05-07 Applied Materials, Inc. Process for plasma etching of vias
US5935877A (en) * 1995-09-01 1999-08-10 Applied Materials, Inc. Etch process for forming contacts over titanium silicide
US5910453A (en) * 1996-01-16 1999-06-08 Advanced Micro Devices, Inc. Deep UV anti-reflection coating etch
US6004884A (en) * 1996-02-15 1999-12-21 Lam Research Corporation Methods and apparatus for etching semiconductor wafers
US5843847A (en) * 1996-04-29 1998-12-01 Applied Materials, Inc. Method for etching dielectric layers with high selectivity and low microloading
US5719089A (en) * 1996-06-21 1998-02-17 Vanguard International Semiconductor Corporation Method for etching polymer-assisted reduced small contacts for ultra large scale integration semiconductor devices
US5668038A (en) * 1996-10-09 1997-09-16 Taiwan Semiconductor Manufacturing Company, Ltd. One step smooth cylinder surface formation process in stacked cylindrical DRAM products
JPH10125654A (en) * 1996-10-21 1998-05-15 Sharp Corp Manufacture of semiconductor device

Also Published As

Publication number Publication date
WO1999010923A1 (en) 1999-03-04
JP2001514447A (en) 2001-09-11
KR100563969B1 (en) 2006-03-29
KR20010023462A (en) 2001-03-26
EP1012877A1 (en) 2000-06-28
TW538479B (en) 2003-06-21
US6090304A (en) 2000-07-18

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