WO1999016115A1

WO1999016115A1 - Method for producing a semiconductor structure with a plurality of implanted grooves

Info

Publication number: WO1999016115A1
Application number: PCT/DE1998/002783
Authority: WO
Inventors: Thomas Böhm; Manfred Hain; Armin Kohlhase; Yoichi Otani; Andreas Rusch; Alexander Trüby; Ulrich Zimmermann
Original assignee: Siemens Aktiengesellschaft
Priority date: 1997-09-25
Filing date: 1998-09-18
Publication date: 1999-04-01
Also published as: DE19742397C2; DE19742397A1

Abstract

The invention relates to a method for producing a semiconductor structure on the main surface of a substrate (1), comprising a plurality of grooves (2, 3, 4) with corresponding crests (5a, 5b, 5c, 5d), bottoms (2a, 3a, 4a) and walls (2b, 2c; 3b, 3; 4b, 4c). The inventive method consists of the following steps: spacers (6a, 6b; 6c; 6d; 6e, 6f) are formed on the walls of the grooves; predetermined spacers (6c; 6d) are optionally removed to uncover the corresponding walls of said grooves (3b, 3c); at least one implantation is made at a given angle (α', α'') to the normal of the main surface in order to form corresponding conduction areas.

Description

description

METHOD FOR PRODUCING A SEMICONDUCTOR STRUCTURE WITH A MULTIPLE NUMBER OF IMPLANTED TRENCHES

The present invention relates to a method for producing a semiconductor structure, and in particular to a method for producing a semiconductor structure on a main surface of a substrate with a plurality of trenches with corresponding trench crowns, trench bottoms and trench walls.

Although applicable in principle to a wide variety of semiconductor structures, the present invention and the problems on which it is based are described on the basis of a read-only memory cell arrangement with vertical MOS transistors.

A fixed value memory cell arrangement is known from DE 195 10 042 C2, in which longitudinal trenches are provided in a main surface of the semiconductor substrate, said trenches running essentially parallel to the rows. The word lines run transversely to the rows and are each connected to the gate electrodes of MOS transistors of the memory cells arranged along different rows.

Such a fixed value memory cell arrangement with parallel longitudinal trenches makes it possible to reduce the projection of the memory cells onto the main area by up to 50%. A packing density of 3.125 bit / μm ² can thus be achieved with a minimal photolithographic structure width of 0.4 μm.

In such a fixed value memory cell arrangement, DE 195 14 834 C1 proposes to provide memory cells which have a vertical MOS transistor which runs between a trench crown and a trench bottom via an intervening trench wall. The source area lies on the trench crown, the channel area on the trench wall and the drain area on the trench floor. Between the vertical Trench walls and the polysilicon of the word lines there is a gate oxide over the channel region of the vertical MOS transistor, that is to say the trench wall.

To produce the vertical MOS transistors, the trenches are first filled with electrically insulating material. Then, in accordance with the desired information pattern of the fixed value memory cell arrangement, the insulating material in the trenches is removed in the form of vertical holes, so-called programming holes, along the trench edges. Finally, after gate oxidation, the holes are filled with the polysilicon of the word lines. The adjustment of the programming hole mask and the etching of the holes are extremely critical in this process.

DE 19 609 678 discloses the manufacture of the source and drain regions of the vertical MOS transistors by vertical implantation parallel to the trench walls.

It is possible to program the vertical MOS transistors by setting the threshold voltages by obliquely implanting suitable dopants in the channel area. Such an implantation can shift the threshold voltage of the vertical transistor in such a way that it does not open at the gate voltages used. The implantation can be carried out in two steps using a respective lacquer mask, one for the right and one for the left trench walls.

The problem underlying the present invention generally consists in that, on the one hand, the oblique implantation for doping the channel areas, the source and drain areas on the horizontal trench crowns and trench bottoms, and on the other hand, the vertical implantation for doping the source and drain areas, the channel areas on the vertical trench walls as little as possible should influence. moreover the process should be as inexpensive as possible, ie have few mask levels.

At the moment there is a basic approach to solving this problem in the prior art, namely the provision of a single lacquer mask for the implantation of both trench walls, as disclosed in DE 19 630 050.

6 shows a schematic illustration to illustrate the problems with the prior art of DE 19 630 050.

In FIG. 6, 1 denotes a semiconductor substrate with a plurality of trenches 2, 3, 4 with corresponding trench crowns 5a, 5b, 5c, 5d; Trench floors 2a, 3a, 4a and trench walls 2b, 2c; 3b, 3c; 4b, 4c. There is a resist mask 70 on the semiconductor substrate 1, which partially fills the holes 2, 3, 4 and protrudes beyond the trench crowns 5b, 5c. A denotes the main surface normal of the semiconductor substrate 1. As shown by the arrows in FIG. 6, an oblique

Implantation can be carried out at a maximum angle α to the main surface normal without there being shadowing of the trench walls 2b, 3b by the resist mask 70. The same applies to an oblique implantation of the trench wall 4c under an angle -oc.

The fact that the thickness of the lacquer into which the lacquer mask 70 is exposed is greater than the desired trench depth or trench width has proven to be disadvantageous in the above known approach.

Together with the cantanular errors of the ^• phototechnology to be taken into account, this means that when the trench walls are implanted obliquely, the angle at which the implantation takes place must be relatively steep, ie low to the main surface normal of the semiconductor substrate 1, in order to avoid the trench walls to be implanted To achieve shading through the paint mask. Due to the associated lower projection of the implanted area dose onto the vertical wall, the implantation time is extended. In addition, due to the high implantation dose, too much dopant gets into the unprotected horizontal trench crown and trench bottom areas.

In order to achieve shallower angles, the lacquer plugs, which are intended to protect the channels that are not to be implanted, must have the minimum width that can be achieved by phototechnology in the direction perpendicular to the trenches. This makes photo technology critical. In addition, the individual paint plugs are mechanically unstable.

It is therefore an object of the present invention to provide an improved method for producing the semiconductor structure mentioned at the outset, which ensures reliable coverage of areas not to be implanted, is less critical photolithographically and can be carried out economically.

According to the invention, this object is achieved by the method specified in claim 1, that is to say by a method for producing a semiconductor structure on a main surface of a substrate having a plurality of trenches with corresponding trench crowns, trench bottoms and trench walls, which comprises the steps: forming spacers on the trench walls ; optionally removing predetermined spacers to expose corresponding trench walls; Performing at least one implantation at a predetermined angle to the main surface normal to form corresponding line areas.

The method according to the invention has the advantage over the known approaches that it can be implanted in different line areas using one and the same hard mask, ie the spacers, ie the number of photo steps is reduced. The general idea on which the present invention is based is that, instead of the customary phototechnically critical lacquer mask, an appropriately structured hard mask is used which does not protrude beyond the main surface.

Advantageous further developments and improvements of the method specified in claim 1 are found in the subclaims.

According to a preferred development, the spacers are left. An implantation is then carried out at a first angle to form corresponding first conduction areas in the trench crowns and / or trench bottoms.

According to a further preferred development, the first angle is chosen as essentially 0 ° to the main surface normal.

According to a further preferred development, predetermined spacers for exposing corresponding trench walls are removed after the implantation has been carried out at the first angle. A further implantation is then carried out at a second angle to the main surface normal to form corresponding second conduction areas in corresponding exposed trench walls. In this case, all spacers for the implantation at the first angle serve as a mask and then part of the, i.e. the not removed, spacers for implantation at the second angle as

Mask.

According to a further preferred development, predetermined spacers for exposing corresponding trench walls are removed before any implantation. Then an implantation is carried out at a second angle to the main surface normal to form corresponding second conduction areas in corresponding the exposed trench walls. The first line areas can also be produced by other common semiconductor processes.

According to a further preferred development, the second angle is selected in relation to the main surface normal in such a way that the exposed trench walls are not yet shaded. This shows a further advantage of the method according to the invention, namely that the permissible implantation angle for the implantation at the second angle is only determined by the aspect ratio of the trench, i.e. by the depth / width ratio. This makes programming much flatter and therefore more efficient.

According to a further preferred development, the semiconductor structure has vertical MOS transistors, the source region of which lies on a respective trench crown or a respective trench bottom, whose channel region lies on a respective trench wall and whose drain region lies on a respective trench bottom or on a respective trench crown.

According to a further preferred development, the first line areas are the source and / or drain areas.

According to a further preferred development, the second line areas are the channel areas.

According to a further preferred development, the predetermined spacers are in each case removed from both trench walls of the relevant trenches.

According to a further preferred development, the step of removing predetermined spacers has the following steps: coating the substrate with the trenches; Exposure of the lacquer at the appropriate places using a mask; Develop and removing the developed paint; Etch out the exposed spacers and remove the remaining paint.

According to a further preferred development, a mask is used which has holes with a diameter in the direction perpendicular to the trenches which is approximately 2B, where B is the trench width, and the holes are centered over the center of the trench.

According to a further preferred development, the trench width B is the minimal structural width F that can be generated by phototechnology.

According to a further preferred development, the implantation is carried out at the second angle only for one of the trench walls of the exposed trenches.

According to a further preferred development, for the implantation of the other of the trench walls, the remaining spacers are removed after the implantation or implantations, and this becomes

Formation and removal of the corresponding spacers are carried out again and an implantation is carried out at a third angle. The third angle is then expediently the negative angle of the second angle.

According to a further preferred development, the formation of the spacers on the trench walls has the following steps: depositing a silicon dioxide layer of a predetermined thickness; and anisotropic dry etching of the silicon dioxide layer.

According to a further preferred development, the silicon dioxide layer is a TEOS layer, preferably of a thickness of approximately 30 to 100 nm.

According to a further preferred development, the formation of the spacers on the trench walls has the following steps on: depositing a silicon nitride layer of a predetermined thickness; and anisotropic dry etching of the silicon nitride layer.

According to a further preferred embodiment, the anisotropic dry etching with CHF is _3/0 ₂ - performed plasma.

Exemplary embodiments of the invention are shown in the drawings and are explained in more detail in the following description.

Show it:

1 to 4 is a schematic representation of various

Steps in the implementation of a first embodiment of the method according to the invention;

5 shows a schematic illustration of a second embodiment of the method according to the invention; and

Fig. 6 is a schematic representation to illustrate the problems in the prior art.

In the figures, identical reference symbols designate identical or functionally identical elements.

1 to 4 show a schematic representation of various steps in the implementation of a first embodiment of the method according to the invention.

1 shows a substrate 1 with a plurality of trenches 2, 3, 4 with corresponding trench crowns 5a, 5b, 5c, 5d; Trench floors 2a, 3a, 4a and trench walls 2b, 2c; 3b, 3c; 4b, 4c, the trenches having a width B and a depth T. The trenches 2, 3, 4 have a strip-shaped cross section parallel to the main surface of the substrate 1. Their width B is usually 0.2-0.6 μm, their length 100-150 μm and their depth T 0.4-0.8 μm. The distance from trench to trench is also typically 0.2-0.6 μ.

A semiconductor structure with vertical MOS transistors is now to be formed in the substrate 1 designed in this way, the source region of which is on a respective trench crown or a respective trench floor, the channel region of which is on a respective trench wall and the drain region on a respective trench floor or on a respective one Trench crown lies.

As shown in Fig. 2, on the vertical trench walls 2b, 2c; 3b, 3c, ^• 4b, 4c spacer produced from Si0 ₂ . This is done conveniently by conformal deposition of a Si0 ₂ layer in a TEOS process in a layer thickness of for example 30 to 100 nm and subsequent anisotropic dry etching with CHF _3/0 - plasma.

The next step is the removal of predetermined spacers 6c, 6d in preparation for an oblique implantation. For this purpose, the substrate 1 is coated with photoresist 7. The mask 7 then exposes the lacquer 7 through holes 9 in the mask 8 at the corresponding points.

In the exemplary embodiment shown in FIG. 3, a mask 8 is used which has such holes 9 with a diameter in the direction perpendicular to the trenches which is approximately 2B, B being the trench width and the holes 9 being centered over the center of the trench. The trench width B is the minimum structure width F that can be generated by phototechnology.

This is followed by developing and removing the lacquer using conventional semiconductor process techniques, according to which lacquer plugs in the trenches 2, 4 with the spacers 6a, 6b; 6e, 6f remain. Finally, the exposed spacers 6c, 6d are etched out, for example by an HF dip, and then the remaining lacquer is removed. A hard mask suitable for the oblique implantation is now completed.

Next, as shown in FIG. 3, there is an implantation at an angle α ″ to the main surface normal for each of the trench walls, that is to say here the trench wall 3b. The angle CC 'is chosen such that it is normal to the main surface normal such that the exposed trench wall 3b is not yet shaded. It can be clearly seen that the angle α ″ in the method according to the invention can be selected to be substantially larger than the corresponding angle α ″ in the previously customary method with the lacquer mask according to FIG. 6.

The remaining spacers 6a, 6b; 6c, 6d removed after implantation. The corresponding spacers are then formed and removed again, in order to produce a hard mask for the right trench walls to be implanted.

Finally, implantation takes place in an analogous manner at an angle -CC '.

The trench walls as channel regions of the vertical MOS transistors are thus completed. In the first embodiment, the formation of the source and drain regions on the trench crowns or trench bottoms is carried out either by a customary method, e.g. by a diffusion method, or by a second embodiment of the method according to the invention, which is explained below with reference to FIG. 5.

5 illustrates a schematic representation of a second embodiment of the method according to the invention, wherein the spacers 6a, 6b; 6c; 6d; 6e, 6f are all left after their formation.

Then, using the spacers as a hard mask, an implantation is carried out at an angle .alpha. 'To form the source and drain areas of corresponding first conduction areas in the trench crowns and trench bottoms. The angle α 'is chosen as essentially 0 ° to the main surface normal. The trench walls are all covered by the spacers 6a, 6b; 6c; 6d; 6e, 6f protected.

It should be noted that with this procedure it is expedient to implant the channel regions after the source and drain regions, since in this case the spacers 6a, 6b; 6e, 6f can be left.

Although the present invention has been described above on the basis of preferred exemplary embodiments, it is not limited to these but can be modified in a variety of ways.

Instead of the vertical MOS transistors, the method according to the invention can also be used to form other semiconductor components which extend along the trench walls.

The spacers do not have to be formed from silicon dioxide, but can also be made from silicon nitride or polysilicon or the like. be formed.

Claims

claims

1. A method for producing a semiconductor structure on a main surface of a substrate (1) with a plurality of trenches (2, 3, 4) with corresponding trench crowns (5a, 5b, 5c, 5d), trench bottoms (2a, 3a, 4a) and trench walls (2b, 2c; 3b, 3c; 4b, 4c), which has the steps:

- Forming spacers (6a, 6b; 6c; 6d; 6e, 6f) on the trench walls (2b, 2c; 3b, 3c; 4b, 4c); - Optional removal of predetermined spacers (6c; 6d) to expose corresponding trench walls (3b, 3c);

- Performing at least one implantation at a predetermined angle (α ', α' ') to the main surface normal to form corresponding conduction areas.

2. The method according to claim 1, g e k e n n z e i c h n e t by the steps:

- leaving the spacers (6a, 6b; 6c; 6d; 6e, 6f);

Performing an implantation at a first angle (OC) to form corresponding first conduction areas in the trench crowns and / or trench bottoms.

3. The method of claim 2, d a d u r c h g e k e n n z e i c h n e t that the first angle is chosen as substantially 0 ° to the main surface normal.

4. The method of claim 2 or 3, g e k e n e z e i c h n e t by the steps: - Removing predetermined spacers (6c; 6d) to expose corresponding trench walls (3b, 3c) after performing the implantation at the first angle (α '); and

- Carrying out a further implantation at a second angle (α ″) to the main surface normal to form corresponding second conduction areas in corresponding exposed trench walls (3b).

5. The method of claim 1, g e k e n e z e i c h n e t by the steps: - Removing predetermined spacers (6c; 6d) to expose corresponding trench walls (3b, 3c); and - performing an implantation at a second angle

(α '') to the main surface normal to form corresponding second conduction areas in corresponding exposed trench walls (3b).

6. The method according to claim 4 or 5, d a d u r c h g e k e n n z e i c h n e t that the second angle (α '') is selected to the main surface normal that just no shadowing of the exposed trench walls (3b) occurs.

7. The method according to any one of the preceding claims, characterized in that the semiconductor structure has vertical MOS transistors, the source region on a respective trench crown or a respective trench bottom, the channel region on a respective trench wall and the drain region on a respective trench bottom or on a respective Trench crown lies.

8. The method according to claim 7, so that the first conduction regions are the source and / or drain regions.

9. The method according to claim 7 or 8, d a d u r c h g e k e n n z e i c h n e t that the second line areas are the channel areas.

10. The method according to any one of the preceding claims, that the predetermined spacers (6c, 6d) are respectively removed from both trench walls (3b, 3c) of the relevant trenches (3).

11. The method according to any one of the preceding claims, characterized in that the step of removing predetermined spacers (6c, 6d) comprises the following steps:

- coating the substrate (1) with the trenches (2, 3, 4);

- Exposing the lacquer (7) at corresponding points via a mask (8);

- Developing and removing the developed paint (7);

- Etching out the exposed spacers (6c, 6d); and

- Remove the remaining paint (7).

12. The method according to claim 11, characterized in that a mask (8) is used which has holes (9) with a diameter in the direction perpendicular to the trenches which is approximately 2B, where B is the trench width, and the holes (9 ) are centered over the middle of the trench.

13. The method according to claim 12, so that the trench width B is the structure width F that can be generated with minimum phototechnology.

14. The method according to any one of claims 4 to 13, that the implantation is carried out at the second angle (OT ') only for one of the trench walls (3b) of the exposed trenches (3).

15. The method according to claim 14, characterized in that for the implantation of the other of the trench walls, the remaining spacers (6a, 6b; 6c, 6d) are removed after or the implantations and the formation and removal of the corresponding spacers is carried out again and an implantation is carried out at a third angle (-0T ').

16. The method according to any one of the preceding claims, characterized in that the formation of the spacers (6a, 6b; 6c; 6d; 6e, 6f) on the trench walls (2b, 2c; 3b, 3c; 4b, 4c) comprises the following steps:

- depositing a silicon dioxide layer of a predetermined thickness; and

- Anisotropic dry etching of the silicon dioxide layer.

17. The method according to claim 16, and the fact that the silicon dioxide layer is a TEOS layer, preferably of a thickness of approximately 30 to 100 nm.

18. The method according to any one of claims 1 to 15, characterized in that the formation of the spacers (6a, 6b; 6c; 6d; 6e, 6f) on the trench walls (2b, 2c; 3b, 3c; 4b, 4c) following steps having:

- depositing a silicon nitride layer of a predetermined thickness; and

- Anisotropic dry etching of the silicon nitride layer.

19. The method according to claim 16, 17 or 18, characterized in that the anisotropic dry etching with CHF _3/0 ₂ - plasma is performed.