WO1999023705A1

WO1999023705A1 - Passive hf element and method for operating, producing and determining characteristic properties of the same

Info

Publication number: WO1999023705A1
Application number: PCT/EP1997/006012
Authority: WO
Inventors: Dietmar Eggert; Peter Hübler; Arnd HÜRRICH; Ulrich Todt; Matthias Vorwerk
Original assignee: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
Priority date: 1997-10-30
Filing date: 1997-10-30
Publication date: 1999-05-14

Abstract

The invention relates to a passive high frequency element, comprising a semiconductor substrate (14), an insulator (12) which is arranged on said semiconductor substrate (14) and through which interlayer charges are produced in an interface area between the semiconductor substrate (14) and the insulator (12), and a conductor (10) which is located on the isolator (12). According to the invention, the interlayer charges are depleted through the application of a direct voltage (U) between the conductor (10) and the semiconductor substrate (14) and/or through a weakly doped area under the insulator (12). This results in a considerably lower density of mobile charge carriers in the transitional area between the insulator (12) and the semiconductor (14). A window of low attenuation is provided for the inventive high-frequency elements, said window being delimited in the interface area by a slight depletion of interlayer charges and by a slight enhancement of charges with opposite polarity to the interlayer charges.

Description

Passive RF element and method for operating, producing and determining characteristic properties of the same

description

The present invention relates to MOS structures, and in particular to passive radio frequency (RF) elements that have MOS structures.

In the monolithic integration, electrical connections between individual components are generally designed as aluminum conductor tracks, which are separated from the semiconductor starting material by an oxide. The band bending resulting from the combination of metal, oxide and semiconductor determines the propagation properties of high-frequency electromagnetic fields on the connections, in particular in the case of high-resistance semiconductor starting materials. The band bending results from the properties of the materials involved, i. H. the difference of the work functions or the density of the interlayer charges, and are expressed in freely movable charge carriers, d. H. Holes or electrons that lead to a thin semiconductor layer with a comparatively low specific resistance below the oxide layer. In the usual metal-oxide semiconductor used in connection systems. Polysilicon oxide semiconductor layers determine the nature of the oxide, the electrical properties of these structures due to the high number of interlayer charges present in the border area between oxide and semiconductor. The influence of the differences in the work functions of the materials involved, on the other hand, decreases in its influence. In the case of high-resistance substrates in particular, space charge zones with an extension of a few μm result.

Simulations show that with the same potential at the bounding edges in a p-type semiconductor substrate material with a specific resistance of 10 kΩcm and a density of the interlayer charges of, for example, 2 ^• 10- ^ cm ^-2 below the oxide layer, an accumulation of electrons occurs, as a result of which the semiconductor substrate (e.g. Silicon) is already in inversion. The inverted area at the interface between the semiconductor substrate and the insulator leads to a sharp increase in the conductivity in the substrate, which for a substrate material with a resistivity of 10 kΩcm is up to five orders of magnitude greater than that of the starting material. This inversion layer thus decisively determines the conditions for the damping and, more generally, for the spread of high-frequency electromagnetic fields on a conductor-insulator-semiconductor layer structure.

In particular, this inversion layer leads to a high damping of an electromagnetic wave which propagates, for example, on a coplanar line in which the metallizations are separated from the semiconductor substrate material by an oxide. The inversion layer, which is present in the oxide solely due to solid, mostly positive charges, therefore also leads to a reduction in the quality of integrated coils or interdigital capacitors, which are designed as a conductor-insulator-semiconductor structure.

In order to prevent the formation of an inversion layer within the semiconductor material, so-called field threshold implantation is carried out in standard CMOS technologies. This avoids current flow between the source and drain regions of different transistors. Although ion implantation through the buried oxide is technically possible, the following problems limit the feasibility of this step:

1. When using high-resistance silicon substrates, the corresponding MOS structure reacts very sensitively to the smallest implantation doses. It must be ensured here that the implantation does not result in an enrichment of holes at the interface. These increase the damping in a similar way as the electrons present during inversion increase the substrate-related losses.

2. A technological implementation of this process step leads to an unacceptably high dopant diffusion in the subsequent high-temperature steps.

3. The buried oxide isolates the active transistor regions from one another in terms of DC voltage; this step is therefore not necessary to ensure the functionality of the transistors.

4. The use of this effect places high demands on the reproducibility of the technology, since the passive structures are realized in the implementation of the wiring levels, and thus an adjustment of this threshold voltage must take place over almost the entire process.

The object of the present invention is to provide a passive high-frequency element and a method for operating for producing and determining characteristic properties of the same which, in a simple yet effective manner, improve high-frequency properties of passive RF components in comparison to conventional passive components Reach RF components that are designed as a conductor-insulator-semiconductor structure.

This object is achieved by a passive RF element according to claim 1, by a method for operating a passive RF element according to claim 9, by a method for determining characteristic properties of a passive RF element according to claim 11 and by a method for producing one passive RF element according to claim 14 solved. - 4th -

The present invention is based on the knowledge that targeted depletion of the inversion layer according to a first aspect of the present invention by applying a DC voltage between the conductor and the semiconductor substrate leads to a significant improvement in the high-frequency properties of the passive RF element. According to a second aspect, instead of applying the DC voltage or together with a DC voltage, a weakly doped region is formed under the insulator, the doping of which is selected such that depletion of interlayer charges occurs in the boundary region.

The passive RF element according to the present invention in particular comprises a semiconductor substrate, an insulator arranged on the semiconductor substrate, by means of which interlayer charges are generated at the interface between the semiconductor substrate and the insulator, a conductor arranged on the insulator and a device for applying a DC voltage between the conductor and the semiconductor substrate in such a way that depletion of the interlayer charges is achieved. As discussed in more detail below, depending on the substrate conductivity, the insulator or oxide thickness and the interlayer charge density, a "window" of low attenuation results, which can be achieved by applying a DC voltage between the conductor and the semiconductor.

Preferred exemplary embodiments are explained in more detail below with reference to the accompanying drawings. Show it:

FIG. 1 is a schematic diagram showing the layer structure of a conductor-insulator-semiconductor structure for a passive RF element according to the first aspect;

FIG. 2 shows the potential curve at the in FIG. 1 shown structure with an applied voltage of OV for - 5 - -

different substrate resistances and an interface charge density of N ₀ = 2 ^• 10 ^ cm ^-2 ;

FIG. 3 shows the course of the concentrations of the freely movable charge carriers in the depletion region for different applied voltages;

FIG. 4 the local distribution of the specific resistance in the semiconductor;

FIG. 5 the voltage dependence of the damping using the example of a coplanar line;

FIG. 6 shows the voltage dependence of the elements of the line equivalent circuit diagram of a coplanar line;

FIG. 7 is an illustration of sequential method steps for producing a passive high-frequency component in accordance with the second aspect of the present invention;

FIG. 8 shows a measuring arrangement for characterizing coplanar waveguide structures; and

FIG. 9 shows a signal flow graph for the extraction of line parameters.

FIG. 1 schematically shows a high-frequency (RF) element according to the first aspect, which consists of a conductor 10, an insulator 12 and a semiconductor 14. The conductor 10 can either be made of metal, e.g. As aluminum, or be formed from polysilicon. The semiconductor 14 can be a silicon semiconductor, which is why the insulator 12 is preferably designed as silicon oxide (Si0 ₂ ). However, it will be apparent to those skilled in the art that other conductor-insulator-semiconductor configurations can be used in connection with the present invention. A passive radio frequency element that the the in FIG. 1 shows MOS structure (MOS = metal-oxide-semiconductor), of course, requires a ground plane, which can be embodied, for example, as rear-side metallization of semiconductor 14 in the case of a microstrip line or as a ground plane on oxide 12 in the case of a coplanar line or as another reference plane can. This fact is self-evident and therefore in FIG. 1 not drawn. The passive RF element according to the present invention further comprises connections 16a and 16b, which are arranged on the metal 10 or on the semiconductor 14 and can serve as a device for applying a direct voltage U. Left in FIG. 1 also shows the reference coordinate x for the following figures, it being pointed out that the value x = 0 is located at the interface between the oxide 12 and the semiconductor 14. For the calculation and description set out below by way of example, a semiconductor substrate is assumed which has a thickness in the x-direction of 100 μm, while the silicon oxide 12 has a thickness of 2.5 μm and the metallization 10 is 0.5 μm thick.

If the in FIG. 1 structure shown, metal, oxide and semiconductor are brought together. Since the Fermi potential in the thermodynamic equilibrium must have the same level in the entire structure, a band edge bending occurs. In the area of the boundary layer, which is also referred to as the "interface", between the oxide and the semiconductor, the disruption of the crystal structure creates a number of illegal energy levels or a number of intermediate layer states. They are caused by so-called trap centers, which act as acceptors or donors and are therefore able to bind freely moving electrons.

FIG. 2 shows the potential curve of the in FIG. 1 shown MIS transition with an applied voltage U of OV for different substrate resistances and an interfacial density of 2-10 ¹¹ cm ^{~ 2} . The in FIG. 2 shows the potential profile for the semiconductor materials with the individual specific resistances corresponds to the profile of the voltage difference between the intrinsic conduction level and the quasi-Fermi level of the semiconductor. The 0 potential corresponds to the position of the Fermi level of intrinsic (intrinsically conductive) silicon. In the interior of the semiconductor (x> 0) at the point where there is a parallel potential profile, negative values result from the p-doping of the silicon used. Different specific substrate resistances cause a difference in the position of the respective quasi-Fermi levels due to the different basic doping. An increase in the specific resistance (reduction in the p-type basic doping) consequently leads to an approximation to the O potential.

For the in FIG. The two results presented were based on a difference in contact potential between aluminum and doped silicon of 0.3 V. The potential runs parallel to the coordinate axis within the metal. The actual contact voltage results from the potential difference between the metallization and the interior of the semiconductor. It is 0.6 V for the material with the lowest specific resistance (10 Ωcm) and decreases when using high-resistance (10 kΩcm) output substrates to a value of around 0.42 V. Because all oxide charges and interlayer states act as interface charges The actual oxide area is considered to be charge-free in the simulation presented here, which is why there is a linear increase in the potential here. In the silicon area in the vicinity of the oxide, however, there is a strong curvature in the potential profile. This indicates the dominance of negative charges.

In the semiconductor interior, the specific resistance has the value of the starting material. As the space charge zone begins near the oxide, the resistivity increases up to a maximum value jp _Itιaχ = l / σ _m i _n - This value is approx. 400 kΩcm. The semiconductor is depleted in this area by freely movable charge carriers, while the acceptor ions firmly anchored in the crystal lattice determine the charge of the semiconductor. If the interface between the oxide and the semiconductor is approached further, the specific resistance drops again as a result of the increasing proportion of freely mobile electrons due to the positive charges present in the oxide. In the area of the semiconductor interface, there is a sharp increase in conductivity in the inverted area, which can be up to five orders of magnitude higher than the conductivity of the starting material. This inversion layer largely determines the propagation conditions for high-frequency electromagnetic fields on the MOS structure of FIG. 1.

As has already been mentioned, in order to prevent the formation of this inversion layer within the semiconductor material in standard CMOS technologies, a field threshold implantation is carried out, which deliberately depletes the parasitic MOS structure occurring in the connection system. For the reasons mentioned at the outset, this measure is unfavorable or not possible with the high-resistance substrates used here.

According to the present invention, however, by deliberately depleting the interface area between the oxide 12 and the semiconductor 14, a significant reduction in the conductivity and thus an improvement in the high-frequency-relevant properties of the MOS structure is possible. This depletion region, which is limited on the one hand by the beginning accumulation and on the other hand by the onset of inversion, is therefore used according to the invention for the operation of passive HF elements, preferably using silicon technology.

FIG. 3 shows the location-dependent distributions of the freely movable charge carriers for different ones between the conductor - 9 - ~

10 and the semiconductor 14 applied DC voltages.

At this point it should be noted that in the sense of this application the term "DC voltage" does not mean strictly a DC voltage. The "DC voltage" can also be a low-frequency voltage, the frequency of which is significantly lower than the frequency of the electromagnetic waves that can propagate on the passive high-frequency components according to the invention. As is customary in practice, the "DC voltage" according to this invention can also contain high-frequency noise components, the alternating amplitude of which, however, is significantly less than the DC amplitude of the voltage.

The voltage values shown in FIG. 3 have been selected to estimate the depletion region and, according to the invention, lead to a significant increase in the specific resistance in the semiconductor compared to the case in which no voltage is applied. However, it should be noted that even with smaller or larger voltages than that shown in FIG. 3, an increase in the resistivity of the MOS structure occurs, which is why they are also within the scope of this invention. Based on the derivations of the behavior of an MIS structure that are widespread in the literature, the tensions are related to the backside potential of the structure. According to the directional convention of FIG. 1 thus a negative voltage U leads to depletion of an inversion layer between the oxide 12 and the semiconductor 14, since the inversion layer essentially consists of electrons, the semiconductor 14 being slightly p-doped. In a case where the oxide has essentially only negative fixed charges, the inversion between the oxide 12 and the semiconductor 14 will result in a hole accumulation, especially if the semiconductor 14 is n-doped. In this case, positive voltages U are of course necessary in order to deplete this inversion layer according to the invention in order to achieve a higher specific resistance of the semiconductor 14. From FIG. 3 it can be seen that in the example of the present invention described in this application, a very high electron density is present between the oxide 12 and the semiconductor 14 at a voltage of -23 V. Similarly, the hole density at this voltage is very small, as can be seen from the right drawing of FIG. 3 can be seen. If the applied voltage U is made more negative, the electron density decreases, while the hole density increases. At a voltage of approximately -24.25 V there is the so-called flat band case. The electron and hole densities are unchanged from their initial value, with FIG. 3 is seen that the output value of the electron density is 10 ⁸ cm ^-3, while the output value of the hole density is ¹² cm ^-3 I0, since, as has already been mentioned, the semiconductor 14 slightly p-doped. A further reduction in the applied voltage U now leads to an increase in the hole concentration at the interface between the oxide 12 and the semiconductor 14, this increase also being referred to as accumulation or enrichment.

FIG. 4 shows the simulated local course of the specific sheet resistance. With an external voltage of -23 V (the semiconductor is biased positively in relation to the metallization 10), the specific resistance is greatly reduced as a result of the inversion layer in the interface area (in this case about 90 Ωcm). In the adjoining space charge zone, the specific resistance rises to the highest possible value P _max = 400 kΩcm, in order to finally decrease in the undisturbed semiconductor to the value of © = 10 kΩcm, which is typical for the starting material.

With an external voltage of -24 V, on the other hand, optimal conditions are achieved with regard to the resistance in the silicon for the propagation of high-frequency electromagnetic fields. Here, the specific resistance already has a theoretical maximum value J » _max = 400 kΩcm at the interface, _ _{l χ} _

to then drop to the initial value of β = 10 kΩcm inside the semiconductor. The interface area is optimally impoverished in this state. From FIG. 4 it can be seen that within a range of approximately 15 μm, applying a corresponding direct voltage achieves a substantial improvement over the already high-resistance semiconductor material 14. A further increase in the applied voltage leads to an increase in the hole density, while the number of freely moving electrons decreases.

Passive radio frequency elements according to the present invention are in the area of high resistance, i. H. low attenuation, use according to the invention, in particular coplanar lines, integrated coils and interdigital capacitors.

FIG. 5 shows the damping behavior of a preferred exemplary embodiment of the present invention, namely the damping behavior of a coplanar line. For the in FIG. 5 measurement, all metal components of the coplanar line, ie the inner strip and the outer ground planes, were placed at the same potential in order to achieve the most uniform possible distribution of the static electric field which is generated by applying the DC voltage between the metal and the semiconductor . FIG. 5 underlines that a substantial reduction in damping, e.g. B. at a frequency of 5 GHz of 0.27 dB / mm at 0 V applied voltage to 0.1 dB / mm at an externally applied voltage of about -30 V is achieved. FIG. 5 further illustrates that a reduction in the attenuation of the coplanar line occurs even when the voltage is low. Voltages between -10 V and -40 V are preferably applied, although it should be noted that smaller direct voltages up to 0 V and much larger direct voltages up to -120 V can be applied, but care must be taken that the dielectric strength of the oxide and the semiconductor is taken into account, on the one hand, to avoid avalanche effects, and - 12 - -

on the other hand, in particular to rule out irreversible destruction of the MOS structure according to the invention.

From FIG. 5 further shows that at a voltage of approximately -30 V the inversion in the semiconductor is reduced, after which the attenuation of the coplanar line increases again, since such high negative voltages will lead to hole accumulation in the boundary layer region. As previously mentioned, the negative voltage between the back of the wafer, i. H. on the semiconductor 14, and all metallizations on the oxide 12 are applied. However, a reduction in damping can also be achieved if the voltage between the back of the wafer, i. H. the semiconductor 14, and for example only the inner conductor of a coplanar line or only the ground surfaces of the coplanar line. The same applies to integrated coils in which the integrated coil structure and the surrounding ground plane can be kept at the same potential or at different potential. With interdigital capacitors it is also possible to keep both electrode finger structures at the same potential. A reduction in the damping for electromagnetic waves is also achieved, however, if only one finger electrode is negatively biased towards the back of the wafer.

FIG. 6 finally shows the four frequency-dependent line equivalent circuit parameters, starting from a simple line equivalent circuit diagram consisting of a series connection of a resistor and an inductor and a parallel connection of a capacitor and a conductance, as is generally known. FIG. 6 shows the individual equivalent circuit parameters for different applied voltages between 0 V and 28 V. It can clearly be seen that the serial elements, ie the inductance coating and the resistance coating, are essentially not affected by the applied voltage. In contrast, the courses of the capacitance and the conductance covering show a significant voltage dependency. By applying A DC voltage between the metal 10 and the semiconductor 14 of a conductor-insulator-semiconductor structure can therefore not only reduce the attenuation of passive high-frequency components, but also increase resonance frequencies that may occur in order to increase the range of use of integrated passive high-frequency components at higher operating frequencies to enlarge.

Passive RF elements according to the present invention and methods for operating passive RF elements according to the present invention thus enable a substantial reduction in the attenuation for electromagnetic waves. Particularly in the case of SOO processes based on SIMOX, the depletion of the inversion layer between the semiconductor and the oxide is extremely important, since a commonly used field threshold implantation is not possible. Although the semiconductor substrates used for the passive RF elements according to the present invention can also be low-resistance, the advantageous use of the present invention is particularly evident in the case of high-resistance substrates (resistivity greater than 100 Ωcm).

FIG. 7 shows a diagram of sequential method steps for producing a passive high-frequency element according to the second aspect of the present invention. SIMOX technology is preferably used for the passive high-frequency element according to the second aspect of the present invention. SIMOX means Separation by Implantation of Oxygen. This means that highly accelerated oxygen atoms are shot into a silicon wafer, which reach a certain depth of penetration into the silicon in accordance with the selected energy. The crystal structure in the Si surface is largely destroyed. The crystal structure is restored by a healing step at a very high temperature, which is, for example, between 1000 ° C. and 1375 ° C. and preferably in a range between 1250 ° C. to 1350 ° C. At the same time, the effect occurs that the oxygen with Si reacts and forms an Si0 ₂ layer under the Si surface. The special thing here is that the interface between the silicon and the silicon dioxide is very clearly formed, and is comparable to the interface of Si with an SiO ₂ layer produced by oxidation. As will become clearer below, because of this comparability, the interface between the buried silicon dioxide layer and the silicon substrate can be regarded as an insulator-semiconductor junction, as was also explained and carried out in connection with the first aspect of the present invention. The considerations can therefore also be used in the case of a buried silicon oxide layer.

For high-frequency circuits, this buried oxide layer is very advantageous because it causes parasitic capacitances, for. B. the source and drain regions to the semiconductor substrate (or Si bulk) can be significantly reduced. For this reason, high-resistance wafers are used, which can have resistivities of up to 10 kΩcm, as already mentioned at the beginning.

According to the first aspect of the present invention, a wide depletion region was created under the Si surface by applying a suitable DC voltage in order to reduce the undesired charge accumulations which could lead to inversion, in order to reduce the specific resistance or the damping due to the eliminate higher conductivity in these areas. With higher substrate doping, this expansion of the space charge zone is significantly smaller, which is why the technically exploitable effect compared to the use of very high-resistance substrates is significantly less. According to the second aspect, a weakly doped semiconductor region is now generated under the insulator in order to build the effect of the application of the DC voltage, as it were, firmly into the passive element. Therefore, all previously made considerations regarding the effect of the direct voltage on the interlayer charges also apply to the second aspect. Generally speaking, can thus essentially any special voltage value can be imitated by a suitable choice of the doping parameters for the doped region under the insulator.

The first step of FIG. 7 shows a raw semiconductor substrate 14, which is preferably made of silicon. This is treated by means of oxygen implantation 20 in order to produce the buried oxide layer mentioned. This oxide layer is shown at 22 in the second field of FIG. 7 designated. In the SIMOX process described, a thin silicon film 24 has formed over the oxide layer by annealing the Si crystal. The buried Si0 ₂ layer is, for example, 400 nm thick, while the silicon film 24 will only have a thickness of 100 nm. In the areas of the semiconductor wafer or the semiconductor substrate 14, where later waveguides, coils or capacitors are to be produced as passive high-frequency components, a selective oxidation of the silicon film is now carried out, with which the latter now forms a thicker silicon oxide layer together with the buried silicon oxide layer, which forms the insulator 12 of FIG. 1 corresponds. According to the second aspect of the present invention, a weakly doped semiconductor layer is now formed under the insulator 12 in order to achieve depletion of the interlayer charges between the insulator 12 and the semiconductor substrate 14 even without applying a DC voltage. In the process sequence described in SIMOX technology, the p-type is selected here as the doping type. In particular, the weakly doped p ^"silicon layer 24 is produced by means of a boron implantation, the doping concentration is preferably in the range of 10 ¹¹ -.. 10 ¹³ cm ^-2 The boron implantation is to take place with high energy, the energy in the range 200 ... 1000 keV must lie so that an implantation can take place through the insulator 12, in this case the silicon oxide, and the thickness of the weakly doped layer and especially the doping concentration can essentially achieve any charge state which can also be obtained by applying a voltage Advantageous in the passive high frequency element that with respect to sub-picture 4 of FIG. 7 only needs a metallization, is that no DC voltage has to be applied, but that the band bending in the Si at the SiO ₂ interface can be adjusted by doping the weakly p-doped region 24. At this point it should be noted that the representation of a SIMOX process is only an example, since the silicon technologies have reached a high degree of maturity. Those skilled in the art will recognize that the targeted depletion of interlayer charges in high-frequency elements can also be achieved with other semiconductor systems, in which case other parameters or materials must be used for implantation or for producing the insulator.

FIG. 8 shows a measuring arrangement for characterizing passive high-frequency elements, in this example of coplanar waveguide structures. The left half of FIG. 8 shows a known network analyzer with which the method according to the invention for determining characteristic properties of a passive high-frequency component can be carried out according to a further aspect of the present invention. The network analyzer additionally has a DC voltage source U in order to be able to apply different voltages to the coplanar waveguide structure in such a way that depletion of interlayer charges between the semiconductor substrate and the insulator formed thereon can be achieved.

The right half of FIG. 8 shows an enlarged schematic plan view of the measuring tip arrangement for transmission measurement. In the middle is the coplanar line as an example of a high-frequency element, which is contacted on the left and right by network analyzer measuring tips. The case shown here is a so-called ON wafer measurement. With such measurements, the choice of coplanar measuring heads assumes a very good adaptation of the field distributions. For the investigations of the character - -

terization of the line behavior is now shown in FIG. 8 shown measurement setup used. A DC voltage source is used during the measurements in order to determine the properties of the coplanar lines at the respective DC voltage values by determining their four-pole parameters and preferably their scattering parameters. The corresponding line parameters are then determined directly from the measured values.

FIG. 9 shows a signal flow graph for extracting the line parameters. When determining the line parameters, in the case of the coplanar line, a symmetrical reflection behavior of a waveguide is assumed. This means that the two scattering parameters S and S _{22 are the} same. This property can also be used to check the quality of adaptation when carrying out the measurements. Because of the reciprocal behavior S ₂₁ = S ₁₂ , two of the four scattering parameters determined are complex variables that are independent of one another and can be used to calculate the complex line parameters r and r. Knowing the cable length, the two parameters result as follows:

1 + s {. -. - O »t_-s? _- l) ^a - **? Ι

_.S ₂₁

The complex reflection factor r given here is directly related to the characteristic impedance Z _w which characterizes the adaptive behavior of the cable due to Z _w = 50 Ω (1 + r) / (l - r). As is known, the attenuation of a line results as a real part of the propagation constant r.

The measuring method according to the invention, which, like the method for operating the passive RF element and the passive RF element itself, is based on the knowledge that A targeted depletion of the interlayer loads in order to improve circuit-relevant properties can be applied to all known methods for determining material parameters via CV dependencies. While known CV measurements are associated with large measurement errors, particularly in the case of high-resistance substrates, CV measurements also give an integral picture of the transition. However, the measuring methods according to the invention are particularly sensitive to the nature of the material immediately below the oxide and thus allow a differential analysis of this area. Preferred characteristic properties which can be determined from the four-pole parameters are, in particular, the attenuation, the shortening factor and the characteristic impedance for lines and the quality for coils or capacitors.

Claims

claims

1. Passive high-frequency element with the following features:

a semiconductor substrate (14);

an insulator (12) arranged on the semiconductor substrate (14), by means of which interlayer charges are generated in a boundary layer region between the semiconductor substrate (14) and the insulator (12);

a conductor (10) arranged on the insulator (12); and

a device (16a, 16b; 24) with which depletion of the interlayer charges can be achieved.

2. Passive high-frequency element according to Claim 1, in which the device (16a, 16b) with which depletion of the interlayer charges can be achieved is a device for applying a DC voltage between the conductor (10) and the semiconductor substrate (14), which can be selected such that depletion of the interlayer charges can be achieved.

3. Passive high-frequency element according to claim 2, characterized in that a voltage can be applied by the means for applying a DC voltage, in which the depletion is substantially complete, while an enrichment of charges with opposite polarity to the interlayer charges essentially does not occur, as a result of which the passive high-frequency element has minimal attenuation for electromagnetic waves.

4. Passive high-frequency element according to claim 2 or 3,

in which the conductor (10) is made of metal or polysilicon stands while the semiconductor substrate is p-type silicon and the insulator (12) consists of silicon oxide; and

in which a negative voltage can be applied between the conductor (10) and the semiconductor substrate (14) by the device (16a, 16b) for applying a direct voltage (U).

The high-frequency passive element of claim 1, wherein the means (24) for depleting interlayer charges is a low doping region in the interface region between the semiconductor substrate (14) and the insulator (12), the Doping type is selected such that depletion of the interlayer charges occurs.

Passive high-frequency element according to Claim 5, in which the device (16a, 16b; 24) with which depletion of the interlayer charges can be achieved includes both the device (16a, 16b) for applying a DC voltage and the region (24) weak doping.

Passive high-frequency element according to one of the preceding claims, which is designed as a coplanar line, integrated coil or as an interdigital capacitor.

Passive high-frequency element according to one of the preceding claims, in which a high-resistance semiconductor substrate (14) is used.

Method for operating a passive high-frequency element with a semiconductor substrate (14), an insulator (12) arranged on the semiconductor substrate (14), by means of which interlayer charges are generated in the boundary layer region between the semiconductor substrate (14) and the insulator (12), and a conductor (10) arranged on the insulator (12), the method following step:

Applying a DC voltage (U) between the conductor (10) and the semiconductor substrate (14) in such a way that depletion of the interlayer charges is achieved.

10. The method according to claim 9, in which a DC voltage (U) between the conductor (10) and the semiconductor substrate (14) is applied, which causes that on the one hand the depletion is substantially complete, while on the other hand an enrichment of charges of opposite polarity to the interlayer charges does not occur, as a result of which the passive high-frequency element has minimal attenuation.

11. A method for determining characteristic properties of a passive high-frequency element with a semiconductor substrate (14), an insulator (12) arranged on the semiconductor substrate (14), by means of the interlayer charges in the boundary layer region between the semiconductor substrate (14) and the insulator (12 ) and a conductor (10) arranged on the insulator (12), with the following steps:

Measuring four-pole parameters of the passive high-frequency element for different direct voltages between the conductor (10) and the semiconductor substrate (14), the direct voltages (U) being selected such that depletion of the interlayer charges is achieved; and

Calculation of characteristic properties of the passive high-frequency element as a function of the applied DC voltage from the four-pole parameters determined.

12. The method of claim 11, wherein the characteristic properties of the passive high-frequency element include the complex reflection factor and the propagation parameter.

13. The method according to claim 11 or 12, wherein the characteristic properties include the attenuation, the shortening factor and the characteristic impedance of lines or the quality of coils and capacitors.

14. A method for producing a passive high-frequency element with the following steps:

Implanting a semiconductor substrate (14) with implantation atoms (20) in such a way that the implantation atoms (20) reach a desired depth of penetration in the semiconductor substrate (14);

Healing of the implanted substrate (14) in such a way that a buried insulator layer (22) forms in the semiconductor substrate (14) and, with respect to the direction of implantation, a new semiconductor layer (24) forms over the buried insulator layer (22);

Converting the new semiconductor layer (24) at the areas of the semiconductor substrate (14) on which the passive high-frequency element is to be produced into a new insulator layer, which together with the buried insulator layer (22) forms an insulator (12);

Implanting a layer (24) with weak doping through the insulator (12) into the semiconductor (14), the doping type being selected such that depletion of interlayer charges occurs under the insulator (12); and

selectively metallizing the isolator (12) to obtain the high frequency passive element.

15. The method according to claim 14, in which the semiconductor substrate (14) is a high-resistance silicon substrate;

in which the implantation atoms (20) are oxygen atoms in the first step;

wherein the buried insulator layer (22) comprises silicon oxide; and

in which the layer (24) with a weak doping is a p-type layer and is implanted by means of acceptor atoms and in particular boron atoms.

16. The method according to claim 15, in which the acceptor doping is carried out with energies between 100 and 2000 keV, and in which the acceptor density in a range from 10 ¹¹ to 10 ¹⁴ cm " ² and preferably in a range between 10 ¹² and 10 ¹³ cm ^"2 lies.