WO1999023705A1 - Element hf passif et procede permettant son fonctionnement, ainsi que son procede de fabrication et procede de determination de proprietes caracteristiques - Google Patents

Element hf passif et procede permettant son fonctionnement, ainsi que son procede de fabrication et procede de determination de proprietes caracteristiques Download PDF

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Publication number
WO1999023705A1
WO1999023705A1 PCT/EP1997/006012 EP9706012W WO9923705A1 WO 1999023705 A1 WO1999023705 A1 WO 1999023705A1 EP 9706012 W EP9706012 W EP 9706012W WO 9923705 A1 WO9923705 A1 WO 9923705A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor substrate
insulator
charges
voltage
passive
Prior art date
Application number
PCT/EP1997/006012
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German (de)
English (en)
Inventor
Dietmar Eggert
Peter Hübler
Arnd HÜRRICH
Ulrich Todt
Matthias Vorwerk
Original Assignee
Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
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Priority to PCT/EP1997/006012 priority Critical patent/WO1999023705A1/fr
Publication of WO1999023705A1 publication Critical patent/WO1999023705A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors with potential-jump barrier or surface barrier
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS

Definitions

  • the present invention relates to MOS structures, and in particular to passive radio frequency (RF) elements that have MOS structures.
  • RF radio frequency
  • electrical connections between individual components are generally designed as aluminum conductor tracks, which are separated from the semiconductor starting material by an oxide.
  • the band bending resulting from the combination of metal, oxide and semiconductor determines the propagation properties of high-frequency electromagnetic fields on the connections, in particular in the case of high-resistance semiconductor starting materials.
  • the band bending results from the properties of the materials involved, i. H. the difference of the work functions or the density of the interlayer charges, and are expressed in freely movable charge carriers, d. H. Holes or electrons that lead to a thin semiconductor layer with a comparatively low specific resistance below the oxide layer.
  • metal-oxide semiconductor used in connection systems.
  • Polysilicon oxide semiconductor layers determine the nature of the oxide, the electrical properties of these structures due to the high number of interlayer charges present in the border area between oxide and semiconductor.
  • space charge zones with an extension of a few ⁇ m result.
  • Simulations show that with the same potential at the bounding edges in a p-type semiconductor substrate material with a specific resistance of 10 k ⁇ cm and a density of the interlayer charges of, for example, 2 • 10- ⁇ cm -2 below the oxide layer, an accumulation of electrons occurs, as a result of which the semiconductor substrate (e.g. Silicon) is already in inversion.
  • the inverted area at the interface between the semiconductor substrate and the insulator leads to a sharp increase in the conductivity in the substrate, which for a substrate material with a resistivity of 10 k ⁇ cm is up to five orders of magnitude greater than that of the starting material.
  • This inversion layer thus decisively determines the conditions for the damping and, more generally, for the spread of high-frequency electromagnetic fields on a conductor-insulator-semiconductor layer structure.
  • this inversion layer leads to a high damping of an electromagnetic wave which propagates, for example, on a coplanar line in which the metallizations are separated from the semiconductor substrate material by an oxide.
  • the inversion layer which is present in the oxide solely due to solid, mostly positive charges, therefore also leads to a reduction in the quality of integrated coils or interdigital capacitors, which are designed as a conductor-insulator-semiconductor structure.
  • the corresponding MOS structure reacts very sensitively to the smallest implantation doses. It must be ensured here that the implantation does not result in an enrichment of holes at the interface. These increase the damping in a similar way as the electrons present during inversion increase the substrate-related losses.
  • the buried oxide isolates the active transistor regions from one another in terms of DC voltage; this step is therefore not necessary to ensure the functionality of the transistors.
  • the object of the present invention is to provide a passive high-frequency element and a method for operating for producing and determining characteristic properties of the same which, in a simple yet effective manner, improve high-frequency properties of passive RF components in comparison to conventional passive components Reach RF components that are designed as a conductor-insulator-semiconductor structure.
  • the present invention is based on the knowledge that targeted depletion of the inversion layer according to a first aspect of the present invention by applying a DC voltage between the conductor and the semiconductor substrate leads to a significant improvement in the high-frequency properties of the passive RF element.
  • a weakly doped region is formed under the insulator, the doping of which is selected such that depletion of interlayer charges occurs in the boundary region.
  • the passive RF element in particular comprises a semiconductor substrate, an insulator arranged on the semiconductor substrate, by means of which interlayer charges are generated at the interface between the semiconductor substrate and the insulator, a conductor arranged on the insulator and a device for applying a DC voltage between the conductor and the semiconductor substrate in such a way that depletion of the interlayer charges is achieved.
  • a "window" of low attenuation results, which can be achieved by applying a DC voltage between the conductor and the semiconductor.
  • FIG. 1 is a schematic diagram showing the layer structure of a conductor-insulator-semiconductor structure for a passive RF element according to the first aspect
  • FIG. 2 shows the potential curve at the in FIG. 1 shown structure with an applied voltage of OV for - 5 - -
  • FIG. 3 shows the course of the concentrations of the freely movable charge carriers in the depletion region for different applied voltages
  • FIG. 4 the local distribution of the specific resistance in the semiconductor
  • FIG. 5 the voltage dependence of the damping using the example of a coplanar line
  • FIG. 6 shows the voltage dependence of the elements of the line equivalent circuit diagram of a coplanar line
  • FIG. 7 is an illustration of sequential method steps for producing a passive high-frequency component in accordance with the second aspect of the present invention.
  • FIG. 8 shows a measuring arrangement for characterizing coplanar waveguide structures
  • FIG. 9 shows a signal flow graph for the extraction of line parameters.
  • FIG. 1 schematically shows a high-frequency (RF) element according to the first aspect, which consists of a conductor 10, an insulator 12 and a semiconductor 14.
  • the conductor 10 can either be made of metal, e.g. As aluminum, or be formed from polysilicon.
  • the semiconductor 14 can be a silicon semiconductor, which is why the insulator 12 is preferably designed as silicon oxide (Si0 2 ).
  • Si0 2 silicon oxide
  • MOS metal-oxide-semiconductor
  • the passive RF element according to the present invention further comprises connections 16a and 16b, which are arranged on the metal 10 or on the semiconductor 14 and can serve as a device for applying a direct voltage U.
  • a semiconductor substrate which has a thickness in the x-direction of 100 ⁇ m, while the silicon oxide 12 has a thickness of 2.5 ⁇ m and the metallization 10 is 0.5 ⁇ m thick.
  • FIG. 2 shows the potential curve of the in FIG. 1 shown MIS transition with an applied voltage U of OV for different substrate resistances and an interfacial density of 2-10 11 cm ⁇ 2 .
  • the in FIG. 2 shows the potential profile for the semiconductor materials with the individual specific resistances corresponds to the profile of the voltage difference between the intrinsic conduction level and the quasi-Fermi level of the semiconductor.
  • the 0 potential corresponds to the position of the Fermi level of intrinsic (intrinsically conductive) silicon. In the interior of the semiconductor (x> 0) at the point where there is a parallel potential profile, negative values result from the p-doping of the silicon used.
  • Different specific substrate resistances cause a difference in the position of the respective quasi-Fermi levels due to the different basic doping. An increase in the specific resistance (reduction in the p-type basic doping) consequently leads to an approximation to the O potential.
  • the semiconductor is depleted in this area by freely movable charge carriers, while the acceptor ions firmly anchored in the crystal lattice determine the charge of the semiconductor. If the interface between the oxide and the semiconductor is approached further, the specific resistance drops again as a result of the increasing proportion of freely mobile electrons due to the positive charges present in the oxide.
  • FIG. 3 shows the location-dependent distributions of the freely movable charge carriers for different ones between the conductor - 9 - ⁇
  • DC voltage does not mean strictly a DC voltage.
  • the “DC voltage” can also be a low-frequency voltage, the frequency of which is significantly lower than the frequency of the electromagnetic waves that can propagate on the passive high-frequency components according to the invention.
  • the “DC voltage” according to this invention can also contain high-frequency noise components, the alternating amplitude of which, however, is significantly less than the DC amplitude of the voltage.
  • the inversion between the oxide 12 and the semiconductor 14 will result in a hole accumulation, especially if the semiconductor 14 is n-doped.
  • positive voltages U are of course necessary in order to deplete this inversion layer according to the invention in order to achieve a higher specific resistance of the semiconductor 14. From FIG. 3 it can be seen that in the example of the present invention described in this application, a very high electron density is present between the oxide 12 and the semiconductor 14 at a voltage of -23 V. Similarly, the hole density at this voltage is very small, as can be seen from the right drawing of FIG. 3 can be seen. If the applied voltage U is made more negative, the electron density decreases, while the hole density increases.
  • FIG. 4 shows the simulated local course of the specific sheet resistance.
  • the specific resistance is greatly reduced as a result of the inversion layer in the interface area (in this case about 90 ⁇ cm).
  • Passive radio frequency elements according to the present invention are in the area of high resistance, i. H. low attenuation, use according to the invention, in particular coplanar lines, integrated coils and interdigital capacitors.
  • FIG. 5 shows the damping behavior of a preferred exemplary embodiment of the present invention, namely the damping behavior of a coplanar line.
  • all metal components of the coplanar line ie the inner strip and the outer ground planes, were placed at the same potential in order to achieve the most uniform possible distribution of the static electric field which is generated by applying the DC voltage between the metal and the semiconductor .
  • FIG. 5 underlines that a substantial reduction in damping, e.g. B. at a frequency of 5 GHz of 0.27 dB / mm at 0 V applied voltage to 0.1 dB / mm at an externally applied voltage of about -30 V is achieved.
  • FIG. 5 further shows that at a voltage of approximately -30 V the inversion in the semiconductor is reduced, after which the attenuation of the coplanar line increases again, since such high negative voltages will lead to hole accumulation in the boundary layer region.
  • the negative voltage between the back of the wafer, i. H. on the semiconductor 14, and all metallizations on the oxide 12 are applied.
  • a reduction in damping can also be achieved if the voltage between the back of the wafer, i. H. the semiconductor 14, and for example only the inner conductor of a coplanar line or only the ground surfaces of the coplanar line.
  • integrated coils in which the integrated coil structure and the surrounding ground plane can be kept at the same potential or at different potential. With interdigital capacitors it is also possible to keep both electrode finger structures at the same potential.
  • a reduction in the damping for electromagnetic waves is also achieved, however, if only one finger electrode is negatively biased towards the back of the wafer.
  • FIG. 6 finally shows the four frequency-dependent line equivalent circuit parameters, starting from a simple line equivalent circuit diagram consisting of a series connection of a resistor and an inductor and a parallel connection of a capacitor and a conductance, as is generally known.
  • FIG. 6 shows the individual equivalent circuit parameters for different applied voltages between 0 V and 28 V. It can clearly be seen that the serial elements, ie the inductance coating and the resistance coating, are essentially not affected by the applied voltage. In contrast, the courses of the capacitance and the conductance covering show a significant voltage dependency.
  • a DC voltage between the metal 10 and the semiconductor 14 of a conductor-insulator-semiconductor structure can therefore not only reduce the attenuation of passive high-frequency components, but also increase resonance frequencies that may occur in order to increase the range of use of integrated passive high-frequency components at higher operating frequencies to enlarge.
  • Passive RF elements according to the present invention and methods for operating passive RF elements according to the present invention thus enable a substantial reduction in the attenuation for electromagnetic waves.
  • the depletion of the inversion layer between the semiconductor and the oxide is extremely important, since a commonly used field threshold implantation is not possible.
  • the semiconductor substrates used for the passive RF elements according to the present invention can also be low-resistance, the advantageous use of the present invention is particularly evident in the case of high-resistance substrates (resistivity greater than 100 ⁇ cm).
  • FIG. 7 shows a diagram of sequential method steps for producing a passive high-frequency element according to the second aspect of the present invention.
  • SIMOX technology is preferably used for the passive high-frequency element according to the second aspect of the present invention.
  • SIMOX means Separation by Implantation of Oxygen. This means that highly accelerated oxygen atoms are shot into a silicon wafer, which reach a certain depth of penetration into the silicon in accordance with the selected energy. The crystal structure in the Si surface is largely destroyed. The crystal structure is restored by a healing step at a very high temperature, which is, for example, between 1000 ° C. and 1375 ° C. and preferably in a range between 1250 ° C. to 1350 ° C.
  • the effect occurs that the oxygen with Si reacts and forms an Si0 2 layer under the Si surface.
  • the special thing here is that the interface between the silicon and the silicon dioxide is very clearly formed, and is comparable to the interface of Si with an SiO 2 layer produced by oxidation.
  • the interface between the buried silicon dioxide layer and the silicon substrate can be regarded as an insulator-semiconductor junction, as was also explained and carried out in connection with the first aspect of the present invention. The considerations can therefore also be used in the case of a buried silicon oxide layer.
  • this buried oxide layer is very advantageous because it causes parasitic capacitances, for. B. the source and drain regions to the semiconductor substrate (or Si bulk) can be significantly reduced. For this reason, high-resistance wafers are used, which can have resistivities of up to 10 k ⁇ cm, as already mentioned at the beginning.
  • a wide depletion region was created under the Si surface by applying a suitable DC voltage in order to reduce the undesired charge accumulations which could lead to inversion, in order to reduce the specific resistance or the damping due to the eliminate higher conductivity in these areas.
  • a weakly doped semiconductor region is now generated under the insulator in order to build the effect of the application of the DC voltage, as it were, firmly into the passive element. Therefore, all previously made considerations regarding the effect of the direct voltage on the interlayer charges also apply to the second aspect.
  • any special voltage value can be imitated by a suitable choice of the doping parameters for the doped region under the insulator.
  • the first step of FIG. 7 shows a raw semiconductor substrate 14, which is preferably made of silicon. This is treated by means of oxygen implantation 20 in order to produce the buried oxide layer mentioned. This oxide layer is shown at 22 in the second field of FIG. 7 designated.
  • a thin silicon film 24 has formed over the oxide layer by annealing the Si crystal.
  • the buried Si0 2 layer is, for example, 400 nm thick, while the silicon film 24 will only have a thickness of 100 nm.
  • a selective oxidation of the silicon film is now carried out, with which the latter now forms a thicker silicon oxide layer together with the buried silicon oxide layer, which forms the insulator 12 of FIG. 1 corresponds.
  • a weakly doped semiconductor layer is now formed under the insulator 12 in order to achieve depletion of the interlayer charges between the insulator 12 and the semiconductor substrate 14 even without applying a DC voltage.
  • the p-type is selected here as the doping type.
  • the weakly doped p "silicon layer 24 is produced by means of a boron implantation, the doping concentration is preferably in the range of 10 11 -.. 10 13 cm -2
  • the boron implantation is to take place with high energy, the energy in the range 200 ... 1000 keV must lie so that an implantation can take place through the insulator 12, in this case the silicon oxide, and the thickness of the weakly doped layer and especially the doping concentration can essentially achieve any charge state which can also be obtained by applying a voltage Advantageous in the passive high frequency element that with respect to sub-picture 4 of FIG.
  • FIG. 8 shows a measuring arrangement for characterizing passive high-frequency elements, in this example of coplanar waveguide structures.
  • the left half of FIG. 8 shows a known network analyzer with which the method according to the invention for determining characteristic properties of a passive high-frequency component can be carried out according to a further aspect of the present invention.
  • the network analyzer additionally has a DC voltage source U in order to be able to apply different voltages to the coplanar waveguide structure in such a way that depletion of interlayer charges between the semiconductor substrate and the insulator formed thereon can be achieved.
  • FIG. 8 shows an enlarged schematic plan view of the measuring tip arrangement for transmission measurement.
  • the coplanar line as an example of a high-frequency element, which is contacted on the left and right by network analyzer measuring tips.
  • the case shown here is a so-called ON wafer measurement.
  • the choice of coplanar measuring heads assumes a very good adaptation of the field distributions.
  • FIG. 8 shown measurement setup used.
  • a DC voltage source is used during the measurements in order to determine the properties of the coplanar lines at the respective DC voltage values by determining their four-pole parameters and preferably their scattering parameters. The corresponding line parameters are then determined directly from the measured values.
  • FIG. 9 shows a signal flow graph for extracting the line parameters.
  • the measuring method according to the invention which, like the method for operating the passive RF element and the passive RF element itself, is based on the knowledge that A targeted depletion of the interlayer loads in order to improve circuit-relevant properties can be applied to all known methods for determining material parameters via CV dependencies. While known CV measurements are associated with large measurement errors, particularly in the case of high-resistance substrates, CV measurements also give an integral picture of the transition. However, the measuring methods according to the invention are particularly sensitive to the nature of the material immediately below the oxide and thus allow a differential analysis of this area. Preferred characteristic properties which can be determined from the four-pole parameters are, in particular, the attenuation, the shortening factor and the characteristic impedance for lines and the quality for coils or capacitors.

Abstract

L'invention concerne un élément haute fréquence comprenant un substrat semi-conducteur (14), un isolateur (12) au moyen duquel des charges de couches d'interface sont produites dans une zone à couche limite, entre le substrat semi-conducteur (14) et l'isolateur (12), et un conducteur (10) disposé sur l'isolateur (12). En appliquant une tension uniforme (U) entre le conducteur (10) et le substrat semi-conducteur (14) et/ou à travers une zone faiblement dopée sous l'isolateur (12), on obtient une déplétion des charges des couches d'interface, de sorte que la densité des porteurs de charge mobiles dans la zone se trouvant au niveau de la transition de l'isolateur (12) vers le semi-conducteur (14) est sensiblement réduite. Une fenêtre de faible amortissement est prévue pour des éléments haute fréquence passifs conformes à l'invention, ladite fenêtre étant délimitée dans la zone de la couche limite, d'une part, par une faible déplétion des charges des couches d'interface et, d'autre part, par un faible enrichissement des charges de polarité opposée aux charges des couches d'interface.
PCT/EP1997/006012 1997-10-30 1997-10-30 Element hf passif et procede permettant son fonctionnement, ainsi que son procede de fabrication et procede de determination de proprietes caracteristiques WO1999023705A1 (fr)

Priority Applications (1)

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PCT/EP1997/006012 WO1999023705A1 (fr) 1997-10-30 1997-10-30 Element hf passif et procede permettant son fonctionnement, ainsi que son procede de fabrication et procede de determination de proprietes caracteristiques

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PCT/EP1997/006012 WO1999023705A1 (fr) 1997-10-30 1997-10-30 Element hf passif et procede permettant son fonctionnement, ainsi que son procede de fabrication et procede de determination de proprietes caracteristiques

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2525778A1 (fr) * 1982-04-23 1983-10-28 Thomson Csf Dispositif de modulation d'onde transmise dans un guide d'onde optique
US4604304A (en) * 1985-07-03 1986-08-05 Rca Corporation Process of producing thick layers of silicon dioxide
EP0464453A1 (fr) * 1990-06-18 1992-01-08 Kabushiki Kaisha Toshiba Condensateur de type MIS ayant un changement de capacitance réduit lors de polarisations selon des directions directes et inverses
US5173835A (en) * 1991-10-15 1992-12-22 Motorola, Inc. Voltage variable capacitor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2525778A1 (fr) * 1982-04-23 1983-10-28 Thomson Csf Dispositif de modulation d'onde transmise dans un guide d'onde optique
US4604304A (en) * 1985-07-03 1986-08-05 Rca Corporation Process of producing thick layers of silicon dioxide
EP0464453A1 (fr) * 1990-06-18 1992-01-08 Kabushiki Kaisha Toshiba Condensateur de type MIS ayant un changement de capacitance réduit lors de polarisations selon des directions directes et inverses
US5173835A (en) * 1991-10-15 1992-12-22 Motorola, Inc. Voltage variable capacitor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
A. HÜRRICH ET AL.: "SOI-CMOS technology with monothically integrated active and pasive RF devices on high resistivity SIMOX substrates", PROCEEDINGS 1996 IEEE INTERNATIONAL SOI CONFERENCE, October 1996 (1996-10-01), pages 130- - 131, XP002069620 *

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