WO1999031732A3 - Semiconductor processing method and field effect transistor - Google Patents

Semiconductor processing method and field effect transistor Download PDF

Info

Publication number
WO1999031732A3
WO1999031732A3 PCT/US1998/027109 US9827109W WO9931732A3 WO 1999031732 A3 WO1999031732 A3 WO 1999031732A3 US 9827109 W US9827109 W US 9827109W WO 9931732 A3 WO9931732 A3 WO 9931732A3
Authority
WO
WIPO (PCT)
Prior art keywords
gate
chlorine
fluorine
oxide layer
proximate
Prior art date
Application number
PCT/US1998/027109
Other languages
French (fr)
Other versions
WO1999031732A2 (en
Inventor
Salman Akram
Akram Ditali
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to JP2000539530A priority Critical patent/JP2002509361A/en
Priority to AU19331/99A priority patent/AU1933199A/en
Publication of WO1999031732A2 publication Critical patent/WO1999031732A2/en
Publication of WO1999031732A3 publication Critical patent/WO1999031732A3/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28176Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the definitive gate conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/511Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/512Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being parallel to the channel plane
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66575Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314Inorganic layers
    • H01L21/316Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604Deposition from a gas or vapour
    • H01L21/31629Deposition of halogen doped silicon oxide, e.g. fluorine doped silicon oxide

Abstract

A method of forming a transistor gate includes forming a gate oxide layer over a semiconductive substrate. Chlorine is provided within the gate oxide layer. A gate is formed proximate the gate oxide layer. In another method, a gate and a gate oxide layer are formed in overlapping relation, with the gate having opposing edges and a center therebetween. At least one of chlorine or fluorine is concentrated in the gate oxide layer within the overlap more proximate at least one of the gate edges than the center. Preferably, the central region is substantially undoped with fluorine and chlorine. The chlorine and/or fluorine can be provided by forming sidewall spacers proximate the opposing lateral edges of the gate, with the sidewall spacers comprising at least one of chlorine or fluorine. The spacers are annealed at a temperature and for a time effective to diffuse the fluorine or chlorine into the gate oxide layer to beneath the gate. Transistors and transistor gates fabricated according to the above and other methods are disclosed. Further, a transistor includes a semiconductive material and a transistor gate having gate oxide positioned therebetween. A source is formed laterally proximate one of the gate edges and a drain is formed laterally proximate the other of the gate edges. First insulative spacers are formed proximate the gate edges, with the first insulative spacers being doped with at least one of chlorine or fluorine. Second insulative spacers formed over the first insulative spacers.
PCT/US1998/027109 1997-12-18 1998-12-18 Semiconductor processing method and field effect transistor WO1999031732A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2000539530A JP2002509361A (en) 1997-12-18 1998-12-18 Semiconductor manufacturing method and field effect transistor
AU19331/99A AU1933199A (en) 1997-12-18 1998-12-18 Semiconductor processing method and field effect transistor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US99366397A 1997-12-18 1997-12-18
US08/993,663 1997-12-18

Publications (2)

Publication Number Publication Date
WO1999031732A2 WO1999031732A2 (en) 1999-06-24
WO1999031732A3 true WO1999031732A3 (en) 1999-07-29

Family

ID=25539806

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1998/027109 WO1999031732A2 (en) 1997-12-18 1998-12-18 Semiconductor processing method and field effect transistor

Country Status (5)

Country Link
US (3) US6593196B2 (en)
JP (1) JP2002509361A (en)
KR (1) KR100389899B1 (en)
AU (1) AU1933199A (en)
WO (1) WO1999031732A2 (en)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3687776B2 (en) * 1999-12-14 2005-08-24 旭化成マイクロシステム株式会社 Manufacturing method of semiconductor device
US7247919B1 (en) 2000-08-25 2007-07-24 Micron Technology, Inc. Method and device to reduce gate-induced drain leakage (GIDL) current in thin gate oxides MOSFETs
KR100383083B1 (en) * 2000-09-05 2003-05-12 아남반도체 주식회사 Flash memory having low operation voltage and manufacturing method thereof
JP2003204063A (en) 2002-01-10 2003-07-18 Toshiba Corp Semiconductor device and its manufacturing method
US6544853B1 (en) * 2002-01-18 2003-04-08 Infineon Technologies Ag Reduction of negative bias temperature instability using fluorine implantation
US6825133B2 (en) * 2003-01-22 2004-11-30 Taiwan Semiconductor Manufacturing Company, Ltd. Use of fluorine implantation to form a charge balanced nitrided gate dielectric layer
US6780730B2 (en) * 2002-01-31 2004-08-24 Infineon Technologies Ag Reduction of negative bias temperature instability in narrow width PMOS using F2 implantation
US6825684B1 (en) 2002-06-10 2004-11-30 Advanced Micro Devices, Inc. Hot carrier oxide qualification method
US6856160B1 (en) 2002-06-10 2005-02-15 Advanced Micro Devices, Inc. Maximum VCC calculation method for hot carrier qualification
JP2004022575A (en) 2002-06-12 2004-01-22 Sanyo Electric Co Ltd Semiconductor device
KR100464852B1 (en) * 2002-08-07 2005-01-05 삼성전자주식회사 Method of forming gate oxide layer in semiconductor device
JP3851896B2 (en) * 2002-09-27 2006-11-29 株式会社東芝 Manufacturing method of semiconductor device
KR100483438B1 (en) * 2002-12-09 2005-04-14 삼성전자주식회사 a method of forming cell of non-volatile memory
DE102004044667A1 (en) * 2004-09-15 2006-03-16 Infineon Technologies Ag Semiconductor component and associated production method
US20060105530A1 (en) * 2004-11-12 2006-05-18 Nanya Technology Corporation Method for fabricating semiconductor device
EP3925997A3 (en) 2005-04-22 2022-04-20 Mitsubishi Chemical Corporation Biomass-resource-derived polyester and production process thereof
KR100678477B1 (en) * 2005-06-15 2007-02-02 삼성전자주식회사 Nanocrystal nonvolatile memory devices and method of fabricating the same
US20080135953A1 (en) * 2006-12-07 2008-06-12 Infineon Technologies Ag Noise reduction in semiconductor devices
WO2008136225A1 (en) * 2007-04-27 2008-11-13 Semiconductor Energy Laboratory Co., Ltd. Soi substrate and manufacturing method of the same, and semiconductor device
JP2008283051A (en) * 2007-05-11 2008-11-20 Toshiba Corp Semiconductor storage device and manufacturing method of semiconductor storage device
US8674434B2 (en) * 2008-03-24 2014-03-18 Micron Technology, Inc. Impact ionization devices
US9490368B2 (en) * 2010-05-20 2016-11-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method of the same
US8828834B2 (en) 2012-06-12 2014-09-09 Globalfoundries Inc. Methods of tailoring work function of semiconductor devices with high-k/metal layer gate structures by performing a fluorine implant process
US8975143B2 (en) * 2013-04-29 2015-03-10 Freescale Semiconductor, Inc. Selective gate oxide properties adjustment using fluorine
US9263270B2 (en) 2013-06-06 2016-02-16 Globalfoundries Inc. Method of forming a semiconductor device structure employing fluorine doping and according semiconductor device structure
CN104979391B (en) * 2014-04-08 2019-04-23 联华电子股份有限公司 Semiconductor element and preparation method thereof
WO2018125154A1 (en) * 2016-12-29 2018-07-05 Intel Corporation End of line parasitic capacitance improvement using implants
US11075283B2 (en) * 2018-10-30 2021-07-27 Taiwan Semiconductor Manufacturing Co., Ltd. Dielectric constant reduction of gate spacer

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01272161A (en) * 1987-07-14 1989-10-31 Oki Electric Ind Co Ltd Manufacture of mos type fet
JPH0462974A (en) * 1990-06-30 1992-02-27 Fuji Xerox Co Ltd Mos field-effect transistor and manufacture thereof
DE4229574A1 (en) * 1991-09-05 1993-03-11 Mitsubishi Electric Corp FET with good current control even at low gate voltage - comprises principal surface and source and drain zones spaced apart on semiconductor substrate and nitride- and oxide-films on principal surface
US5506178A (en) * 1992-12-25 1996-04-09 Sony Corporation Process for forming gate silicon oxide film for MOS transistors
US5516707A (en) * 1995-06-12 1996-05-14 Vlsi Technology, Inc. Large-tilted-angle nitrogen implant into dielectric regions overlaying source/drain regions of a transistor
US5672525A (en) * 1996-05-23 1997-09-30 Chartered Semiconductor Manufacturing Pte Ltd. Polysilicon gate reoxidation in a gas mixture of oxygen and nitrogen trifluoride gas by rapid thermal processing to improve hot carrier immunity

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3933530A (en) 1975-01-28 1976-01-20 Rca Corporation Method of radiation hardening and gettering semiconductor devices
GB8421967D0 (en) 1984-08-30 1984-10-03 Hickory Springs Mfg Co Polyurethane foams
US5243212A (en) 1987-12-22 1993-09-07 Siliconix Incorporated Transistor with a charge induced drain extension
US5225355A (en) 1988-02-26 1993-07-06 Fujitsu Limited Gettering treatment process
US4949136A (en) 1988-06-09 1990-08-14 University Of Connecticut Submicron lightly doped field effect transistors
JPH02173611A (en) 1988-12-27 1990-07-05 Hitachi Cable Ltd Kaleidoscope
JPH05102067A (en) 1991-10-11 1993-04-23 Fujitsu Ltd Manufacture of semiconductor device
JP2842491B2 (en) 1992-03-06 1999-01-06 日本電気株式会社 Method for manufacturing semiconductor device
US5382533A (en) 1993-06-18 1995-01-17 Micron Semiconductor, Inc. Method of manufacturing small geometry MOS field-effect transistors having improved barrier layer to hot electron injection
JPH0851108A (en) 1994-05-31 1996-02-20 Kawasaki Steel Corp Semiconductor device and manufacture thereof
US5721170A (en) 1994-08-11 1998-02-24 National Semiconductor Corporation Method of making a high-voltage MOS transistor with increased breakdown voltage
US5571734A (en) 1994-10-03 1996-11-05 Motorola, Inc. Method for forming a fluorinated nitrogen containing dielectric
JPH08139315A (en) 1994-11-09 1996-05-31 Mitsubishi Electric Corp Mos transistor, semiconductor device and their manufacture
JP3266433B2 (en) 1994-12-22 2002-03-18 三菱電機株式会社 Method for manufacturing semiconductor device
US5710450A (en) 1994-12-23 1998-01-20 Intel Corporation Transistor with ultra shallow tip and method of fabrication
KR960030440A (en) 1995-01-12 1996-08-17 모리시다 요이치 Semiconductor device and manufacturing method thereof
JP3811518B2 (en) 1995-01-12 2006-08-23 松下電器産業株式会社 Semiconductor device and manufacturing method thereof
JPH08213605A (en) 1995-02-06 1996-08-20 Oki Electric Ind Co Ltd Method of manufacturing mos transistor
US5714875A (en) * 1995-02-23 1998-02-03 Atomic Energy Of Canada Limited Electron beam stop analyzer
SG50741A1 (en) 1995-07-26 1998-07-20 Chartered Semiconductor Mfg Method for minimizing the hot carrier effect in m-mosfet devices
US5705409A (en) 1995-09-28 1998-01-06 Motorola Inc. Method for forming trench transistor structure
US5966623A (en) * 1995-10-25 1999-10-12 Eastman Kodak Company Metal impurity neutralization within semiconductors by fluorination
US5599726A (en) 1995-12-04 1997-02-04 Chartered Semiconductor Manufacturing Pte Ltd Method of making a conductive spacer lightly doped drain (LDD) for hot carrier effect (HCE) control
US5605848A (en) 1995-12-27 1997-02-25 Chartered Semiconductor Manufacturing Pte Ltd. Dual ion implantation process for gate oxide improvement
US5716875A (en) 1996-03-01 1998-02-10 Motorola, Inc. Method for making a ferroelectric device
JPH09252117A (en) 1996-03-14 1997-09-22 Sanyo Electric Co Ltd Field-effect transistor
US5672544A (en) 1996-04-22 1997-09-30 Pan; Yang Method for reducing silicided poly gate resistance for very small transistors
US5807771A (en) 1996-06-04 1998-09-15 Raytheon Company Radiation-hard, low power, sub-micron CMOS on a SOI substrate
US6087239A (en) * 1996-11-22 2000-07-11 Micron Technology, Inc. Disposable spacer and method of forming and using same
US5840610A (en) * 1997-01-16 1998-11-24 Advanced Micro Devices, Inc. Enhanced oxynitride gate dielectrics using NF3 gas
US6004852A (en) 1997-02-11 1999-12-21 United Microelectronics Corp. Manufacture of MOSFET having LDD source/drain region
US5923949A (en) 1997-03-21 1999-07-13 Advanced Micro Devices Semiconductor device having fluorine bearing sidewall spacers and method of manufacture thereof
US5763312A (en) 1997-05-05 1998-06-09 Vanguard International Semiconductor Corporation Method of fabricating LDD spacers in MOS devices with double spacers and device manufactured thereby
US5851890A (en) 1997-08-28 1998-12-22 Lsi Logic Corporation Process for forming integrated circuit structure with metal silicide contacts using notched sidewall spacer on gate electrode
US6004857A (en) * 1998-09-17 1999-12-21 Taiwan Semiconductor Manufacturing Company Method to increase DRAM capacitor via rough surface storage node plate

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01272161A (en) * 1987-07-14 1989-10-31 Oki Electric Ind Co Ltd Manufacture of mos type fet
JPH0462974A (en) * 1990-06-30 1992-02-27 Fuji Xerox Co Ltd Mos field-effect transistor and manufacture thereof
DE4229574A1 (en) * 1991-09-05 1993-03-11 Mitsubishi Electric Corp FET with good current control even at low gate voltage - comprises principal surface and source and drain zones spaced apart on semiconductor substrate and nitride- and oxide-films on principal surface
US5506178A (en) * 1992-12-25 1996-04-09 Sony Corporation Process for forming gate silicon oxide film for MOS transistors
US5516707A (en) * 1995-06-12 1996-05-14 Vlsi Technology, Inc. Large-tilted-angle nitrogen implant into dielectric regions overlaying source/drain regions of a transistor
US5672525A (en) * 1996-05-23 1997-09-30 Chartered Semiconductor Manufacturing Pte Ltd. Polysilicon gate reoxidation in a gas mixture of oxygen and nitrogen trifluoride gas by rapid thermal processing to improve hot carrier immunity

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 014, no. 038 (E - 878) 24 January 1990 (1990-01-24) *
PATENT ABSTRACTS OF JAPAN vol. 016, no. 271 (E - 1218) 18 June 1992 (1992-06-18) *

Also Published As

Publication number Publication date
KR100389899B1 (en) 2003-07-04
KR20010033261A (en) 2001-04-25
US7189623B2 (en) 2007-03-13
US20030017689A1 (en) 2003-01-23
US6288433B1 (en) 2001-09-11
WO1999031732A2 (en) 1999-06-24
JP2002509361A (en) 2002-03-26
AU1933199A (en) 1999-07-05
US20060001054A1 (en) 2006-01-05
US6593196B2 (en) 2003-07-15

Similar Documents

Publication Publication Date Title
WO1999031732A3 (en) Semiconductor processing method and field effect transistor
KR950002073A (en) Thin film transistor and its manufacturing method
EP0235705A3 (en) Self-aligned ultra high-frequency field-effect transistor, and method for manufacturing the same
KR970007965B1 (en) Structure and fabrication method of tft
TW327240B (en) Semiconductor device and process for producing the same
TW330309B (en) Novel transistor with ultra shallow tip and method of fabrication
MY123831A (en) Method for manufacturing a semiconductor device
TW345746B (en) Upper gate type thin film transistor and process for producing the same
KR960012583B1 (en) Tft (thin film transistor )and the method of manufacturing the same
WO2003032401A1 (en) Semiconductor device and its manufacturing method
WO2002075781A3 (en) Method of forming silicide contacts and device incorporating same
EP0364818A3 (en) Method for making a polysilicon transistor
TW340965B (en) Process to separate the doping of polygate and source drain regions in dual gate field effect transistors
TW200614387A (en) Method of fabricating mos transistor by millisecond anneal
WO1998053491A3 (en) Manufacture of a semiconductor device with a mos transistor having an ldd structure
KR920020594A (en) LDD transistor structure and manufacturing method
KR930005272A (en) LDD type MOS transistor and manufacturing method thereof
JPS6439773A (en) Manufacture of semiconductor device
JPH0231463A (en) Mis transistor
TW245815B (en) Process for self-aligned metal silicide
KR950012645A (en) Method of manufacturing thin film transistor of semiconductor device
JPS6465875A (en) Thin film transistor and manufacture thereof
JPS57211779A (en) Field effect transistor
KR940003073A (en) Method for manufacturing MOS transistor and device accordingly
KR930015087A (en) LDD transistor structure and manufacturing method

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT UA UG UZ VN YU ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW SD SZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

AK Designated states

Kind code of ref document: A3

Designated state(s): AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT UA UG UZ VN YU ZW

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): GH GM KE LS MW SD SZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
WWE Wipo information: entry into national phase

Ref document number: 1020007006697

Country of ref document: KR

ENP Entry into the national phase

Ref country code: JP

Ref document number: 2000 539530

Kind code of ref document: A

Format of ref document f/p: F

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase
WWP Wipo information: published in national office

Ref document number: 1020007006697

Country of ref document: KR

WWG Wipo information: grant in national office

Ref document number: 1020007006697

Country of ref document: KR