WO1999042945A1 - Non-lot based method for assembling integrated circuit devices - Google Patents

Non-lot based method for assembling integrated circuit devices Download PDF

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Publication number
WO1999042945A1
WO1999042945A1 PCT/US1999/001916 US9901916W WO9942945A1 WO 1999042945 A1 WO1999042945 A1 WO 1999042945A1 US 9901916 W US9901916 W US 9901916W WO 9942945 A1 WO9942945 A1 WO 9942945A1
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WO
WIPO (PCT)
Prior art keywords
devices
code
mounting substrate
assembly
substrates
Prior art date
Application number
PCT/US1999/001916
Other languages
French (fr)
Inventor
Kevin Wilson
Ron Hjorth
Original Assignee
Micron Technology, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology, Inc. filed Critical Micron Technology, Inc.
Priority to JP2000532808A priority Critical patent/JP4008198B2/en
Priority to AU24816/99A priority patent/AU2481699A/en
Priority to EP99904416A priority patent/EP1062618A4/en
Publication of WO1999042945A1 publication Critical patent/WO1999042945A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H01L29/34—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being on the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67294—Apparatus for monitoring, sorting or marking using identification means, e.g. labels on substrates or labels on containers
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/418—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS], computer integrated manufacturing [CIM]
    • G05B19/4183—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS], computer integrated manufacturing [CIM] characterised by data acquisition, e.g. workpiece identification
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67276—Production flow monitoring, e.g. for increasing throughput
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/30—Nc systems
    • G05B2219/31—From computer integrated manufacturing till monitoring
    • G05B2219/31307—Identification structure is partly a copy of operating structure
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/30—Nc systems
    • G05B2219/36—Nc in input of data, input key till input tape
    • G05B2219/36371—Barcode reader
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/30—Nc systems
    • G05B2219/45—Nc applications
    • G05B2219/45031—Manufacturing semiconductor wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
    • H01L2223/5444—Marks applied to semiconductor devices or parts containing identification or tracking information for electrical read out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/5448—Located on chip prior to dicing and remaining on chip after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Definitions

  • TECHNICAL FIELD This invention relates in general to methods for manufacturing integrated circuit (IC) devices. More specifically, the invention relates to non-lot based IC device manufacturing methods in which individual devices can be uniquely identified during their assembly, which enables individual tracking of the devices through assembly and, in turn, enables assembly of the devices in a substantially continuous manner.
  • a process 10 for manufacturing integrated circuit (IC) devices typically begins with ICs being fabricated on the surfaces of wafers 12 of semiconductor material, such as silicon. Less typically, ICs may also be formed in layers of silicon deposited on layers of sapphire (known as Silicon-on-Sapphire (SOS)), insulating material (SOI), or glass (SOG).
  • SOS Silicon-on-Sapphire
  • SOI insulating material
  • SOG glass
  • ICs are electronically probed to determine whether they are functional (i.e. , "good") or nonfunctional (i.e. , "bad”).
  • a computer then stores electronic wafer maps 14 of the wafers 12 identifying the locations of the good and bad ICs on the wafers 12.
  • ICs are sawed from their wafers 12 into discrete IC dice (also known as "chips") using high-speed precision dicing equipment.
  • IC dice identified as good by their wafer maps 14 are then each "picked” by automated equipment from their sawed wafers 12 and "placed” on an epoxy coated bonding site of one of a set of lead frames 16, while IC dice identified as bad are discarded into a scrap bin 18.
  • the epoxy attaching the good IC dice to their lead frames 16 is allowed to cure, and the attached dice are then wire bonded to their lead frames 16 using high speed bonding equipment. At this point in the process 10, the lead frames 16 of IC dice are still interconnected.
  • IC dice and their lead frames 16 are formed into IC packages using a hot thermosetting plastic encapsulant injected into a mold. Leads of the lead frames 16 project from the IC packages after encapsulation, and these leads -2- are dipped in a cleansing chemical bath in a process referred to as "de-flash. " After de-flash, IC packages are cured to set their plastic encapsulant, and their projecting leads are then electroplated with a lead/tin finish.
  • connections between the lead frames 16 of different IC packages are cut to "singulate" the IC packages into discrete IC devices, and the leads projecting from each IC device are then trimmed and formed into their final form.
  • the IC devices are then tested in a simple electronic test that checks for "opens” (i.e. , no connection) in the devices where connections should exist and "shorts" (i.e. , a connection) where connections should not exist. Devices that fail the opens/shorts test are discarded into the scrap bin 18, and devices that pass proceed to extensive back-end test procedures where they are tested for functionality before being shipped to customers.
  • ICs are typically tracked by lot number through the fabrication, probe, assembly, and back-end test steps described above so the location of particular lots of ICs within the manufacturing process 10 can be determined.
  • Lot numbers are first assigned to ICs when they are fabricated on semiconductor wafers 12.
  • a group of 20-50 wafers 12 receive a unique lot number (e.g. , 36/1/9970).
  • the wafers 12 are typically split into several sub-lots, with each sub-lot being assigned a new lot number (sometimes referred to as a "sub-lot" number) that is a modified form of the group's original lot number (e.g. , 36/1/9970/0, 36/1/9970/1, . . .
  • FIG. 2 An example of ICs being tracked through a portion of assembly using lot numbers is shown in FIG. 2.
  • ICs are first processed on molding equipment to encapsulate them. Once encapsulated, ICs are fed into output carriers 20, each of which has a unique carrier number (e.g. , a bar code). The lot number of ICs fed into a particular output carrier 20 are stored in association with the carrier number of the carrier 20 in a data store 22, such as a computer memory system.
  • a data store 22 such as a computer memory system.
  • the output carriers 20 containing the encapsulated ICs are then placed on shelves, with the carrier number of each carrier 20 being stored in the data store 22 in -3- association with a unique shelf number of the shelf on which the carrier 20 is placed (e.g. , by scanning in the bar code of each carrier 20 and a bar code of the shelf on which it is placed). Later, selected ICs are retrieved by lot from the shelves for processing on de-flash equipment by first identifying the carriers 20 associated in the data store 22 with the lot number of the selected ICs, then identifying the shelves associated in the data store 22 with the carrier numbers of the identified carriers 20, and finally retrieving the identified carriers 20 from the identified shelves for processing.
  • a sub-lot (e.g. , sub-lot H) is received from an input queue 26 where sub-lots wait to proceed through the assembly step 24.
  • the assembly step 24 may be any step in the IC assembly process of FIG. 1 , including, for example, wafer saw, die attach, die cure, wire bond, molding, de-flash, lead finish, trim and form, and opens/shorts testing.
  • data 28 related to the assembly step 24 is generated.
  • data 28 may include, for example: an identification of the processing equipment and the operating personnel for the assembly step 24; information regarding the set-up of the assembly step 24; and the time and date the sub-lot advanced through the assembly step 24.
  • a process report 30 is manually or automatically generated based on the generated data 28.
  • the report 30 lists the lot number (e.g. , "H") of the ICs in the sub-lot.
  • the report 30 (often referred to as a "lot traveler") also physically accompanies the sub-lot through the remainder of the manufacturing process to ensure that the data 28 is correlated with the ICs in the sub-lot.
  • a processed sub-lot (e.g. , sub-lot H) is cleared from equipment associated with the assembly step 24 to an output queue 32 to prepare the assembly step 24 for processing the next sub-lot (e.g. , sub-lot I).
  • the next sub-lot can be processed.
  • This "clearing" process is necessary because if two sub-lots (e.g. , sub-lots H and I) proceed through -4- the assembly step 24 in a continuous manner, the conventional lot-based tracking procedure described above is unable to correlate the data 28 and the process report 30 generated as each of the two sub-lots proceed with the correct sub-lot. Instead, the data 28 for the two sub-lots is mixed, causing the conventional tracking procedure to fail to uniquely track the two sub-lots through the assembly step 24.
  • the described conventional lot-based tracking procedure is inefficient because it makes inefficient use of often very expensive manufacturing equipment and other resources by leaving sub-lots "parked" in input queues while process reports are generated and the equipment is cleared of already processed sub-lots.
  • assembly steps which use multiple machines in parallel to process a sub-lot e.g. , wire bond
  • some machines may be idle while other machines finish their allotment from the sub- lot being processed and the next sub-lot waits in an input queue.
  • generation of the process reports, as well as clearing a processed sub-lot from equipment often requires laborious manual work by operating personnel.
  • the conventional tracking procedure is not as reliable as desired, because the process reports that must physically accompany sub-lots through the manufacturing process can be lost or damaged.
  • Fuse ID's and other electrically retrievable ID codes are typically programmed into ICs by blowing selected fuses or anti-fuses in circuitry on the ICs so that the circuitry outputs the ID code when accessed.
  • None of these methods addresses the inefficiency and reliability problems associated with the conventional lot-based tracking procedure described above. Therefore, there is a need in the art for a non-lot based procedure for tracking
  • IC integrated circuit
  • COB Chip-on-Board
  • SIMMs Single In-Line Memory Modules
  • DIMMs Dual In-Line Memory Modules
  • MCMs Multi-Chip Modules
  • Each of the IC devices includes a mounting substrate, such as a lead frame or a printed circuit (PC) board, on which a substantially unique mounting substrate identification (ID) code is marked.
  • ID code may be, for example, a bar code, an Optical Character Recognition (OCR) code, or, preferably, a coded hole matrix laser scribed into the substrate.
  • the ID codes of the IC devices are read using, for example, a bar code reader, OCR reader, or optical hole reader, and the IC devices are advanced through at least one of the assembly steps in the manufacturing process in a substantially continuous manner (i.e. , without a break between lots). While the IC devices advance, they generate data related to the assembly step, such as data identifying particular equipment used during the step and the time and date each device advanced through the step. This data is then associated with the ID code of each of the IC devices to which it pertains (preferably by storing the data in a computer memory system) so the progress of individual devices can be tracked through the manufacturing process.
  • a bar code reader such as data identifying particular equipment used during the step and the time and date each device advanced through the step.
  • This data is then associated with the ID code of each of the IC devices to which it pertains (preferably by storing the data in a computer memory system) so the progress of individual devices can be tracked through the manufacturing process.
  • the invention provides for the tracking of individual IC devices during assembly, it allows the processing of IC devices without regard to lots, and thus substantially eliminates the inefficiencies associated with the conventional lot-based tracking methods previously described. Also, the invention provides a more reliable tracking method because it eliminates the need for lot travelers to accompany IC devices through the manufacturing process. Tracking continuity between fabrication, probe, assembly, and back-end testing can be maintained in a number of ways. For example, at die attach (an assembly step), the mounting substrate ID codes of the IC devices can be stored in -6- association with lot numbers, wafer numbers, or fuse IDs used during fabrication and probe. Also, at opens/shorts testing (another assembly step), for example, lot numbers can be assigned to groups of the IC devices, or fuse IDs of individual devices can be stored in association with the mounting substrate ID codes of the devices.
  • a locating method can locate an individual IC device on a manufacturing line.
  • mounting substrates of each of the IC devices are each marked with a substantially unique, optically-readable mounting substrate ID code.
  • the ID code of the device is read and stored in association with a machine ID code of the machine.
  • the ID code of the device is read and stored in association with a carrier ID number of the carrier.
  • the carrier ID numbers of carriers storing IC devices are then read and stored in association with a location code identifying the location of the carriers on the manufacturing line.
  • This location code may specify, for example, that a carrier is mounted to feed IC devices to a particular machine, mounted to receive processed IC devices from a particular machine, or stored in a particular storage location, such as a shelf or bin. Then, in order to locate an individual IC device on the manufacturing line, it is a simple matter of accessing the mounting substrate ID code of the device to be located and tracking the device to a particular machine, or to a particular carrier mounted on a machine or stored in a storage location.
  • FIG. 1 is a flow diagram illustrating a conventional lot-based integrated circuit
  • FIG. 2 is a flow diagram illustrating a portion of the conventional lot-based process of FIG. 1 in more detail
  • FIG. 3 is a flow diagram illustrating some of the inefficiencies of the conventional lot-based process of FIG. 1; -7-
  • FIG. 4 is a diagram illustrating an IC, an IC device, an assembly machine, an IC device carrier, a shelf, and a bin having identification (ID) codes and location codes associated therewith in accordance with the invention
  • FIGS. 5 A and 5B are flow diagrams of a method for assembling IC devices in accordance with the invention.
  • FIG. 6 is a flow diagram illustrating processing efficiencies gained by using the inventive method of FIGS. 5 A and 5B.
  • FIG. 4 to aid in understanding the invention. This description of general concepts will be followed by a detailed description of the illustrated embodiments of the invention, with reference made to FIGS. 5 A, 5B, and 6.
  • an IC 40 has at least one identification (ID) number, such as a lot number, a wafer number, or a fuse ID code, during fabrication and probe. This ID number allows the IC 40 to be tracked through fabrication and probe.
  • ID identification
  • the IC 40 is assembled into an IC device 42 that includes a lead frame 44 laser scribed with a coded hole matrix that gives the IC device 42 a substantially unique, optically readable lead frame ID code.
  • This lead frame ID code allows the IC device 42 to be individually tracked through assembly.
  • the lead frame ID code is stored in a computer system (not shown) in association with the ID number of the IC 40.
  • the IC device 42, and the IC 40 from which it is formed can be tracked from fabrication through assembly by referring to the unique lead frame ID code of the device 42.
  • the lead frame ID code of the IC device 42 can be correlated at the opens/shorts testing step to a fuse ID code of the device 42 used during back-end testing, for example, or IC devices coming out of assembly can be bundled into lots for processing by lot during back-end testing.
  • back-end ID codes other than fuse ID codes and lot numbers can be used in association with the invention.
  • the IC device 42 may be individually located within assembly, the machines 46 that assemble the device 42, the IC device carriers 48 that store the device 42, and the shelves 50 or bins 52 that store the carriers 48 each have a unique ID number.
  • the carriers 48 and the IC device 42 each have a location code that identifies their respective locations.
  • the location code of the IC device 42 may, for example, indicate that the device 42 is located in a particular carrier 48, or that the device 42 is being processed on a particular machine 46.
  • the location code of the carrier 48 may, for example, indicate that the carrier 48 is mounted at the input to a particular machine 46, mounted at the output of the machine 46, or stored on a particular shelf 50 or in a particular bin 52.
  • the IC device 42 can be located at any time within assembly by referring to the lead frame ID number of the device 42, which points the way to the machine 46, shelf 50, or bin 52 at which the device 42 is located.
  • an inventive method 60 for tracking IC devices through assembly begins at the die attach step 62 after the probe step has generated wafer maps 64 as previously described and the wafers (not shown) have been diced at the wafer saw step.
  • DRAMs Dynamic Random Access Memories
  • SRAMs Static RAMs
  • SDRAMs Synchronous DRAMs
  • ASICs Application Specific ICs
  • ROMs Read Only Memories
  • EEPROMs Electrically Erasable Programmable ROMs
  • flip- chip IC devices Chip-on-Board (COB) IC devices, lead frame IC devices, Single In- Line Memory Modules (SIMMs), Dual In-Line Memory Modules (DIMMs), and Multi-Chip Modules (MCMs).
  • SIMMs Single In- Line Memory Modules
  • DIMMs Dual In-Line Memory Modules
  • MCMs Multi-Chip Modules
  • inventive method 60 may begin tracking IC devices at a step within assembly that is later than the die attach step 62, but that the die attach step 62 is a convenient step in which to begin such tracking. -9-
  • the ICs (not shown) are provided to the die attach step 62 from the wafer saw step in lots identified by lot numbers.
  • the lot numbers of the lots are scanned using a bar code scanner.
  • other means may also be used to retrieve the lot numbers.
  • the invention is not limited to working with ICs initially identified by lot numbers but, rather, works equally well with ICs initially identified by any front- end ID code, including, for example, a wafer ID number or a fuse ID code.
  • Lead frames 66 used during assembly are each marked in accordance with the invention with a substantially unique lead frame ID code.
  • this "marking" process is performed by a laser scribe that produces a coded hole matrix in the rail of each of the lead frames 66, which provides a lead frame ID code that should be readable throughout the various steps of assembly.
  • other methods may be used for marking, including the use of bar codes or Optical Character Recognition (OCR) codes.
  • OCR Optical Character Recognition
  • the invention will be described with respect to lead frames, it should be understood that the invention is equally applicable to IC devices manufactured on mounting substrates other than lead frames, such as printed circuit (PC) boards, where bar codes or OCR codes may be more suitable.
  • substantially unique means sufficiently unique for each of the codes to be unique amongst those IC devices currently being manufactured.
  • a lead frame ID code of a previously manufactured IC device might be used again at a later date with an IC device then being manufactured.
  • the lead frames 66 are fed into the die attach step 62 and the lead frame ID code of each lead frame 66 is read using an optical hole reader (not shown).
  • an optical hole reader not shown
  • the ID code is a bar or OCR code
  • a bar code reader or OCR reader will be used to read the ID codes of the lead frames 66 instead.
  • a conventional Cycle Redundancy Check (CRC) may be used during reading to enhance the accuracy of the reading.
  • the ICs are each attached to one of the lead frames 66 and the lot number of each of the ICs is stored in a data store 68 in association with the lead frame ID code of the lead frame 66 to which each IC is attached.
  • Data related to the die attach step 62 such as a machine ID number of -10- equipment used during the step 62 and the date and time of processing through the step 62, is also stored in the data store 68 in association with the lead frame ID codes.
  • any ICs identified by the wafer maps 64 as being bad are diverted to repair/scrap 70.
  • the IC devices each have an associated location code.
  • the location codes of the IC devices are stored in the data store 68 in association with the lead frame ID codes of the devices, and the location codes identify the location of the devices as being in-process on the die attach equipment (not shown).
  • the data store 68 employs local data distribution and buffering techniques so that a failure of a central portion of the computer system (not shown) does not impact the local storage and use of data in the data store 68 along the manufacturing line.
  • the resulting IC devices are output from the die attach equipment and stored in carriers 72, such as IC device magazines or tubes.
  • the carriers 72 each have an associated carrier ID number (e.g. , a bar code) and location code stored in the data store 68. Because the carriers 72 are mounted at the output of the die attach equipment, the location codes of the carriers 72 indicate this. At the same time, as the IC devices exit the die attach equipment, the location codes of the devices are updated in the data store 68 to indicate that the IC devices are located in particular carriers 72.
  • the carriers 72 are stored on a shelf (not shown) or in a bin (not shown), and the location codes of the carriers 72 are updated in the date store 68 to indicate their location at a particular shelf having a shelf ID number or in a particular bin having a bin ID number.
  • FIG. 5B when the carriers 72 (FIG. 5 A) are ready to be processed at another step within assembly, such as die cure, wire bond, molding, de- flash, lead finish, trim and form, or opens/shorts testing, an operator retrieves the carriers 72 from their storage location, at which point the carriers 72 are disassociated in the data store 68 with the storage location. Of course, if the carriers 72 proceed in a continuous manner between assembly steps then the operator -11- would retrieve the carriers 72 from the previous step rather than from a storage location.
  • the carriers 72 are loaded on the processing equipment of the next assembly step, and the location codes of the carriers 72 are updated in the data store 68 to indicate the new location of the carriers 72.
  • the IC devices are then fed into the equipment from the carriers 72, the lead frame ID codes of the devices are read using an optical hole reader mounted on the equipment, and the location codes of the devices are updated in the data store 68 to indicate they are in-process on the equipment.
  • the devices are then checked to verify they are supposed to be processed in the assembly step. If any of the devices are found to be at the equipment in error, or are found to be scrap, the devices are diverted to repair/scrap 70.
  • the devices are processed on the equipment and process-related data, such as time and date of processing, is generated and stored in the data store 68 in association with the previously read lead frame ID codes of the devices.
  • the devices are then fed out of the equipment into new carriers 74, with the location codes of the carriers 74 being updated in the data store 68 to indicate the carriers 74 are mounted at the output of the equipment, and the location codes of the IC devices being updated in the data store 68 to indicate their location in particular carriers 74. If the carriers 74 are to be stored prior to being processed at the next assembly step, the carriers 74 are stored on a shelf or in a bin in a manner similar to that described above with respect to FIG. 5A.
  • a method 80 for tracking IC devices through an assembly step 2 in an IC manufacturing process in accordance with the invention includes a step 84 of receiving IC devices from multiple, mixed lots 86.
  • the step 82 may encompass processing by a single machine, part of a machine, many machines operating in series or parallel, or any combination thereof.
  • the step 84 of receiving IC devices from multiple, mixed lots 86 is without regard to the lots from which the IC devices come, and thus allows a more efficient use of processing equipment than traditional lot-based procedures.
  • the invention is described as being -12- implemented in a single assembly step 82 for ease of understanding, the invention more typically is implemented on a series of assembly steps.
  • a data store 88 Before or after the IC devices progress through the assembly step 82, their lead frame ID codes are read and stored in a data store 88.
  • data related to the assembly step 82 is generated for each IC device. Such data may include, for example, the processing equipment used, the operating personnel present, the set-up, and the time and date of processing for the assembly step 82.
  • the set-up for the assembly step 82 may include, for example, a standard set-up or a set-up in accordance with a Special Work Request (SWR) or a "hot" lot.
  • SWR Special Work Request
  • the processed IC devices are output from the assembly step 82 to mixed output lots 90. It should be understood that in some cases the processed IC devices must be cleared from assembly equipment before other IC devices can be processed, and in other cases, such as in serial-feed machines, processed IC devices are being output from the assembly step 82 while other IC devices are advancing through the assembly step 82 and still other IC devices are being received by the assembly step 82. Any of these cases fall within the scope of the invention.
  • the inventive method 80 avoids the need for lot-based manufacturing altogether.
  • the input and output lots 86 and 90 may then be mixed without regard to lots, and the processing of IC devices through the assembly step 82 may proceed in a substantially continuous fashion, thus dramatically improving the utilization of processing equipment.
  • the inventive method is more reliable than conventional tracking procedures (i.e. , it eliminates the need for lot travelers).

Abstract

An inventive method tracks IC devices through the assembly steps in a manufacturing process (62). Prior to die attach, a laser scribe marks the lead frame of each of the devices (66) with a coded hole matrix that gives each device a unique ID code. During die attach, an optical hole reader retrieves the ID code of each of the IC devices (66), and a computer system stores the retrieved ID codes in association with the lot numbers of the IC's attached to the lead frames (68). The ID codes of the devices are then read at each step in assembly so the devices can be tracked through assembly individually, rather than by lots. As a result, the devices can proceed through assembly in a more efficient, continuous manner (i.e., without breaks between lots).

Description

-1-
NON-LOT BASED METHOD FOR ASSEMBLING INTEGRATED CIRCUIT DEVICES
TECHNICAL FIELD This invention relates in general to methods for manufacturing integrated circuit (IC) devices. More specifically, the invention relates to non-lot based IC device manufacturing methods in which individual devices can be uniquely identified during their assembly, which enables individual tracking of the devices through assembly and, in turn, enables assembly of the devices in a substantially continuous manner.
BACKGROUND ART As shown in FIG. 1, a process 10 for manufacturing integrated circuit (IC) devices typically begins with ICs being fabricated on the surfaces of wafers 12 of semiconductor material, such as silicon. Less typically, ICs may also be formed in layers of silicon deposited on layers of sapphire (known as Silicon-on-Sapphire (SOS)), insulating material (SOI), or glass (SOG).
Once fabricated, ICs are electronically probed to determine whether they are functional (i.e. , "good") or nonfunctional (i.e. , "bad"). A computer then stores electronic wafer maps 14 of the wafers 12 identifying the locations of the good and bad ICs on the wafers 12.
After being probed, ICs are sawed from their wafers 12 into discrete IC dice (also known as "chips") using high-speed precision dicing equipment. IC dice identified as good by their wafer maps 14 are then each "picked" by automated equipment from their sawed wafers 12 and "placed" on an epoxy coated bonding site of one of a set of lead frames 16, while IC dice identified as bad are discarded into a scrap bin 18. The epoxy attaching the good IC dice to their lead frames 16 is allowed to cure, and the attached dice are then wire bonded to their lead frames 16 using high speed bonding equipment. At this point in the process 10, the lead frames 16 of IC dice are still interconnected.
Once wire bonded, IC dice and their lead frames 16 are formed into IC packages using a hot thermosetting plastic encapsulant injected into a mold. Leads of the lead frames 16 project from the IC packages after encapsulation, and these leads -2- are dipped in a cleansing chemical bath in a process referred to as "de-flash. " After de-flash, IC packages are cured to set their plastic encapsulant, and their projecting leads are then electroplated with a lead/tin finish.
After lead finishing, connections between the lead frames 16 of different IC packages are cut to "singulate" the IC packages into discrete IC devices, and the leads projecting from each IC device are then trimmed and formed into their final form. The IC devices are then tested in a simple electronic test that checks for "opens" (i.e. , no connection) in the devices where connections should exist and "shorts" (i.e. , a connection) where connections should not exist. Devices that fail the opens/shorts test are discarded into the scrap bin 18, and devices that pass proceed to extensive back-end test procedures where they are tested for functionality before being shipped to customers.
ICs are typically tracked by lot number through the fabrication, probe, assembly, and back-end test steps described above so the location of particular lots of ICs within the manufacturing process 10 can be determined. Lot numbers are first assigned to ICs when they are fabricated on semiconductor wafers 12. Typically, a group of 20-50 wafers 12 receive a unique lot number (e.g. , 36/1/9970). As the group of wafers 12 proceeds to probe, the wafers 12 are typically split into several sub-lots, with each sub-lot being assigned a new lot number (sometimes referred to as a "sub-lot" number) that is a modified form of the group's original lot number (e.g. , 36/1/9970/0, 36/1/9970/1, . . . ). As the group continues through the manufacturing process 10, sub-lots are split and re-split for a variety of reasons until the group is typically split into many sub-lots, all having a unique lot number that is a modified form of the group's original lot number. An example of ICs being tracked through a portion of assembly using lot numbers is shown in FIG. 2. In the example, ICs are first processed on molding equipment to encapsulate them. Once encapsulated, ICs are fed into output carriers 20, each of which has a unique carrier number (e.g. , a bar code). The lot number of ICs fed into a particular output carrier 20 are stored in association with the carrier number of the carrier 20 in a data store 22, such as a computer memory system. The output carriers 20 containing the encapsulated ICs are then placed on shelves, with the carrier number of each carrier 20 being stored in the data store 22 in -3- association with a unique shelf number of the shelf on which the carrier 20 is placed (e.g. , by scanning in the bar code of each carrier 20 and a bar code of the shelf on which it is placed). Later, selected ICs are retrieved by lot from the shelves for processing on de-flash equipment by first identifying the carriers 20 associated in the data store 22 with the lot number of the selected ICs, then identifying the shelves associated in the data store 22 with the carrier numbers of the identified carriers 20, and finally retrieving the identified carriers 20 from the identified shelves for processing.
Unfortunately, the conventional lot-based tracking procedure described above is not as efficient as desired, as is illustrated by FIG. 3. In a typical assembly step 24, a sub-lot (e.g. , sub-lot H) is received from an input queue 26 where sub-lots wait to proceed through the assembly step 24. The assembly step 24 may be any step in the IC assembly process of FIG. 1 , including, for example, wafer saw, die attach, die cure, wire bond, molding, de-flash, lead finish, trim and form, and opens/shorts testing.
As a sub-lot advances through the assembly step 24, data 28 related to the assembly step 24 is generated. Such data 28 may include, for example: an identification of the processing equipment and the operating personnel for the assembly step 24; information regarding the set-up of the assembly step 24; and the time and date the sub-lot advanced through the assembly step 24.
Once a sub-lot has advanced through the assembly step 24, a process report 30 is manually or automatically generated based on the generated data 28. To associate the report 30, and hence the data 28, with the ICs in the sub-lot, and thus track the ICs through the assembly step 24, the report 30 lists the lot number (e.g. , "H") of the ICs in the sub-lot. Typically, the report 30 (often referred to as a "lot traveler") also physically accompanies the sub-lot through the remainder of the manufacturing process to ensure that the data 28 is correlated with the ICs in the sub-lot.
With the report 30 generated, a processed sub-lot (e.g. , sub-lot H) is cleared from equipment associated with the assembly step 24 to an output queue 32 to prepare the assembly step 24 for processing the next sub-lot (e.g. , sub-lot I). Once the processed sub-lot is cleared, the next sub-lot can be processed. This "clearing" process is necessary because if two sub-lots (e.g. , sub-lots H and I) proceed through -4- the assembly step 24 in a continuous manner, the conventional lot-based tracking procedure described above is unable to correlate the data 28 and the process report 30 generated as each of the two sub-lots proceed with the correct sub-lot. Instead, the data 28 for the two sub-lots is mixed, causing the conventional tracking procedure to fail to uniquely track the two sub-lots through the assembly step 24.
Thus, the described conventional lot-based tracking procedure is inefficient because it makes inefficient use of often very expensive manufacturing equipment and other resources by leaving sub-lots "parked" in input queues while process reports are generated and the equipment is cleared of already processed sub-lots. In assembly steps which use multiple machines in parallel to process a sub-lot (e.g. , wire bond), some machines may be idle while other machines finish their allotment from the sub- lot being processed and the next sub-lot waits in an input queue. In addition, generation of the process reports, as well as clearing a processed sub-lot from equipment, often requires laborious manual work by operating personnel. Also, the conventional tracking procedure is not as reliable as desired, because the process reports that must physically accompany sub-lots through the manufacturing process can be lost or damaged.
As described in U.S. Patent No. 's 5,301,143, 5,294,812, and 5,103,166, some non-lot based methods have been devised to aid quality control personnel in tracking ICs undergoing failure analysis back to the wafer from which they come. By tracking the ICs back to their wafer, test data related to the ICs can be correlated to the wafer to pinpoint possible problems with the wafer. Such methods take place off the manufacturing line, and involve the use of electrically retrievable identification (ID) codes, such as so-called "fuse ID's, " programmed into individual ICs to identify the ICs. Fuse ID's and other electrically retrievable ID codes are typically programmed into ICs by blowing selected fuses or anti-fuses in circuitry on the ICs so that the circuitry outputs the ID code when accessed. Unfortunately, none of these methods addresses the inefficiency and reliability problems associated with the conventional lot-based tracking procedure described above. Therefore, there is a need in the art for a non-lot based procedure for tracking
ICs through an IC assembly process that uses manufacturing resources more efficiently. Such a procedure should not leave equipment idle while ICs wait to be -5- processed. In addition, such a procedure should achieve a level of reliability not reached by conventional tracking procedures.
DISCLOSURE OF INVENTION A tracking method in accordance with the invention tracks integrated circuit
(IC) devices through the assembly steps in an IC device manufacturing process. The method is applicable to a variety of IC devices including, for example, lead frame devices, Chip-on-Board (COB) devices, flip-chip devices, Single In-Line Memory Modules (SIMMs), Dual In-Line Memory Modules (DIMMs), and Multi-Chip Modules (MCMs). Each of the IC devices includes a mounting substrate, such as a lead frame or a printed circuit (PC) board, on which a substantially unique mounting substrate identification (ID) code is marked. This ID code may be, for example, a bar code, an Optical Character Recognition (OCR) code, or, preferably, a coded hole matrix laser scribed into the substrate. In the inventive method, the ID codes of the IC devices are read using, for example, a bar code reader, OCR reader, or optical hole reader, and the IC devices are advanced through at least one of the assembly steps in the manufacturing process in a substantially continuous manner (i.e. , without a break between lots). While the IC devices advance, they generate data related to the assembly step, such as data identifying particular equipment used during the step and the time and date each device advanced through the step. This data is then associated with the ID code of each of the IC devices to which it pertains (preferably by storing the data in a computer memory system) so the progress of individual devices can be tracked through the manufacturing process.
Because the invention provides for the tracking of individual IC devices during assembly, it allows the processing of IC devices without regard to lots, and thus substantially eliminates the inefficiencies associated with the conventional lot-based tracking methods previously described. Also, the invention provides a more reliable tracking method because it eliminates the need for lot travelers to accompany IC devices through the manufacturing process. Tracking continuity between fabrication, probe, assembly, and back-end testing can be maintained in a number of ways. For example, at die attach (an assembly step), the mounting substrate ID codes of the IC devices can be stored in -6- association with lot numbers, wafer numbers, or fuse IDs used during fabrication and probe. Also, at opens/shorts testing (another assembly step), for example, lot numbers can be assigned to groups of the IC devices, or fuse IDs of individual devices can be stored in association with the mounting substrate ID codes of the devices.
In another embodiment of the invention, a locating method can locate an individual IC device on a manufacturing line. In the method, mounting substrates of each of the IC devices are each marked with a substantially unique, optically-readable mounting substrate ID code. Then, when one of the devices is processed on an assembly machine, the ID code of the device is read and stored in association with a machine ID code of the machine. Also, when one of the devices is stored in an IC device carrier, such as a magazine, the ID code of the device is read and stored in association with a carrier ID number of the carrier. The carrier ID numbers of carriers storing IC devices are then read and stored in association with a location code identifying the location of the carriers on the manufacturing line. This location code may specify, for example, that a carrier is mounted to feed IC devices to a particular machine, mounted to receive processed IC devices from a particular machine, or stored in a particular storage location, such as a shelf or bin. Then, in order to locate an individual IC device on the manufacturing line, it is a simple matter of accessing the mounting substrate ID code of the device to be located and tracking the device to a particular machine, or to a particular carrier mounted on a machine or stored in a storage location.
BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a flow diagram illustrating a conventional lot-based integrated circuit
(IC) manufacturing process;
FIG. 2 is a flow diagram illustrating a portion of the conventional lot-based process of FIG. 1 in more detail;
FIG. 3 is a flow diagram illustrating some of the inefficiencies of the conventional lot-based process of FIG. 1; -7-
FIG. 4 is a diagram illustrating an IC, an IC device, an assembly machine, an IC device carrier, a shelf, and a bin having identification (ID) codes and location codes associated therewith in accordance with the invention;
FIGS. 5 A and 5B are flow diagrams of a method for assembling IC devices in accordance with the invention; and
FIG. 6 is a flow diagram illustrating processing efficiencies gained by using the inventive method of FIGS. 5 A and 5B.
BEST MODE FOR CARRYING OUT THE INVENTION Some general concepts of the invention will be described with reference to
FIG. 4 to aid in understanding the invention. This description of general concepts will be followed by a detailed description of the illustrated embodiments of the invention, with reference made to FIGS. 5 A, 5B, and 6.
As shown in FIG. 4, in an integrated circuit (IC) device manufacturing process conducted in accordance with a preferred embodiment of the invention, an IC 40 has at least one identification (ID) number, such as a lot number, a wafer number, or a fuse ID code, during fabrication and probe. This ID number allows the IC 40 to be tracked through fabrication and probe.
During assembly, the IC 40 is assembled into an IC device 42 that includes a lead frame 44 laser scribed with a coded hole matrix that gives the IC device 42 a substantially unique, optically readable lead frame ID code. This lead frame ID code allows the IC device 42 to be individually tracked through assembly. In order to provide tracking continuity from fabrication through assembly, at die attach the lead frame ID code is stored in a computer system (not shown) in association with the ID number of the IC 40. As a result, the IC device 42, and the IC 40 from which it is formed, can be tracked from fabrication through assembly by referring to the unique lead frame ID code of the device 42. To provide tracking continuity from assembly into back-end testing, the lead frame ID code of the IC device 42 can be correlated at the opens/shorts testing step to a fuse ID code of the device 42 used during back-end testing, for example, or IC devices coming out of assembly can be bundled into lots for processing by lot during back-end testing. Of course, back-end ID codes other than fuse ID codes and lot numbers can be used in association with the invention. -8-
So that the IC device 42 may be individually located within assembly, the machines 46 that assemble the device 42, the IC device carriers 48 that store the device 42, and the shelves 50 or bins 52 that store the carriers 48 each have a unique ID number. In addition, the carriers 48 and the IC device 42 each have a location code that identifies their respective locations. The location code of the IC device 42 may, for example, indicate that the device 42 is located in a particular carrier 48, or that the device 42 is being processed on a particular machine 46. Similarly, the location code of the carrier 48 may, for example, indicate that the carrier 48 is mounted at the input to a particular machine 46, mounted at the output of the machine 46, or stored on a particular shelf 50 or in a particular bin 52. By constantly updating these location codes during assembly, the IC device 42 can be located at any time within assembly by referring to the lead frame ID number of the device 42, which points the way to the machine 46, shelf 50, or bin 52 at which the device 42 is located. As shown in FIG. 5 A, an inventive method 60 for tracking IC devices through assembly begins at the die attach step 62 after the probe step has generated wafer maps 64 as previously described and the wafers (not shown) have been diced at the wafer saw step. It should be understood by those having skill in the field of this invention that the invention is applicable to any IC devices, including, for example, Dynamic Random Access Memories (DRAMs), Static RAMs (SRAMs), Synchronous DRAMs (SDRAMs), processors, Application Specific ICs (ASICs), Read Only Memories (ROMs), Electrically Erasable Programmable ROMs (EEPROMs), flip- chip IC devices, Chip-on-Board (COB) IC devices, lead frame IC devices, Single In- Line Memory Modules (SIMMs), Dual In-Line Memory Modules (DIMMs), and Multi-Chip Modules (MCMs). Also, although the invention will be described with respect to ICs fabricated on semiconductor wafers, it should be understood that the invention is also applicable to ICs fabricated using other technologies, such as Silicon-on-Sapphire (SOS), Silicon-on-Insulator (SOI), and Silicon-on-Glass (SOG). Further, it should be understood that the inventive method 60 may begin tracking IC devices at a step within assembly that is later than the die attach step 62, but that the die attach step 62 is a convenient step in which to begin such tracking. -9-
The ICs (not shown) are provided to the die attach step 62 from the wafer saw step in lots identified by lot numbers. In accordance with the invention, at the die attach step 62 the lot numbers of the lots are scanned using a bar code scanner. Of course, other means may also be used to retrieve the lot numbers. Also, it should be understood that the invention is not limited to working with ICs initially identified by lot numbers but, rather, works equally well with ICs initially identified by any front- end ID code, including, for example, a wafer ID number or a fuse ID code.
Lead frames 66 used during assembly are each marked in accordance with the invention with a substantially unique lead frame ID code. Preferably, this "marking" process is performed by a laser scribe that produces a coded hole matrix in the rail of each of the lead frames 66, which provides a lead frame ID code that should be readable throughout the various steps of assembly. Of course, other methods may be used for marking, including the use of bar codes or Optical Character Recognition (OCR) codes. Also, although the invention will be described with respect to lead frames, it should be understood that the invention is equally applicable to IC devices manufactured on mounting substrates other than lead frames, such as printed circuit (PC) boards, where bar codes or OCR codes may be more suitable. Further, it should be understood that, as used to describe the lead frame ID codes, "substantially unique" means sufficiently unique for each of the codes to be unique amongst those IC devices currently being manufactured. Thus, for example, in some instances a lead frame ID code of a previously manufactured IC device might be used again at a later date with an IC device then being manufactured.
With the lead frames 66 each marked with a lead frame ID code, the lead frames 66 are fed into the die attach step 62 and the lead frame ID code of each lead frame 66 is read using an optical hole reader (not shown). Of course, when the ID code is a bar or OCR code, a bar code reader or OCR reader will be used to read the ID codes of the lead frames 66 instead. A conventional Cycle Redundancy Check (CRC) may be used during reading to enhance the accuracy of the reading.
Once the lead frame ID codes are read, the ICs are each attached to one of the lead frames 66 and the lot number of each of the ICs is stored in a data store 68 in association with the lead frame ID code of the lead frame 66 to which each IC is attached. Data related to the die attach step 62, such as a machine ID number of -10- equipment used during the step 62 and the date and time of processing through the step 62, is also stored in the data store 68 in association with the lead frame ID codes. Of course, at the die attach step 62 any ICs identified by the wafer maps 64 as being bad are diverted to repair/scrap 70. Also, as previously described with respect to FIG. 4, the IC devices each have an associated location code. Thus, during the die attach step 62 the location codes of the IC devices are stored in the data store 68 in association with the lead frame ID codes of the devices, and the location codes identify the location of the devices as being in-process on the die attach equipment (not shown). Preferably, the data store 68 employs local data distribution and buffering techniques so that a failure of a central portion of the computer system (not shown) does not impact the local storage and use of data in the data store 68 along the manufacturing line.
Once the ICs are attached to the lead frames 66, the resulting IC devices are output from the die attach equipment and stored in carriers 72, such as IC device magazines or tubes. As described previously with respect to FIG. 4, the carriers 72 each have an associated carrier ID number (e.g. , a bar code) and location code stored in the data store 68. Because the carriers 72 are mounted at the output of the die attach equipment, the location codes of the carriers 72 indicate this. At the same time, as the IC devices exit the die attach equipment, the location codes of the devices are updated in the data store 68 to indicate that the IC devices are located in particular carriers 72. If the IC devices have to be stored before proceeding to the next step in assembly, the carriers 72 are stored on a shelf (not shown) or in a bin (not shown), and the location codes of the carriers 72 are updated in the date store 68 to indicate their location at a particular shelf having a shelf ID number or in a particular bin having a bin ID number.
As shown in FIG. 5B, when the carriers 72 (FIG. 5 A) are ready to be processed at another step within assembly, such as die cure, wire bond, molding, de- flash, lead finish, trim and form, or opens/shorts testing, an operator retrieves the carriers 72 from their storage location, at which point the carriers 72 are disassociated in the data store 68 with the storage location. Of course, if the carriers 72 proceed in a continuous manner between assembly steps then the operator -11- would retrieve the carriers 72 from the previous step rather than from a storage location.
Once retrieved, the carriers 72 are loaded on the processing equipment of the next assembly step, and the location codes of the carriers 72 are updated in the data store 68 to indicate the new location of the carriers 72. The IC devices are then fed into the equipment from the carriers 72, the lead frame ID codes of the devices are read using an optical hole reader mounted on the equipment, and the location codes of the devices are updated in the data store 68 to indicate they are in-process on the equipment. The devices are then checked to verify they are supposed to be processed in the assembly step. If any of the devices are found to be at the equipment in error, or are found to be scrap, the devices are diverted to repair/scrap 70. Otherwise, the devices are processed on the equipment and process-related data, such as time and date of processing, is generated and stored in the data store 68 in association with the previously read lead frame ID codes of the devices. The devices are then fed out of the equipment into new carriers 74, with the location codes of the carriers 74 being updated in the data store 68 to indicate the carriers 74 are mounted at the output of the equipment, and the location codes of the IC devices being updated in the data store 68 to indicate their location in particular carriers 74. If the carriers 74 are to be stored prior to being processed at the next assembly step, the carriers 74 are stored on a shelf or in a bin in a manner similar to that described above with respect to FIG. 5A.
As described, the invention provides superior tracking and efficiency, as is illustrated by FIG. 6. As shown therein, a method 80 for tracking IC devices through an assembly step 2 in an IC manufacturing process in accordance with the invention includes a step 84 of receiving IC devices from multiple, mixed lots 86. It will be understood by those having skill in the field of this invention that the step 82 may encompass processing by a single machine, part of a machine, many machines operating in series or parallel, or any combination thereof. In addition, it will be understood that the step 84 of receiving IC devices from multiple, mixed lots 86 is without regard to the lots from which the IC devices come, and thus allows a more efficient use of processing equipment than traditional lot-based procedures. It will also be understood, of course, that although the invention is described as being -12- implemented in a single assembly step 82 for ease of understanding, the invention more typically is implemented on a series of assembly steps.
Before or after the IC devices progress through the assembly step 82, their lead frame ID codes are read and stored in a data store 88. As the IC devices progress through the assembly step 82, data related to the assembly step 82 is generated for each IC device. Such data may include, for example, the processing equipment used, the operating personnel present, the set-up, and the time and date of processing for the assembly step 82. The set-up for the assembly step 82 may include, for example, a standard set-up or a set-up in accordance with a Special Work Request (SWR) or a "hot" lot.
Once the IC devices have advanced through the assembly step 82, the processed IC devices are output from the assembly step 82 to mixed output lots 90. It should be understood that in some cases the processed IC devices must be cleared from assembly equipment before other IC devices can be processed, and in other cases, such as in serial-feed machines, processed IC devices are being output from the assembly step 82 while other IC devices are advancing through the assembly step 82 and still other IC devices are being received by the assembly step 82. Any of these cases fall within the scope of the invention.
It should be understood that by reading the lead frame ID codes of processed IC devices and associating those codes with data generated during processing, the inventive method 80 avoids the need for lot-based manufacturing altogether. The input and output lots 86 and 90 may then be mixed without regard to lots, and the processing of IC devices through the assembly step 82 may proceed in a substantially continuous fashion, thus dramatically improving the utilization of processing equipment. In addition, because the lead frame ID codes and associated data read and generated using the inventive method need not physically accompany ICs as they progress through the manufacturing process, the inventive method is more reliable than conventional tracking procedures (i.e. , it eliminates the need for lot travelers). Although the present invention has been described with reference to particular embodiments, the invention is not limited to these described embodiments. Rather, the invention is limited only by the appended claims, which include within their scope -13- all equivalent methods that operate according to the principles of the invention as described.

Claims

-14-CLAIMSWe claim:
1. A method in an integrated circuit (IC) device manufacturing process for tracking multiple lots of IC devices through an assembly step in the process, each of the IC devices including a mounting substrate on which is marked a substantially unique mounting substrate identification (ID) code, the method comprising: reading the mounting substrate ID code of each of the IC devices in each of the multiple lots; advancing the IC devices in the multiple lots through the assembly step in the manufacturing process in a substantially continuous manner; generating data related to the advancement of each of the IC devices through the assembly step; and associating the data generated for each of the IC devices with the mounting substrate ID code of its associated IC device so the multiple lots of IC devices may be tracked through the assembly step.
2. The method of claim 1 wherein each of the IC devices includes a mounting substrate selected from a group comprising a lead frame and a printed circuit board, wherein each of the IC devices is selected from a group comprising lead frame IC devices, Chip-on-Board (COB) IC devices, and flip-chip IC devices.
3. The method of claim 1 wherein the mounting substrate of each of the IC devices is marked with a unique, optically retrievable mounting substrate ID code, wherein the step of reading the mounting substrate ID code of each of the IC devices comprises optically retrieving the mounting substrate ID code of each of the IC devices.
4. The method of claim 3 wherein each optically retrievable mounting substrate ID code comprises one of a bar code, an Optical Character Recognition (OCR) code, and a coded hole matrix, wherein the step of optically retrieving the mounting substrate ID code of each of the IC devices comprises retrieving the code of -15- each of the devices with one of a bar code reader, an OCR reader, and an optical hole reader.
5. The method of claim 1 wherein the assembly step in the IC device manufacturing process comprises one of die attach, die cure, wire bond, molding, de- flash, lead finish, trim and form, and opens/shorts testing.
6. The method of claim 1 wherein the step of reading the mounting substrate ID code of each of the IC devices occurs before the step of advancing the IC devices through the assembly step in the manufacturing process.
7. The method of claim 1 wherein the step of advancing the IC devices through the assembly step in the manufacturing process comprises advancing the IC devices serially through multiple machines associated with the assembly step.
8. The method of claim 1 wherein the step of advancing the IC devices through the assembly step in the manufacturing process comprises advancing the IC devices through parallel machines associated with the assembly step.
9. The method of claim 1 wherein the step of generating data related to the advancement of each of the IC devices through the assembly step comprises generating at least one of assembly equipment data, assembly personnel data, assembly set-up data, and time and date data.
10. The method of claim 1, further comprising the step of storing the mounting substrate ID code of each of the IC devices after it is read, wherein the step of associating the data generated for each of the IC devices with the mounting substrate ID code of its associated IC device comprises storing the data generated for each of the IC devices in association with the stored mounting substrate ID code of its associated IC device. -16-
11. The method of claim 10 wherein the step of storing the data generated for each of the IC devices in association with the stored mounting substrate ID code of its associated IC device comprises storing the data in a decentralized manner within a computer system so at least partial access to the stored data may continue during a failure of a centralized portion of the computer system.
12. A method of manufacturing integrated circuit (IC) devices, the method comprising: providing a plurality of fabrication substrates in multiple lots; fabricating a plurality of ICs on each of the fabrication substrates; separating each of the ICs on each of the fabrication substrates from its fabrication substrate to form one of a plurality of IC dice; providing a plurality of mounting substrates, each marked with a substantially unique mounting substrate identification (ID) code; reading a front-end ID code associated with each of the IC dice; reading the mounting substrate ID code marked on each of the mounting substrates; attaching each of the IC dice to one of the mounting substrates to form one of a plurality of IC devices; storing the front-end ID code of each of the IC dice in each of the IC devices in association with the mounting substrate ID code of the mounting substrate to which each of the IC dice is attached; advancing each of the IC devices through assembly; while advancing the IC devices through assembly; advancing the IC devices through at least one assembly step in a substantially continuous manner; generating data related to the advancement of each of the IC devices through the assembly step; and associating the data generated for each of the IC devices with the mounting substrate ID code of the mounting substrate of each device so the devices may be tracked through the assembly step; and back-end testing each of the IC devices. -17-
13. The method of claim 12, further comprising: storing a back-end ID code of each of the IC devices in association with the mounting substrate ID code of the mounting substrate to which each of the IC dice is attached; and storing back-end testing-related data for each of the IC devices in association with the back-end ID code of each of the devices so the devices may be tracked through back-end testing.
14. The method of claim 13 wherein the step of storing a back-end ID code of each of the IC devices comprises storing at least one of a fuse ID code and a lot number.
15. The method of claim 13 wherein the front-end and back-end ID codes associated with each of the IC devices are identical.
16. The method of claim 12 wherein the step of providing the fabrication substrates comprises providing substrates selected from a group comprising semiconductor wafers, Silicon-on-Sapphire (SOS) substrates, Silicon-on-Insulator (SOI) substrates, and Silicon-on-Glass (SOG) substrates.
17. The method of claim 12 wherein the step of fabricating a plurality of ICs on each of the fabrication substrates comprises fabricating ICs selected from a group comprising Dynamic Random Access Memory (DRAM) ICs, Static Random Access Memory (SRAM) ICs, Synchronous DRAM (SDRAM) ICs, processor ICs, Application Specific ICs (ASICs), Read Only Memory (ROM) ICs, and Electrically Erasable Programmable ROM (EEPROM) ICs.
18. The method of claim 12, further comprising the step of programming each of the ICs on each of the fabrication substrates to permanently store a substantially unique fuse ID code, wherein the step of reading a front-end ID code associated with each of the IC dice comprises reading the fuse ID code programmed into the IC of each of the IC dice. -18-
19. The method of claim 18 wherein the step of programming each of the ICs on each of the fabrication substrates to permanently store a substantially unique fuse ID code comprises programming at least one of fuses and anti-fuses in each of the ICs on each of the fabrication substrates to permanently store each substantially unique fuse ID.
20. The method of claim 12 wherein the step of providing the mounting substrates includes marking each of the mounting substrates with an optically readable, substantially unique mounting substrate ID code selected from a group comprising a bar code, an Optical Character Recognition (OCR) code, and a coded hole matrix.
21. The method of claim 20 wherein each of the mounting substrates comprises one of a plurality of lead frames, wherein the step of marking each of the mounting substrates comprises laser scribing a coded hole matrix in a lead frame rail of each of the lead frames.
22. The method of claim 12 wherein the step of reading a front-end ID code associated with each of the IC dice comprises reading at least one of a lot number, a wafer number, and a fuse ID code associated with each of the IC dice.
23. The method of claim 12 wherein the step of reading the mounting substrate ID code marked on each of the mounting substrates comprises reading the mounting substrate ID codes with at least one of a bar code reader, an Optical Character Recognition (OCR) reader, and an optical hole reader.
24. The method of claim 12 wherein the step of reading the mounting substrate ID code includes verifying the mounting substrate ID code using a Cycle Redundancy Check (CRC).
25. The method of claim 12 wherein the step of providing the mounting substrates comprises providing at least one of lead frames and printed circuit boards. -19-
26. The method of claim 12, further comprising the step of verifying that the IC devices are supposed to progress through the assembly step before advancing the IC devices through the assembly step.
27. The method of claim 12 wherein the step of attaching the IC dice comprises attaching the dice using at least one of a Chip-on-Board (COB) technique and a flip-chip technique.
28. A method of manufacturing multi-chip integrated circuit (IC) devices, the method comprising: providing a plurality of fabrication substrates in multiple lots; fabricating a plurality of ICs on each of the fabrication substrates; separating each of the ICs on each of the fabrication substrates from its fabrication substrate to form one of a plurality of IC dice; providing a plurality of mounting substrates, each marked with a substantially unique mounting substrate identification (ID) code; reading a front-end ID code associated with each of the IC dice; reading the mounting substrate ID code marked on each of the mounting substrates; attaching more than one of the IC dice to each of the mounting substrates to form a plurality of multi-chip IC devices; storing the front-end ID code of each of the IC dice in each of the multi-chip IC devices in association with the mounting substrate ID code of the mounting substrate to which each of the IC dice is attached; advancing each of the multi-chip IC devices through assembly; while advancing the multi-chip IC devices through assembly; advancing the multi-chip IC devices through at least one assembly step in a substantially continuous manner; generating data related to the advancement of each of the multi-chip IC devices through the assembly step; and associating the data generated for each of the multi-chip IC devices with the mounting substrate ID code of the mounting substrate of -20- each device so the devices may be tracked through the assembly step; and back-end testing each of the multi-chip IC devices.
29. The method of claim 28, further comprising: storing a back-end ID code of each of the IC dice in each of the multi-chip IC devices in association with the mounting substrate ID code of the mounting substrate to which each of the IC dice is attached; and storing back-end testing-related data for each of the IC devices in association with the back-end ID code of each of the IC dice so the dice may be tracked through back-end testing.
30. The method of claim 28 wherein the step of attaching more than one of the IC dice to each of the mounting substrates to form a plurality of multi-chip IC devices comprises attaching more than one of the IC dice to each of the mounting substrates to form a plurality of multi-chip IC devices selected from a group comprising Single In-Line Memory Modules (SIMMs), Dual In-Line Memory Modules (DIMMs), Multi-Chip Modules (MCMs), and multi-chip printed circuit (PC) boards.
31. A method of locating an individual integrated circuit (IC) device on an IC device manufacturing line on which a multitude of IC devices are being manufactured, the method comprising: marking a mounting substrate of each of the IC devices with a substantially unique, optically-readable mounting substrate identification (ID) code; when one of the IC devices is being processed by an assembly-related machine, reading the mounting substrate ID code of the IC device and storing the code in association with a machine ID number of the assembly-related machine; when one of the IC devices is stored in an IC device carrier, reading the mounting substrate ID code of the IC device and storing the code in association with a carrier ID number of the device carrier; -21- reading the carrier ID numbers of IC device carriers in which IC devices are stored and storing the carrier ID numbers in association with a location code identifying the location of the carriers on the manufacturing line; and when an individual IC device is stored in an IC device carrier, locating the individual IC device on the manufacturing line by accessing the carrier ID number stored in association with the mounting substrate ID code of the individual IC device and by accessing the location code stored in association with the accessed carrier ID number; and when an individual IC device is being processed by an assembly-related machine, locating the individual IC device on the manufacturing line by accessing the machine ID number stored in association with the mounting substrate ID code of the individual IC device.
32. The method of claim 31 wherein the step of reading the carrier ID numbers comprises reading carrier bar codes.
33. The method of claim 31 wherein the step of storing the carrier ID numbers in association with a location code identifying the location of the carriers on the manufacturing line comprises storing the carrier ID numbers in association with a location code identifying the location of the carriers as being a location selected from a group comprising on a storage shelf, in a storage bin, mounted to feed IC devices into an assembly-related machine, and mounted to receive processed IC devices from an assembly-related machine.
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001067386A1 (en) * 2000-03-06 2001-09-13 Siemens Aktiengesellschaft Electronic component containing indelible information, set comprising several components of this type, a method for packing a component of this type and a method for packing all components of a corresponding set
WO2004075267A1 (en) * 2003-02-20 2004-09-02 Hitachi High-Technologies Corporation Semiconductor device and semiconductor production management system
NL2019504A (en) * 2016-09-08 2018-03-13 Mapper Lithography Ip Bv Secure chips with serial numbers
NL2020162A (en) * 2016-12-23 2018-07-02 Mapper Lithography Ip Bv Secure chips with serial numbers
US10079206B2 (en) 2016-10-27 2018-09-18 Mapper Lithography Ip B.V. Fabricating unique chips using a charged particle multi-beamlet lithography system
US10522472B2 (en) 2016-09-08 2019-12-31 Asml Netherlands B.V. Secure chips with serial numbers

Families Citing this family (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6100486A (en) 1998-08-13 2000-08-08 Micron Technology, Inc. Method for sorting integrated circuit devices
US5927512A (en) * 1997-01-17 1999-07-27 Micron Technology, Inc. Method for sorting integrated circuit devices
US5844803A (en) * 1997-02-17 1998-12-01 Micron Technology, Inc. Method of sorting a group of integrated circuit devices for those devices requiring special testing
US5915231A (en) 1997-02-26 1999-06-22 Micron Technology, Inc. Method in an integrated circuit (IC) manufacturing process for identifying and redirecting IC's mis-processed during their manufacture
US5856923A (en) 1997-03-24 1999-01-05 Micron Technology, Inc. Method for continuous, non lot-based integrated circuit manufacturing
US7120513B1 (en) * 1997-06-06 2006-10-10 Micron Technology, Inc. Method for using data regarding manufacturing procedures integrated circuits (ICS) have undergone, such as repairs, to select procedures the ICS will undergo, such as additional repairs
US5907492A (en) * 1997-06-06 1999-05-25 Micron Technology, Inc. Method for using data regarding manufacturing procedures integrated circuits (IC's) have undergone, such as repairs, to select procedures the IC's will undergo, such as additional repairs
US6049624A (en) * 1998-02-20 2000-04-11 Micron Technology, Inc. Non-lot based method for assembling integrated circuit devices
US6760472B1 (en) * 1998-12-14 2004-07-06 Hitachi, Ltd. Identification method for an article using crystal defects
US6200823B1 (en) * 1999-02-09 2001-03-13 Advanced Micro Devices, Inc. Method for isolation of optical defect images
US6483334B1 (en) * 2000-09-28 2002-11-19 United Microelectronics Corp. Method for reliability testing of semiconductor IC
US6469384B2 (en) 2001-02-01 2002-10-22 Fairchild Semiconductor Corporation Unmolded package for a semiconductor device
US6931298B1 (en) 2001-02-27 2005-08-16 Cypress Semiconductor Corporation Integrated back-end integrated circuit manufacturing assembly
US6901984B1 (en) * 2001-02-27 2005-06-07 Cypress Semiconductor Corporation Method and system for controlling the processing of an integrated circuit chip assembly line using a central computer system and a common communication protocol
MY127433A (en) * 2001-05-29 2006-12-29 Integrated Device Tech Die bonding apparatus with automatic die and lead frame image matching system.
US6601008B1 (en) * 2001-08-02 2003-07-29 Lsi Logic Corporation Parametric device signature
US6792365B2 (en) * 2001-08-10 2004-09-14 Micron Technology, Inc. Sequential unique marking
JP3870780B2 (en) * 2001-12-21 2007-01-24 ヤマハ株式会社 Manufacturing method of semiconductor device
US7840803B2 (en) * 2002-04-16 2010-11-23 Massachusetts Institute Of Technology Authentication of integrated circuits
WO2003091290A1 (en) * 2002-04-23 2003-11-06 Boehringer Ingelheim Pharmaceuticals, Inc. Method for reduction of residual organic solvent in carbomer
US7668702B2 (en) * 2002-07-19 2010-02-23 Applied Materials, Inc. Method, system and medium for controlling manufacturing process using adaptive models based on empirical data
DE10259049A1 (en) * 2002-12-17 2004-07-15 Infineon Technologies Ag Integrated semiconductor module
US20050096782A1 (en) * 2003-10-30 2005-05-05 T-Chun Chen Automated sorter system and method thereof
WO2005052705A1 (en) * 2003-11-28 2005-06-09 Matsushita Electric Industrial Co., Ltd. Circuit substrate manufacturing method and system, substrate used for the same, and circuit substrate using the same
US7415317B2 (en) * 2004-02-25 2008-08-19 Micron Technology, Inc. Method and system for correlating and combining production and non-production data for analysis
US7395130B2 (en) * 2004-02-27 2008-07-01 Micron Technology, Inc. Method and system for aggregating and combining manufacturing data for analysis
US7105377B1 (en) * 2004-04-13 2006-09-12 Cypress Semiconductor Corporation Method and system for universal packaging in conjunction with a back-end integrated circuit manufacturing process
US7134599B2 (en) * 2004-06-09 2006-11-14 Inventec Appliances Corp. Circuit board inspection apparatus
JP2008517465A (en) * 2004-10-15 2008-05-22 アプライド マテリアルズ インコーポレイテッド Die level tracking mechanism for semiconductor assembly and test facilities.
KR100674950B1 (en) * 2005-01-22 2007-01-26 삼성전자주식회사 Semiconductor wafer including reference semiconductor chip and method of semiconductor chip assembly using the same
US7622313B2 (en) * 2005-07-29 2009-11-24 Freescale Semiconductor, Inc. Fabrication of three dimensional integrated circuit employing multiple die panels
US20070050075A1 (en) * 2005-08-26 2007-03-01 Electro Scientific Industries, Inc. Automatic wafer tracking process and apparatus for carrying out the process
US7684608B2 (en) * 2006-02-23 2010-03-23 Vistech Corporation Tape and reel inspection system
TW200807425A (en) * 2006-06-05 2008-02-01 Renesas Tech Corp Semiconductor device, unique ID of semiconductor device and method for verifying unique ID
TWI322645B (en) * 2006-12-20 2010-03-21 Nan Ya Printed Circuit Board Corp Lot traceable printed circuit board
US7494846B2 (en) * 2007-03-09 2009-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. Design techniques for stacking identical memory dies
US20090288057A1 (en) * 2008-05-15 2009-11-19 Texas Instruments Incorporated System and Method for Ordering the Selection of Integrated Circuit Chips
DE102009015496A1 (en) * 2009-03-30 2010-10-07 Siemens Electronics Assembly Systems Gmbh & Co. Kg Method for detecting and tracking elements to be loaded
US20100274717A1 (en) * 2009-04-22 2010-10-28 Shaun Wright Global Internet Based Method and System For Compiling, Assigning, Registration, and Maintenance of Unique Tags
JP5315186B2 (en) 2009-09-18 2013-10-16 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
US20110156033A1 (en) * 2009-12-31 2011-06-30 Stmicroelectronics Asia Pacific Pte. Ltd. Method and system for tracing die at unit level
CN104952487B (en) * 2010-01-14 2018-03-27 旺宏电子股份有限公司 A kind of method for operating multi-chip package device
US8377747B2 (en) 2010-04-21 2013-02-19 Texas Instruments Incorporated Interleaf for leadframe identification
KR101785618B1 (en) 2012-02-02 2017-11-06 삼성전자주식회사 A method for searching the position of multi sim mobile station
JP5970948B2 (en) * 2012-05-11 2016-08-17 凸版印刷株式会社 Production management system and production management method
JP5968705B2 (en) * 2012-07-13 2016-08-10 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
JP2013157626A (en) * 2013-04-11 2013-08-15 Renesas Electronics Corp Semiconductor device manufacturing method
JP2015114814A (en) * 2013-12-11 2015-06-22 株式会社デンソー Product history management method of semiconductor device
JP6223583B2 (en) * 2014-09-01 2017-11-01 三菱電機株式会社 Semiconductor device, semiconductor chip, and characteristic information management method for semiconductor chip
US11771139B2 (en) 2020-01-13 2023-10-03 Altria Client Services Llc Non-nicotine electronic vaping device with memory module
US11666100B2 (en) 2020-01-13 2023-06-06 Altria Client Services Llc Nicotine electronic vaping device

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4454413A (en) * 1982-02-19 1984-06-12 Precision Monolithics, Inc. Apparatus for tracking integrated circuit devices
US4510673A (en) * 1983-06-23 1985-04-16 International Business Machines Corporation Laser written chip identification method
US4985988A (en) * 1989-11-03 1991-01-22 Motorola, Inc. Method for assembling, testing, and packaging integrated circuits
US5294812A (en) * 1990-09-14 1994-03-15 Kabushiki Kaisha Toshiba Semiconductor device having identification region for carrying out failure analysis
US5399531A (en) 1990-12-17 1995-03-21 United Micrpelectronics Corporation Single semiconductor wafer transfer method and plural processing station manufacturing system
JPH09229999A (en) * 1996-02-27 1997-09-05 Toshiba Microelectron Corp Test handler for semiconductor device
US5801067A (en) * 1993-10-27 1998-09-01 Ronald Shaw Method for recording and identifying integrated circuit chips and the like

Family Cites Families (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US535295A (en) * 1895-03-05 Filter
US4032949A (en) 1975-05-15 1977-06-28 Raytheon Company Integrated circuit fusing technique
US4027246A (en) * 1976-03-26 1977-05-31 International Business Machines Corporation Automated integrated circuit manufacturing system
US4150331A (en) 1977-07-29 1979-04-17 Burroughs Corporation Signature encoding for integrated circuits
DE3036869C2 (en) 1979-10-01 1985-09-05 Hitachi, Ltd., Tokio/Tokyo Semiconductor integrated circuit and circuit activation method
US4534014A (en) 1983-06-20 1985-08-06 Ames Oliver C Mechanically programmable read only memory
US4667403A (en) 1984-05-16 1987-05-26 Siemens Aktiengesellschaft Method for manufacturing electronic card modules
US4967381A (en) 1985-04-30 1990-10-30 Prometrix Corporation Process control interface system for managing measurement data
IT1201837B (en) 1986-07-22 1989-02-02 Sgs Microelettronica Spa SYSTEM FOR VERIFYING THE FUNCTIONALITY AND CHARACTERISTICS OF SEMICONDUCTOR-TYPE EPROM DEVICES DURING THE "BURN-IN"
JPH0671038B2 (en) 1987-03-31 1994-09-07 株式会社東芝 Crystal defect recognition processing method
JPH0616475B2 (en) 1987-04-03 1994-03-02 三菱電機株式会社 Article manufacturing system and article manufacturing method
US5440240A (en) 1991-06-04 1995-08-08 Micron Technology, Inc. Z-axis interconnect for discrete die burn-in for nonpackaged die
US4954453A (en) 1989-02-24 1990-09-04 At&T Bell Laboratories Method of producing an article comprising a multichip assembly
US5289113A (en) * 1989-08-01 1994-02-22 Analog Devices, Inc. PROM for integrated circuit identification and testing
US5003251A (en) * 1989-09-12 1991-03-26 Grumman Aerospace Corporation Bar code reader for printed circuit board
KR920007535B1 (en) 1990-05-23 1992-09-05 삼성전자 주식회사 Semconductor integrated circuit having a test circuit
US5347463A (en) * 1990-07-03 1994-09-13 Honda Giken Kogyo Kabushiki Kaisha System and method for line production management
US5043657A (en) * 1990-07-13 1991-08-27 Analog Devices, Incorporated Marking techniques for identifying integrated circuit parts at the time of testing
JP2907971B2 (en) * 1990-08-14 1999-06-21 株式会社東芝 Method for forming or testing semiconductor device pattern
US5495417A (en) 1990-08-14 1996-02-27 Kabushiki Kaisha Toshiba System for automatically producing different semiconductor products in different quantities through a plurality of processes along a production line
US5118369A (en) * 1990-08-23 1992-06-02 Colorcode Unlimited Corporation Microlabelling system and process for making microlabels
US5219765A (en) 1990-09-12 1993-06-15 Hitachi, Ltd. Method for manufacturing a semiconductor device including wafer aging, probe inspection, and feeding back the results of the inspection to the device fabrication process
US5197650A (en) * 1990-09-18 1993-03-30 Sharp Kabushiki Kaisha Die bonding apparatus
US5175774A (en) * 1990-10-16 1992-12-29 Micron Technology, Inc. Semiconductor wafer marking for identification during processing
US5570293A (en) 1990-11-29 1996-10-29 Tokyo Seimitsu Co., Ltd. Method and device for manufacturing a semiconductor chip
JPH0574909A (en) * 1990-12-17 1993-03-26 Asia Electron Inc Wafer test method
US5256562A (en) 1990-12-31 1993-10-26 Kopin Corporation Method for manufacturing a semiconductor device using a circuit transfer film
US5226118A (en) 1991-01-29 1993-07-06 Prometrix Corporation Data analysis system and method for industrial process control systems
JP2653566B2 (en) 1991-03-27 1997-09-17 株式会社東芝 Semiconductor substrate evaluation method and apparatus
KR970000501B1 (en) 1991-04-12 1997-01-13 Hyundai Electronics Ind Semiconductor memory device with redundancy confirmative circuit
US5235550A (en) 1991-05-16 1993-08-10 Micron Technology, Inc. Method for maintaining optimum biasing voltage and standby current levels in a DRAM array having repaired row-to-column shorts
US5110754A (en) 1991-10-04 1992-05-05 Micron Technology, Inc. Method of making a DRAM capacitor for use as an programmable antifuse for redundancy repair/options on a DRAM
JPH05121521A (en) 1991-10-29 1993-05-18 Komatsu Electron Metals Co Ltd Apparatus and method for manufacture of semiconductor wafer
KR950000099B1 (en) * 1991-11-12 1995-01-09 삼성전자 주식회사 Position recognizing method for semiconductor device by binary coding method
US5326709A (en) 1991-12-19 1994-07-05 Samsung Electronics Co., Ltd. Wafer testing process of a semiconductor device comprising a redundancy circuit
US5256578A (en) 1991-12-23 1993-10-26 Motorola, Inc. Integral semiconductor wafer map recording
US5355320A (en) 1992-03-06 1994-10-11 Vlsi Technology, Inc. System for controlling an integrated product process for semiconductor wafers and packages
US5457400A (en) 1992-04-10 1995-10-10 Micron Technology, Inc. Semiconductor array having built-in test circuit for wafer level testing
US5442561A (en) 1992-05-12 1995-08-15 Nippon Telegraph And Telephone Corporation Production management system and its application method
US5424652A (en) 1992-06-10 1995-06-13 Micron Technology, Inc. Method and apparatus for testing an unpackaged semiconductor die
KR960013508B1 (en) 1992-07-07 1996-10-05 현대전자산업 주식회사 Semiconductor device having thin film transistor & method of manufacturing the same
JP3659981B2 (en) * 1992-07-09 2005-06-15 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド Apparatus comprising integrated circuits on a die characterized by die specific information
US5301143A (en) * 1992-12-31 1994-04-05 Micron Semiconductor, Inc. Method for identifying a semiconductor die using an IC with programmable links
JP3309478B2 (en) * 1993-02-26 2002-07-29 ソニー株式会社 Chip management system, input processing method and lot processing method thereof, and chip manufacturing method using chip management system
US5352945A (en) 1993-03-18 1994-10-04 Micron Semiconductor, Inc. Voltage compensating delay element
US5345110A (en) 1993-04-13 1994-09-06 Micron Semiconductor, Inc. Low-power fuse detect and latch circuit
JP2880876B2 (en) 1993-04-15 1999-04-12 山口日本電気株式会社 Transfer control system
US5360747A (en) * 1993-06-10 1994-11-01 Xilinx, Inc. Method of reducing dice testing with on-chip identification
US5428311A (en) 1993-06-30 1995-06-27 Sgs-Thomson Microelectronics, Inc. Fuse circuitry to control the propagation delay of an IC
JPH0729999A (en) 1993-07-15 1995-01-31 Mitsubishi Electric Corp Nonvolatile semiconductor memory device and its manufacturing method
US5399505A (en) 1993-07-23 1995-03-21 Motorola, Inc. Method and apparatus for performing wafer level testing of integrated circuit dice
JP2727930B2 (en) 1993-10-04 1998-03-18 日本電気株式会社 Boundary scan test circuit
JPH07122099A (en) 1993-10-29 1995-05-12 Nec Corp Semiconductor memory
DE4338445A1 (en) 1993-11-10 1995-05-11 Heraeus Voetsch Gmbh Method and device for temperature control and testing of electronic, electromechanical and mechanical assemblies
JP2776247B2 (en) 1993-11-17 1998-07-16 日本電気株式会社 Semiconductor integrated circuit and manufacturing method thereof
JP2616413B2 (en) 1993-11-22 1997-06-04 日本電気株式会社 Repair data editing device and repair data editing method
US5420796A (en) 1993-12-23 1995-05-30 Vlsi Technology, Inc. Method of inspecting planarity of wafer surface after etchback step in integrated circuit fabrication
JPH07201946A (en) 1993-12-28 1995-08-04 Hitachi Ltd Manufacture of semiconductor device and apparatus for manufacture the same, testing of the same and testing apparatus
JPH07307388A (en) 1994-02-04 1995-11-21 Advanced Micro Devices Inc Array of transistor and its formation
US5511005A (en) 1994-02-16 1996-04-23 Ade Corporation Wafer handling and processing system
US5625816A (en) 1994-04-05 1997-04-29 Advanced Micro Devices, Inc. Method and system for generating product performance history
JPH0817198A (en) 1994-06-28 1996-01-19 Mitsubishi Denki Semiconductor Software Kk Method for testing flash memory
US6075216A (en) * 1994-06-30 2000-06-13 Advantest Corp. Device transfer and reinspection method for IC handler
US5450326A (en) 1994-07-06 1995-09-12 Harris Corporation Graphical display discriminant factor indicator for anomaly identification in semiconductor manufacture batch process
US5654204A (en) * 1994-07-20 1997-08-05 Anderson; James C. Die sorter
US5538141A (en) 1994-09-27 1996-07-23 Intel Corporation Test flow assurance using memory imprinting
US5606193A (en) 1994-10-03 1997-02-25 Sharp Kabushiki Kaisha DRAM and MROM cells with similar structure
US5590069A (en) 1994-10-17 1996-12-31 Qualcomm Incorporated Method and apparatus for providing ROM in an integrated circuit having update through single substance layer modification capability
JP2755195B2 (en) 1994-12-08 1998-05-20 日本電気株式会社 Semiconductor device manufacturing method and device
KR0144711B1 (en) 1994-12-13 1998-08-17 김광호 Test control circuit and method of semiconductor memory apparatus
US5865319A (en) 1994-12-28 1999-02-02 Advantest Corp. Automatic test handler system for IC tester
US5991699A (en) 1995-05-04 1999-11-23 Kla Instruments Corporation Detecting groups of defects in semiconductor feature space
KR0147194B1 (en) 1995-05-26 1998-11-02 문정환 Semiconductor memory device
US5787190A (en) 1995-06-07 1998-07-28 Advanced Micro Devices, Inc. Method and apparatus for pattern recognition of wafer test bins
US5828778A (en) 1995-07-13 1998-10-27 Matsushita Electric Industrial Co., Ltd. Method and apparatus for analyzing failure of semiconductor wafer
US5963881A (en) 1995-09-22 1999-10-05 Texas Instruments Incorporated Method and system for enhancing the identification of causes of variations in the performance of manufactured articles
DE19540348B4 (en) * 1995-10-28 2007-01-11 Micronas Gmbh Method for identifying components
US5787012A (en) * 1995-11-17 1998-07-28 Sun Microsystems, Inc. Integrated circuit with identification signal writing circuitry distributed on multiple metal layers
KR100189180B1 (en) * 1996-05-28 1999-06-01 오우라 히로시 Separation type handler system for ic tester
US6194738B1 (en) * 1996-06-13 2001-02-27 Micron Technology, Inc. Method and apparatus for storage of test results within an integrated circuit
US5895962A (en) * 1996-06-13 1999-04-20 Micron Technology, Inc. Structure and a method for storing information in a semiconductor device
US6138256A (en) * 1998-03-27 2000-10-24 Micron Technology, Inc. Intelligent binning for electrically repairable semiconductor chips
US5764650A (en) 1996-08-02 1998-06-09 Micron Technology, Inc. Intelligent binning for electrically repairable semiconductor chips
US5867505A (en) 1996-08-07 1999-02-02 Micron Technology, Inc. Method and apparatus for testing an integrated circuit including the step/means for storing an associated test identifier in association with integrated circuit identifier for each test to be performed on the integrated circuit
US5898186A (en) 1996-09-13 1999-04-27 Micron Technology, Inc. Reduced terminal testing system
US5927512A (en) 1997-01-17 1999-07-27 Micron Technology, Inc. Method for sorting integrated circuit devices
US6100486A (en) * 1998-08-13 2000-08-08 Micron Technology, Inc. Method for sorting integrated circuit devices
US6072574A (en) * 1997-01-30 2000-06-06 Micron Technology, Inc. Integrated circuit defect review and classification process
US5844803A (en) * 1997-02-17 1998-12-01 Micron Technology, Inc. Method of sorting a group of integrated circuit devices for those devices requiring special testing
US5915231A (en) * 1997-02-26 1999-06-22 Micron Technology, Inc. Method in an integrated circuit (IC) manufacturing process for identifying and redirecting IC's mis-processed during their manufacture
US5856923A (en) * 1997-03-24 1999-01-05 Micron Technology, Inc. Method for continuous, non lot-based integrated circuit manufacturing
US6000830A (en) 1997-04-18 1999-12-14 Tokyo Electron Limited System for applying recipe of semiconductor manufacturing apparatus
KR100216066B1 (en) 1997-05-20 1999-08-16 윤종용 Control system and control method for ic test process
US5907492A (en) * 1997-06-06 1999-05-25 Micron Technology, Inc. Method for using data regarding manufacturing procedures integrated circuits (IC's) have undergone, such as repairs, to select procedures the IC's will undergo, such as additional repairs
US6018686A (en) 1997-10-31 2000-01-25 Cypress Semiconductor Corp. Electrically imprinting a semiconductor die with identifying information
US5837558A (en) * 1997-11-04 1998-11-17 Texas Instruments Incorporated Integrated circuit chip packaging method
US6049624A (en) 1998-02-20 2000-04-11 Micron Technology, Inc. Non-lot based method for assembling integrated circuit devices
US6265232B1 (en) * 1998-08-21 2001-07-24 Micron Technology, Inc. Yield based, in-line defect sampling method
DE10034878C2 (en) * 2000-07-18 2003-12-04 Infineon Technologies Ag Method for checking a component and component with test memory

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4454413A (en) * 1982-02-19 1984-06-12 Precision Monolithics, Inc. Apparatus for tracking integrated circuit devices
US4510673A (en) * 1983-06-23 1985-04-16 International Business Machines Corporation Laser written chip identification method
US4985988A (en) * 1989-11-03 1991-01-22 Motorola, Inc. Method for assembling, testing, and packaging integrated circuits
US5294812A (en) * 1990-09-14 1994-03-15 Kabushiki Kaisha Toshiba Semiconductor device having identification region for carrying out failure analysis
US5399531A (en) 1990-12-17 1995-03-21 United Micrpelectronics Corporation Single semiconductor wafer transfer method and plural processing station manufacturing system
US5801067A (en) * 1993-10-27 1998-09-01 Ronald Shaw Method for recording and identifying integrated circuit chips and the like
JPH09229999A (en) * 1996-02-27 1997-09-05 Toshiba Microelectron Corp Test handler for semiconductor device
US5805472A (en) * 1996-02-27 1998-09-08 Kabushiki Kaisha Toshiba Test handler for semiconductor devices

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
FRESONKE D: "IN-FAB IDENTIFICATION OF SILICON WAFERS WITH CLEAN LASER MARKED BARCODES", IEEE/SEMI ADVANCED SEMICONDUCTOR MANUFACTURING CONFERENCE ANDWORKSHOP., XX, XX, 1 November 1994 (1994-11-01), XX, pages 157 - 160, XP002918188 *
See also references of EP1062618A4

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001067386A1 (en) * 2000-03-06 2001-09-13 Siemens Aktiengesellschaft Electronic component containing indelible information, set comprising several components of this type, a method for packing a component of this type and a method for packing all components of a corresponding set
WO2004075267A1 (en) * 2003-02-20 2004-09-02 Hitachi High-Technologies Corporation Semiconductor device and semiconductor production management system
EP2063456A3 (en) * 2003-02-20 2009-12-09 Hitachi High-Technologies Corporation Semiconductor manufacturing management system
US10714427B2 (en) 2016-09-08 2020-07-14 Asml Netherlands B.V. Secure chips with serial numbers
US10522472B2 (en) 2016-09-08 2019-12-31 Asml Netherlands B.V. Secure chips with serial numbers
NL2019504A (en) * 2016-09-08 2018-03-13 Mapper Lithography Ip Bv Secure chips with serial numbers
US11004800B2 (en) 2016-09-08 2021-05-11 Asml Netherlands B.V. Secure chips with serial numbers
US11688694B2 (en) 2016-09-08 2023-06-27 Asml Netherlands B.V. Secure chips with serial numbers
US10079206B2 (en) 2016-10-27 2018-09-18 Mapper Lithography Ip B.V. Fabricating unique chips using a charged particle multi-beamlet lithography system
US10418324B2 (en) 2016-10-27 2019-09-17 Asml Netherlands B.V. Fabricating unique chips using a charged particle multi-beamlet lithography system
US10600733B2 (en) 2016-10-27 2020-03-24 Asml Netherlands B.V. Fabricating unique chips using a charged particle multi-beamlet lithography system
US11152302B2 (en) 2016-10-27 2021-10-19 Asml Netherlands B.V. Fabricating unique chips using a charged particle multi-beamlet lithography system
NL2020162A (en) * 2016-12-23 2018-07-02 Mapper Lithography Ip Bv Secure chips with serial numbers
EP3559980A4 (en) * 2016-12-23 2020-10-28 ASML Netherlands B.V. Secure chips with serial numbers

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US20010021265A1 (en) 2001-09-13
US6226394B1 (en) 2001-05-01
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US20040005090A1 (en) 2004-01-08
KR20010034519A (en) 2001-04-25
US6400840B2 (en) 2002-06-04
KR100417751B1 (en) 2004-02-11
JP4008198B2 (en) 2007-11-14
US20070086644A1 (en) 2007-04-19
EP1062618A4 (en) 2006-01-25
JP2003524873A (en) 2003-08-19
US20020110270A1 (en) 2002-08-15
US6588854B2 (en) 2003-07-08
AU2481699A (en) 1999-09-06
US6049624A (en) 2000-04-11

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