WO1999043002A3 - Preserving loop fairness with dynamic half-duplex - Google Patents

Preserving loop fairness with dynamic half-duplex Download PDF

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Publication number
WO1999043002A3
WO1999043002A3 PCT/US1999/003955 US9903955W WO9943002A3 WO 1999043002 A3 WO1999043002 A3 WO 1999043002A3 US 9903955 W US9903955 W US 9903955W WO 9943002 A3 WO9943002 A3 WO 9943002A3
Authority
WO
WIPO (PCT)
Prior art keywords
channel
predetermined amount
preserving
fairness
loop
Prior art date
Application number
PCT/US1999/003955
Other languages
French (fr)
Other versions
WO1999043002A2 (en
Inventor
Michael H Miller
Judy Lynn Westby
Original Assignee
Seagate Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seagate Technology filed Critical Seagate Technology
Priority to GB0018845A priority Critical patent/GB2349319B/en
Priority to DE19982971T priority patent/DE19982971T1/en
Priority to JP2000532850A priority patent/JP4076724B2/en
Publication of WO1999043002A2 publication Critical patent/WO1999043002A2/en
Publication of WO1999043002A3 publication Critical patent/WO1999043002A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L12/5602—Bandwidth control in ATM Networks, e.g. leaky bucket
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/42—Loop networks
    • H04L12/427—Loop networks with decentralised control
    • H04L12/433—Loop networks with decentralised control with asynchronous transmission, e.g. token ring, register insertion

Abstract

A method and apparatus for preserving loop fairness. Some embodiments include a dynamic half-duplex feature. One aspect includes a communications channel system and method for preserving loop fairness that includes a first channel node having one or more ports, each port supporting and attached to a fibre-channel arbitrated-loop serial communications channel. One of the ports will arbitrate for control of that port's attached channel, wherein control of the channel loop, once arbitration is won, a fairness-preserving apparatus causes control of the communications channel to be released based at least in part on whether a predetermined amount of use has occurred between the first port and the communications channel. In some embodiments, the predetermined amount of use includes a transfer of a first predetermined amount of data. In some embodiments, release of control of the channel is inhibited if less than a second predetermined amount of data remains to be transferred.
PCT/US1999/003955 1998-02-24 1999-02-24 Preserving loop fairness with dynamic half-duplex WO1999043002A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
GB0018845A GB2349319B (en) 1998-02-24 1999-02-24 Preserving loop fairness with dynamic half-duplex
DE19982971T DE19982971T1 (en) 1998-02-24 1999-02-24 Preserve loop fairness with dynamic half-duplex operation
JP2000532850A JP4076724B2 (en) 1998-02-24 1999-02-24 Maintaining loop fairness with dynamic half-duplex

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US7579798P 1998-02-24 1998-02-24
US60/075,797 1998-02-24

Publications (2)

Publication Number Publication Date
WO1999043002A2 WO1999043002A2 (en) 1999-08-26
WO1999043002A3 true WO1999043002A3 (en) 1999-10-28

Family

ID=22128043

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1999/003955 WO1999043002A2 (en) 1998-02-24 1999-02-24 Preserving loop fairness with dynamic half-duplex

Country Status (7)

Country Link
US (2) US6061360A (en)
JP (1) JP4076724B2 (en)
KR (1) KR100607392B1 (en)
CN (1) CN1309849A (en)
DE (1) DE19982971T1 (en)
GB (1) GB2349319B (en)
WO (1) WO1999043002A2 (en)

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Also Published As

Publication number Publication date
US6553036B1 (en) 2003-04-22
JP2002504765A (en) 2002-02-12
GB0018845D0 (en) 2000-09-20
KR20010086257A (en) 2001-09-10
DE19982971T1 (en) 2001-02-15
US6061360A (en) 2000-05-09
GB2349319B (en) 2003-05-28
WO1999043002A2 (en) 1999-08-26
GB2349319A (en) 2000-10-25
JP4076724B2 (en) 2008-04-16
CN1309849A (en) 2001-08-22
KR100607392B1 (en) 2006-08-02

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